vivado 和 modesim 联合仿真快速修改重仿

vivado与modelsim的联合仿真(一)_坚持-CSDN博客_modelsim和vivado

1 编译联合仿真库 tool → compile_simulation_libraries ，选择simulator 为 modelsim simulator，填写好 compiled library location(联合库存放地址)，simulator executable path (modelsim.exe 地址)

2 setting里面simulation选项，选择 target simulator 为 modelsim，编译库设置为第1步的存放位置。

设置好后点击 run simulation 即可

安装后联合仿真跑不起来的原因：

0 .v中有错误，错误信息会在 vivado的 tcl console窗口中说明

1 查看下环境变量 PATH中有没有modelsim的路径

2 vivado setting中将 3rd party simulators的路径设置一下看是否有用

联合仿真使用建议：

modelsim中的两个操作：do wave.do 和combine signals - FPGA/ASIC技术 - 电子发烧友网

1 在重新加载后还有一个麻烦事是信号要重新往modelsim的波形窗口里面添加一遍，这个很麻烦，do wave.do就是来解决这一麻烦的。

要执行这一命令，首先在上次把信号往波形窗口里面添加好后，单击一下波形窗口的信号，执行一下操作File----Save Format...命令，或者直接点击工具栏中左上角的保存

执行以上命令后，默认保存为wave.do，当然wave这个名字可以随意更改的。

保存好后，在下次加载了 vivado 的程序后，执行do wave.do就可以把上次已经添加到波形窗口的信号自动添加过去，很方便，很省事。

需要说明的是，do wave.do命令等价于File---Load...操作，当然，改了保存的名字那你就找你保存的那个.do文件就行。

2 在vivado中联合使用modelsim中仿真时，经常要修改了vivado里面的程序然后重新仿真，重新加载程序可以使用以下方法来重新加载而不必每次关掉modelsim在vivado中重新打开

1> 在自己制作的 xxx.do 文件中，复制添加vivado生成的 编译命令 prj \ prj.sim \ sim_1\ behav \ modelsim \ tb_preload_top_compile.do，去掉最后的强制退出命令quit -force

2> 在自己制作的 xxx.do 文件中，复制添加vivado生成的 仿真命令 prj \ prj.sim \ sim_1\ behav \ modelsim \ tb_preload_top_simulate.do

3> 在自己制作的 xxx.do 文件中, 添加1保存的波形信息 do wave.do，然后添加 run 1ms 命令

4> 直接打开modelsim，change_dir 到 prj \ prj.sim \ sim_1\ behav \ modelsim （compile.do所在的文件夹），然后 do xxx.do 即可，如果要添加或者删除文件，记得修改compile.do部分的包含内容

xxx.do 的一个示例如下：

######################################################################
#
# File name : tb_preload_top_wave.do
# Created on: Tue Jun 08 13:44:44 +0800 2021
#
# Auto generated by Vivado for 'behavioral' simulation
#
######################### tb_preload_top_compile.do #############################################vlib modelsim_lib/work
vlib modelsim_lib/msimvlib modelsim_lib/msim/xil_defaultlibvmap xil_defaultlib modelsim_lib/msim/xil_defaultlibvlog -64 -incr -work xil_defaultlib  "+incdir+../../../../../rtl/pre_load" "+incdir+../../../../../rtl/pre_load/sim" \
"../../../../../rtl/pre_load/ip/fifo128to128/sim/fifo128to128.v" \
"../../../../../rtl/pre_load/ip/fifo256to128/sim/fifo256to128.v" \
"../../../../../rtl/pre_load/preload_top.v" \
"../../../../../rtl/pre_load/sim/tb_preload_top.v" \# compile glbl module
vlog -work xil_defaultlib "glbl.v"######################### tb_preload_top_simulate.do #############################################vsim -voptargs="+acc" -L fifo_generator_v13_2_4 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -L xpm -lib xil_defaultlib xil_defaultlib.tb_preload_top xil_defaultlib.glblset NumericStdNoWarnings 1
set StdArithNoWarnings 1do {tb_preload_top_wave.do}view wave
view structure
view signalsdo {tb_preload_top.udo}######################### usr #############################################do {I:\ATE_prj\IOPE_prj\rtl\pre_load\sim\preload_wave.do}run 1ms

方案2

直接在modelsim中添加 .v 文件

添加库参考：在ModelSim中添加Xilinx仿真库 - Craftor - 博客园

即修改 .ini 文件，一劳永逸，

具体内容可以copy某个vivado工程中的 prj.sim -- sim_1 -- behav -- modelsim --modelsim.ini中的下面内容

secureip = D:/modelsim10.05/Vivado2019.1_jiont/secureip
unisim = D:/modelsim10.05/Vivado2019.1_jiont/unisim
unimacro = D:/modelsim10.05/Vivado2019.1_jiont/unimacro
unifast = D:/modelsim10.05/Vivado2019.1_jiont/unifast
unisims_ver = D:/modelsim10.05/Vivado2019.1_jiont/unisims_ver
unimacro_ver = D:/modelsim10.05/Vivado2019.1_jiont/unimacro_ver
unifast_ver = D:/modelsim10.05/Vivado2019.1_jiont/unifast_ver
simprims_ver = D:/modelsim10.05/Vivado2019.1_jiont/simprims_ver
xpm = D:/modelsim10.05/Vivado2019.1_jiont/xpm
xilinx_vip = D:/modelsim10.05/Vivado2019.1_jiont/xilinx_vip
advanced_io_wizard_phy_v1_0_0 = D:/modelsim10.05/Vivado2019.1_jiont/advanced_io_wizard_phy_v1_0_0
advanced_io_wizard_v1_0_0 = D:/modelsim10.05/Vivado2019.1_jiont/advanced_io_wizard_v1_0_0
ahblite_axi_bridge_v3_0_14 = D:/modelsim10.05/Vivado2019.1_jiont/ahblite_axi_bridge_v3_0_14
ai_noc = D:/modelsim10.05/Vivado2019.1_jiont/ai_noc
ai_pl_trig = D:/modelsim10.05/Vivado2019.1_jiont/ai_pl_trig
ai_pl = D:/modelsim10.05/Vivado2019.1_jiont/ai_pl
audio_clock_recovery_v1_0 = D:/modelsim10.05/Vivado2019.1_jiont/audio_clock_recovery_v1_0
audio_tpg_v1_0_0 = D:/modelsim10.05/Vivado2019.1_jiont/audio_tpg_v1_0_0
av_pat_gen_v1_0_0 = D:/modelsim10.05/Vivado2019.1_jiont/av_pat_gen_v1_0_0
axis_infrastructure_v1_1_0 = D:/modelsim10.05/Vivado2019.1_jiont/axis_infrastructure_v1_1_0
axis_protocol_checker_v2_0_3 = D:/modelsim10.05/Vivado2019.1_jiont/axis_protocol_checker_v2_0_3
axi_ahblite_bridge_v3_0_16 = D:/modelsim10.05/Vivado2019.1_jiont/axi_ahblite_bridge_v3_0_16
axi_amm_bridge_v1_0_9 = D:/modelsim10.05/Vivado2019.1_jiont/axi_amm_bridge_v1_0_9
axi_bram_ctrl_v4_1_1 = D:/modelsim10.05/Vivado2019.1_jiont/axi_bram_ctrl_v4_1_1
axi_chip2chip_v5_0_5 = D:/modelsim10.05/Vivado2019.1_jiont/axi_chip2chip_v5_0_5
axi_dbg_hub = D:/modelsim10.05/Vivado2019.1_jiont/axi_dbg_hub
axi_infrastructure_v1_1_0 = D:/modelsim10.05/Vivado2019.1_jiont/axi_infrastructure_v1_1_0
axi_jtag_v1_0_0 = D:/modelsim10.05/Vivado2019.1_jiont/axi_jtag_v1_0_0
axi_lite_ipif_v3_0_4 = D:/modelsim10.05/Vivado2019.1_jiont/axi_lite_ipif_v3_0_4
axi_pcie3_v3_0_9 = D:/modelsim10.05/Vivado2019.1_jiont/axi_pcie3_v3_0_9
axi_perf_mon_v5_0_21 = D:/modelsim10.05/Vivado2019.1_jiont/axi_perf_mon_v5_0_21
axi_pmon_v1_0_0 = D:/modelsim10.05/Vivado2019.1_jiont/axi_pmon_v1_0_0
blk_mem_gen_v8_3_6 = D:/modelsim10.05/Vivado2019.1_jiont/blk_mem_gen_v8_3_6
blk_mem_gen_v8_4_3 = D:/modelsim10.05/Vivado2019.1_jiont/blk_mem_gen_v8_4_3
bsip_v1_1_0 = D:/modelsim10.05/Vivado2019.1_jiont/bsip_v1_1_0
bs_mux_v1_0_0 = D:/modelsim10.05/Vivado2019.1_jiont/bs_mux_v1_0_0
clk_gen_sim_v1_0_0 = D:/modelsim10.05/Vivado2019.1_jiont/clk_gen_sim_v1_0_0
clk_vip_v1_0_2 = D:/modelsim10.05/Vivado2019.1_jiont/clk_vip_v1_0_2
cmac_usplus_v2_4_5 = D:/modelsim10.05/Vivado2019.1_jiont/cmac_usplus_v2_4_5
cmac_usplus_v2_5_1 = D:/modelsim10.05/Vivado2019.1_jiont/cmac_usplus_v2_5_1
cmac_usplus_v2_6_0 = D:/modelsim10.05/Vivado2019.1_jiont/cmac_usplus_v2_6_0
cmac_v2_3_5 = D:/modelsim10.05/Vivado2019.1_jiont/cmac_v2_3_5
cmac_v2_4_1 = D:/modelsim10.05/Vivado2019.1_jiont/cmac_v2_4_1
cmac_v2_5_0 = D:/modelsim10.05/Vivado2019.1_jiont/cmac_v2_5_0
compact_gt_v1_0_5 = D:/modelsim10.05/Vivado2019.1_jiont/compact_gt_v1_0_5
ddr4_pl_phy_v1_0_0 = D:/modelsim10.05/Vivado2019.1_jiont/ddr4_pl_phy_v1_0_0
ddr4_pl_v1_0_2 = D:/modelsim10.05/Vivado2019.1_jiont/ddr4_pl_v1_0_2
dist_mem_gen_v8_0_13 = D:/modelsim10.05/Vivado2019.1_jiont/dist_mem_gen_v8_0_13
ecc_v2_0_13 = D:/modelsim10.05/Vivado2019.1_jiont/ecc_v2_0_13
emb_fifo_gen_v1_0_1 = D:/modelsim10.05/Vivado2019.1_jiont/emb_fifo_gen_v1_0_1
emb_mem_gen_v1_0_1 = D:/modelsim10.05/Vivado2019.1_jiont/emb_mem_gen_v1_0_1
emc_common_v3_0_5 = D:/modelsim10.05/Vivado2019.1_jiont/emc_common_v3_0_5
ethernet_1_10_25g_v2_0_4 = D:/modelsim10.05/Vivado2019.1_jiont/ethernet_1_10_25g_v2_0_4
ethernet_1_10_25g_v2_1_3 = D:/modelsim10.05/Vivado2019.1_jiont/ethernet_1_10_25g_v2_1_3
ethernet_1_10_25g_v2_2_2 = D:/modelsim10.05/Vivado2019.1_jiont/ethernet_1_10_25g_v2_2_2
ethernet_1_10_25g_v2_3_0 = D:/modelsim10.05/Vivado2019.1_jiont/ethernet_1_10_25g_v2_3_0
fifo_generator_v13_0_6 = D:/modelsim10.05/Vivado2019.1_jiont/fifo_generator_v13_0_6
fifo_generator_v13_1_4 = D:/modelsim10.05/Vivado2019.1_jiont/fifo_generator_v13_1_4
fifo_generator_v13_2_4 = D:/modelsim10.05/Vivado2019.1_jiont/fifo_generator_v13_2_4
fit_timer_v2_0_10 = D:/modelsim10.05/Vivado2019.1_jiont/fit_timer_v2_0_10
generic_baseblocks_v2_1_0 = D:/modelsim10.05/Vivado2019.1_jiont/generic_baseblocks_v2_1_0
gigantic_mux = D:/modelsim10.05/Vivado2019.1_jiont/gigantic_mux
gig_ethernet_pcs_pma_v16_1_6 = D:/modelsim10.05/Vivado2019.1_jiont/gig_ethernet_pcs_pma_v16_1_6
gmii_to_rgmii_v4_0_7 = D:/modelsim10.05/Vivado2019.1_jiont/gmii_to_rgmii_v4_0_7
gtwizard_ultrascale_v1_5_4 = D:/modelsim10.05/Vivado2019.1_jiont/gtwizard_ultrascale_v1_5_4
gtwizard_ultrascale_v1_6_11 = D:/modelsim10.05/Vivado2019.1_jiont/gtwizard_ultrascale_v1_6_11
gtwizard_ultrascale_v1_7_6 = D:/modelsim10.05/Vivado2019.1_jiont/gtwizard_ultrascale_v1_7_6
hbm_v1_0_3 = D:/modelsim10.05/Vivado2019.1_jiont/hbm_v1_0_3
hdcp22_cipher_dp_v1_0_0 = D:/modelsim10.05/Vivado2019.1_jiont/hdcp22_cipher_dp_v1_0_0
hdcp22_cipher_v1_0_3 = D:/modelsim10.05/Vivado2019.1_jiont/hdcp22_cipher_v1_0_3
hdcp22_rng_v1_0_1 = D:/modelsim10.05/Vivado2019.1_jiont/hdcp22_rng_v1_0_1
hdcp_keymngmt_blk_v1_0_0 = D:/modelsim10.05/Vivado2019.1_jiont/hdcp_keymngmt_blk_v1_0_0
hdcp_v1_0_3 = D:/modelsim10.05/Vivado2019.1_jiont/hdcp_v1_0_3
hdmi_gt_controller_v1_0_0 = D:/modelsim10.05/Vivado2019.1_jiont/hdmi_gt_controller_v1_0_0
high_speed_selectio_wiz_v3_2_3 = D:/modelsim10.05/Vivado2019.1_jiont/high_speed_selectio_wiz_v3_2_3
high_speed_selectio_wiz_v3_3_1 = D:/modelsim10.05/Vivado2019.1_jiont/high_speed_selectio_wiz_v3_3_1
high_speed_selectio_wiz_v3_4_1 = D:/modelsim10.05/Vivado2019.1_jiont/high_speed_selectio_wiz_v3_4_1
high_speed_selectio_wiz_v3_5_1 = D:/modelsim10.05/Vivado2019.1_jiont/high_speed_selectio_wiz_v3_5_1
i2s_receiver_v1_0_3 = D:/modelsim10.05/Vivado2019.1_jiont/i2s_receiver_v1_0_3
i2s_transmitter_v1_0_3 = D:/modelsim10.05/Vivado2019.1_jiont/i2s_transmitter_v1_0_3
ibert_lib_v1_0_6 = D:/modelsim10.05/Vivado2019.1_jiont/ibert_lib_v1_0_6
ieee802d3_clause74_fec_v1_0_4 = D:/modelsim10.05/Vivado2019.1_jiont/ieee802d3_clause74_fec_v1_0_4
interlaken_v2_4_3 = D:/modelsim10.05/Vivado2019.1_jiont/interlaken_v2_4_3
in_system_ibert_v1_0_9 = D:/modelsim10.05/Vivado2019.1_jiont/in_system_ibert_v1_0_9
iomodule_v3_1_4 = D:/modelsim10.05/Vivado2019.1_jiont/iomodule_v3_1_4
jesd204c_v4_1_0 = D:/modelsim10.05/Vivado2019.1_jiont/jesd204c_v4_1_0
jesd204_v7_2_6 = D:/modelsim10.05/Vivado2019.1_jiont/jesd204_v7_2_6
jtag_axi = D:/modelsim10.05/Vivado2019.1_jiont/jtag_axi
lib_cdc_v1_0_2 = D:/modelsim10.05/Vivado2019.1_jiont/lib_cdc_v1_0_2
lib_pkg_v1_0_2 = D:/modelsim10.05/Vivado2019.1_jiont/lib_pkg_v1_0_2
lmb_bram_if_cntlr_v4_0_16 = D:/modelsim10.05/Vivado2019.1_jiont/lmb_bram_if_cntlr_v4_0_16
lmb_v10_v3_0_9 = D:/modelsim10.05/Vivado2019.1_jiont/lmb_v10_v3_0_9
ltlib_v1_0_0 = D:/modelsim10.05/Vivado2019.1_jiont/ltlib_v1_0_0
lut_buffer_v1_0_0 = D:/modelsim10.05/Vivado2019.1_jiont/lut_buffer_v1_0_0
lut_buffer_v2_0_0 = D:/modelsim10.05/Vivado2019.1_jiont/lut_buffer_v2_0_0
l_ethernet_v2_3_5 = D:/modelsim10.05/Vivado2019.1_jiont/l_ethernet_v2_3_5
l_ethernet_v2_4_1 = D:/modelsim10.05/Vivado2019.1_jiont/l_ethernet_v2_4_1
l_ethernet_v2_5_0 = D:/modelsim10.05/Vivado2019.1_jiont/l_ethernet_v2_5_0
mammoth_transcode_v1_0_0 = D:/modelsim10.05/Vivado2019.1_jiont/mammoth_transcode_v1_0_0
microblaze_v10_0_7 = D:/modelsim10.05/Vivado2019.1_jiont/microblaze_v10_0_7
microblaze_v11_0_1 = D:/modelsim10.05/Vivado2019.1_jiont/microblaze_v11_0_1
microblaze_v9_5_4 = D:/modelsim10.05/Vivado2019.1_jiont/microblaze_v9_5_4
mii_to_rmii_v2_0_21 = D:/modelsim10.05/Vivado2019.1_jiont/mii_to_rmii_v2_0_21
mipi_csi2_rx_ctrl_v1_0_8 = D:/modelsim10.05/Vivado2019.1_jiont/mipi_csi2_rx_ctrl_v1_0_8
mipi_csi2_tx_ctrl_v1_0_4 = D:/modelsim10.05/Vivado2019.1_jiont/mipi_csi2_tx_ctrl_v1_0_4
mipi_dphy_v4_1_3 = D:/modelsim10.05/Vivado2019.1_jiont/mipi_dphy_v4_1_3
mipi_dsi_tx_ctrl_v1_0_7 = D:/modelsim10.05/Vivado2019.1_jiont/mipi_dsi_tx_ctrl_v1_0_7
mrmac_v1_0_0 = D:/modelsim10.05/Vivado2019.1_jiont/mrmac_v1_0_0
multi_channel_25g_rs_fec_v1_0_2 = D:/modelsim10.05/Vivado2019.1_jiont/multi_channel_25g_rs_fec_v1_0_2
mutex_v2_1_10 = D:/modelsim10.05/Vivado2019.1_jiont/mutex_v2_1_10
axi_tg_lib = D:/modelsim10.05/Vivado2019.1_jiont/axi_tg_lib
noc_na_v1_0_0 = D:/modelsim10.05/Vivado2019.1_jiont/noc_na_v1_0_0
noc_nidb_v1_0_0 = D:/modelsim10.05/Vivado2019.1_jiont/noc_nidb_v1_0_0
noc_nmu_v1_0_0 = D:/modelsim10.05/Vivado2019.1_jiont/noc_nmu_v1_0_0
noc_nps_v1_0_0 = D:/modelsim10.05/Vivado2019.1_jiont/noc_nps_v1_0_0
nvmeha_v1_0_0 = D:/modelsim10.05/Vivado2019.1_jiont/nvmeha_v1_0_0
oddr_v1_0_0 = D:/modelsim10.05/Vivado2019.1_jiont/oddr_v1_0_0
pci32_v5_0_12 = D:/modelsim10.05/Vivado2019.1_jiont/pci32_v5_0_12
pci64_v5_0_11 = D:/modelsim10.05/Vivado2019.1_jiont/pci64_v5_0_11
pcie_jtag_v1_0_0 = D:/modelsim10.05/Vivado2019.1_jiont/pcie_jtag_v1_0_0
pc_cfr_v6_0_8 = D:/modelsim10.05/Vivado2019.1_jiont/pc_cfr_v6_0_8
pc_cfr_v6_1_4 = D:/modelsim10.05/Vivado2019.1_jiont/pc_cfr_v6_1_4
pc_cfr_v6_2_2 = D:/modelsim10.05/Vivado2019.1_jiont/pc_cfr_v6_2_2
pc_cfr_v6_3_0 = D:/modelsim10.05/Vivado2019.1_jiont/pc_cfr_v6_3_0
picxo = D:/modelsim10.05/Vivado2019.1_jiont/picxo
qdma_v3_0_1 = D:/modelsim10.05/Vivado2019.1_jiont/qdma_v3_0_1
rama_v1_1_1_lib = D:/modelsim10.05/Vivado2019.1_jiont/rama_v1_1_1_lib
rld3_pl_phy_v1_0_0 = D:/modelsim10.05/Vivado2019.1_jiont/rld3_pl_phy_v1_0_0
rld3_pl_v1_0_1 = D:/modelsim10.05/Vivado2019.1_jiont/rld3_pl_v1_0_1
roe_framer_v2_0_0 = D:/modelsim10.05/Vivado2019.1_jiont/roe_framer_v2_0_0
rst_vip_v1_0_3 = D:/modelsim10.05/Vivado2019.1_jiont/rst_vip_v1_0_3
smartconnect_v1_0 = D:/modelsim10.05/Vivado2019.1_jiont/smartconnect_v1_0
sd_fec_v1_0_2 = D:/modelsim10.05/Vivado2019.1_jiont/sd_fec_v1_0_2
sem_ultra_v3_1_11 = D:/modelsim10.05/Vivado2019.1_jiont/sem_ultra_v3_1_11
sem_v4_1_12 = D:/modelsim10.05/Vivado2019.1_jiont/sem_v4_1_12
shell_utils_msp432_bsl_crc_gen_v1_0_0 = D:/modelsim10.05/Vivado2019.1_jiont/shell_utils_msp432_bsl_crc_gen_v1_0_0
sim_clk_gen_v1_0_2 = D:/modelsim10.05/Vivado2019.1_jiont/sim_clk_gen_v1_0_2
sim_rst_gen_v1_0_2 = D:/modelsim10.05/Vivado2019.1_jiont/sim_rst_gen_v1_0_2
sim_trig_top_v1_0 = D:/modelsim10.05/Vivado2019.1_jiont/sim_trig_top_v1_0
stm_v1_0 = D:/modelsim10.05/Vivado2019.1_jiont/stm_v1_0
stm_v1_0_0 = D:/modelsim10.05/Vivado2019.1_jiont/stm_v1_0_0
system_cache_v4_0_6 = D:/modelsim10.05/Vivado2019.1_jiont/system_cache_v4_0_6
ta_dma_v1_0_3 = D:/modelsim10.05/Vivado2019.1_jiont/ta_dma_v1_0_3
tcc_decoder_3gpplte_v3_0_6 = D:/modelsim10.05/Vivado2019.1_jiont/tcc_decoder_3gpplte_v3_0_6
ten_gig_eth_mac_v15_1_7 = D:/modelsim10.05/Vivado2019.1_jiont/ten_gig_eth_mac_v15_1_7
ten_gig_eth_pcs_pma_v6_0_15 = D:/modelsim10.05/Vivado2019.1_jiont/ten_gig_eth_pcs_pma_v6_0_15
timer_sync_1588_v1_2_4 = D:/modelsim10.05/Vivado2019.1_jiont/timer_sync_1588_v1_2_4
tmr_inject_v1_0_3 = D:/modelsim10.05/Vivado2019.1_jiont/tmr_inject_v1_0_3
tmr_manager_v1_0_4 = D:/modelsim10.05/Vivado2019.1_jiont/tmr_manager_v1_0_4
tmr_voter_v1_0_2 = D:/modelsim10.05/Vivado2019.1_jiont/tmr_voter_v1_0_2
tsn_endpoint_ethernet_mac_block_v1_0_4 = D:/modelsim10.05/Vivado2019.1_jiont/tsn_endpoint_ethernet_mac_block_v1_0_4
uhdsdi_gt_v1_0_3 = D:/modelsim10.05/Vivado2019.1_jiont/uhdsdi_gt_v1_0_3
uhdsdi_gt_v2_0_0 = D:/modelsim10.05/Vivado2019.1_jiont/uhdsdi_gt_v2_0_0
usxgmii_v1_0_5 = D:/modelsim10.05/Vivado2019.1_jiont/usxgmii_v1_0_5
usxgmii_v1_1_0 = D:/modelsim10.05/Vivado2019.1_jiont/usxgmii_v1_1_0
util_idelay_ctrl_v1_0_1 = D:/modelsim10.05/Vivado2019.1_jiont/util_idelay_ctrl_v1_0_1
util_reduced_logic_v2_0_4 = D:/modelsim10.05/Vivado2019.1_jiont/util_reduced_logic_v2_0_4
util_vector_logic_v2_0_1 = D:/modelsim10.05/Vivado2019.1_jiont/util_vector_logic_v2_0_1
ba317 = D:/modelsim10.05/Vivado2019.1_jiont/ba317
versal_cips_v1_0_0 = D:/modelsim10.05/Vivado2019.1_jiont/versal_cips_v1_0_0
vfb_v1_0_13 = D:/modelsim10.05/Vivado2019.1_jiont/vfb_v1_0_13
video_frame_crc_v1_0_1 = D:/modelsim10.05/Vivado2019.1_jiont/video_frame_crc_v1_0_1
vid_edid_v1_0_0 = D:/modelsim10.05/Vivado2019.1_jiont/vid_edid_v1_0_0
vid_phy_controller_v2_1_5 = D:/modelsim10.05/Vivado2019.1_jiont/vid_phy_controller_v2_1_5
vid_phy_controller_v2_2_3 = D:/modelsim10.05/Vivado2019.1_jiont/vid_phy_controller_v2_2_3
v_axi4s_remap_v1_0_11 = D:/modelsim10.05/Vivado2019.1_jiont/v_axi4s_remap_v1_0_11
v_csc_v1_0_13 = D:/modelsim10.05/Vivado2019.1_jiont/v_csc_v1_0_13
v_deinterlacer_v4_0_12 = D:/modelsim10.05/Vivado2019.1_jiont/v_deinterlacer_v4_0_12
v_deinterlacer_v5_0_13 = D:/modelsim10.05/Vivado2019.1_jiont/v_deinterlacer_v5_0_13
v_demosaic_v1_0_5 = D:/modelsim10.05/Vivado2019.1_jiont/v_demosaic_v1_0_5
v_frmbuf_rd_v2_1_2 = D:/modelsim10.05/Vivado2019.1_jiont/v_frmbuf_rd_v2_1_2
v_frmbuf_wr_v2_1_2 = D:/modelsim10.05/Vivado2019.1_jiont/v_frmbuf_wr_v2_1_2
v_gamma_lut_v1_0_5 = D:/modelsim10.05/Vivado2019.1_jiont/v_gamma_lut_v1_0_5
v_hcresampler_v1_0_13 = D:/modelsim10.05/Vivado2019.1_jiont/v_hcresampler_v1_0_13
v_hdmi_rx_v2_0_0 = D:/modelsim10.05/Vivado2019.1_jiont/v_hdmi_rx_v2_0_0
v_hdmi_rx_v3_0_0 = D:/modelsim10.05/Vivado2019.1_jiont/v_hdmi_rx_v3_0_0
v_hdmi_tx_v2_0_0 = D:/modelsim10.05/Vivado2019.1_jiont/v_hdmi_tx_v2_0_0
v_hdmi_tx_v3_0_0 = D:/modelsim10.05/Vivado2019.1_jiont/v_hdmi_tx_v3_0_0
v_hscaler_v1_0_13 = D:/modelsim10.05/Vivado2019.1_jiont/v_hscaler_v1_0_13
v_letterbox_v1_0_13 = D:/modelsim10.05/Vivado2019.1_jiont/v_letterbox_v1_0_13
v_mix_v3_0_3 = D:/modelsim10.05/Vivado2019.1_jiont/v_mix_v3_0_3
v_mix_v4_0_0 = D:/modelsim10.05/Vivado2019.1_jiont/v_mix_v4_0_0
v_multi_scaler_v1_0_1 = D:/modelsim10.05/Vivado2019.1_jiont/v_multi_scaler_v1_0_1
v_scenechange_v1_0_1 = D:/modelsim10.05/Vivado2019.1_jiont/v_scenechange_v1_0_1
v_sdi_rx_vid_bridge_v2_0_0 = D:/modelsim10.05/Vivado2019.1_jiont/v_sdi_rx_vid_bridge_v2_0_0
v_smpte_sdi_v3_0_8 = D:/modelsim10.05/Vivado2019.1_jiont/v_smpte_sdi_v3_0_8
v_smpte_uhdsdi_rx_v1_0_0 = D:/modelsim10.05/Vivado2019.1_jiont/v_smpte_uhdsdi_rx_v1_0_0
v_smpte_uhdsdi_tx_v1_0_0 = D:/modelsim10.05/Vivado2019.1_jiont/v_smpte_uhdsdi_tx_v1_0_0
v_smpte_uhdsdi_v1_0_7 = D:/modelsim10.05/Vivado2019.1_jiont/v_smpte_uhdsdi_v1_0_7
v_tpg_v7_0_13 = D:/modelsim10.05/Vivado2019.1_jiont/v_tpg_v7_0_13
v_tpg_v8_0_1 = D:/modelsim10.05/Vivado2019.1_jiont/v_tpg_v8_0_1
v_uhdsdi_audio_v1_0_0 = D:/modelsim10.05/Vivado2019.1_jiont/v_uhdsdi_audio_v1_0_0
v_uhdsdi_audio_v1_1_0 = D:/modelsim10.05/Vivado2019.1_jiont/v_uhdsdi_audio_v1_1_0
v_uhdsdi_audio_v2_0_1 = D:/modelsim10.05/Vivado2019.1_jiont/v_uhdsdi_audio_v2_0_1
v_uhdsdi_vidgen_v1_0_1 = D:/modelsim10.05/Vivado2019.1_jiont/v_uhdsdi_vidgen_v1_0_1
v_vcresampler_v1_0_13 = D:/modelsim10.05/Vivado2019.1_jiont/v_vcresampler_v1_0_13
v_vid_in_axi4s_v4_0_9 = D:/modelsim10.05/Vivado2019.1_jiont/v_vid_in_axi4s_v4_0_9
v_vscaler_v1_0_13 = D:/modelsim10.05/Vivado2019.1_jiont/v_vscaler_v1_0_13
xaui_v12_3_6 = D:/modelsim10.05/Vivado2019.1_jiont/xaui_v12_3_6
xbip_dsp48_wrapper_v3_0_4 = D:/modelsim10.05/Vivado2019.1_jiont/xbip_dsp48_wrapper_v3_0_4
xbip_utils_v3_0_10 = D:/modelsim10.05/Vivado2019.1_jiont/xbip_utils_v3_0_10
xdma_v4_1_3 = D:/modelsim10.05/Vivado2019.1_jiont/xdma_v4_1_3
xhmc_v1_0_9 = D:/modelsim10.05/Vivado2019.1_jiont/xhmc_v1_0_9
xlconcat_v2_1_3 = D:/modelsim10.05/Vivado2019.1_jiont/xlconcat_v2_1_3
xlconstant_v1_1_6 = D:/modelsim10.05/Vivado2019.1_jiont/xlconstant_v1_1_6
xlslice_v1_0_2 = D:/modelsim10.05/Vivado2019.1_jiont/xlslice_v1_0_2
xsdbm_v2_0_0 = D:/modelsim10.05/Vivado2019.1_jiont/xsdbm_v2_0_0
xsdbm_v3_0_0 = D:/modelsim10.05/Vivado2019.1_jiont/xsdbm_v3_0_0
xxv_ethernet_v2_4_4 = D:/modelsim10.05/Vivado2019.1_jiont/xxv_ethernet_v2_4_4
xxv_ethernet_v2_5_2 = D:/modelsim10.05/Vivado2019.1_jiont/xxv_ethernet_v2_5_2
xxv_ethernet_v3_0_0 = D:/modelsim10.05/Vivado2019.1_jiont/xxv_ethernet_v3_0_0
zynq_ultra_ps_e_v3_2_3 = D:/modelsim10.05/Vivado2019.1_jiont/zynq_ultra_ps_e_v3_2_3
zynq_ultra_ps_e_v3_3_0 = D:/modelsim10.05/Vivado2019.1_jiont/zynq_ultra_ps_e_v3_3_0
lib_srl_fifo_v1_0_2 = D:/modelsim10.05/Vivado2019.1_jiont/lib_srl_fifo_v1_0_2
lib_fifo_v1_0_13 = D:/modelsim10.05/Vivado2019.1_jiont/lib_fifo_v1_0_13
axi_datamover_v5_1_21 = D:/modelsim10.05/Vivado2019.1_jiont/axi_datamover_v5_1_21
amm_axi_bridge_v1_0_5 = D:/modelsim10.05/Vivado2019.1_jiont/amm_axi_bridge_v1_0_5
axis_interconnect_v1_1_17 = D:/modelsim10.05/Vivado2019.1_jiont/axis_interconnect_v1_1_17
ats_switch_v1_0_2 = D:/modelsim10.05/Vivado2019.1_jiont/ats_switch_v1_0_2
audio_formatter_v1_0_1 = D:/modelsim10.05/Vivado2019.1_jiont/audio_formatter_v1_0_1
axi4stream_vip_v1_1_5 = D:/modelsim10.05/Vivado2019.1_jiont/axi4stream_vip_v1_1_5
v_tc_v6_1_13 = D:/modelsim10.05/Vivado2019.1_jiont/v_tc_v6_1_13
v_axi4s_vid_out_v4_0_10 = D:/modelsim10.05/Vivado2019.1_jiont/v_axi4s_vid_out_v4_0_10
axi4svideo_bridge_v1_0_10 = D:/modelsim10.05/Vivado2019.1_jiont/axi4svideo_bridge_v1_0_10
axis_accelerator_adapter_v2_1_15 = D:/modelsim10.05/Vivado2019.1_jiont/axis_accelerator_adapter_v2_1_15
axis_broadcaster_v1_1_18 = D:/modelsim10.05/Vivado2019.1_jiont/axis_broadcaster_v1_1_18
axis_clock_converter_v1_1_20 = D:/modelsim10.05/Vivado2019.1_jiont/axis_clock_converter_v1_1_20
axis_combiner_v1_1_17 = D:/modelsim10.05/Vivado2019.1_jiont/axis_combiner_v1_1_17
axis_data_fifo_v1_1_20 = D:/modelsim10.05/Vivado2019.1_jiont/axis_data_fifo_v1_1_20
axis_data_fifo_v2_0_1 = D:/modelsim10.05/Vivado2019.1_jiont/axis_data_fifo_v2_0_1
axis_register_slice_v1_1_19 = D:/modelsim10.05/Vivado2019.1_jiont/axis_register_slice_v1_1_19
axis_dwidth_converter_v1_1_18 = D:/modelsim10.05/Vivado2019.1_jiont/axis_dwidth_converter_v1_1_18
axis_subset_converter_v1_1_19 = D:/modelsim10.05/Vivado2019.1_jiont/axis_subset_converter_v1_1_19
axis_switch_v1_1_19 = D:/modelsim10.05/Vivado2019.1_jiont/axis_switch_v1_1_19
axis_vio_v1_0_0 = D:/modelsim10.05/Vivado2019.1_jiont/axis_vio_v1_0_0
axi_apb_bridge_v3_0_15 = D:/modelsim10.05/Vivado2019.1_jiont/axi_apb_bridge_v3_0_15
axi_bram_ctrl_v4_0_14 = D:/modelsim10.05/Vivado2019.1_jiont/axi_bram_ctrl_v4_0_14
axi_sg_v4_1_12 = D:/modelsim10.05/Vivado2019.1_jiont/axi_sg_v4_1_12
axi_cdma_v4_1_19 = D:/modelsim10.05/Vivado2019.1_jiont/axi_cdma_v4_1_19
axi_clock_converter_v2_1_18 = D:/modelsim10.05/Vivado2019.1_jiont/axi_clock_converter_v2_1_18
axi_data_fifo_v2_1_18 = D:/modelsim10.05/Vivado2019.1_jiont/axi_data_fifo_v2_1_18
axi_register_slice_v2_1_19 = D:/modelsim10.05/Vivado2019.1_jiont/axi_register_slice_v2_1_19
axi_crossbar_v2_1_20 = D:/modelsim10.05/Vivado2019.1_jiont/axi_crossbar_v2_1_20
axi_dma_v7_1_20 = D:/modelsim10.05/Vivado2019.1_jiont/axi_dma_v7_1_20
axi_protocol_converter_v2_1_19 = D:/modelsim10.05/Vivado2019.1_jiont/axi_protocol_converter_v2_1_19
axi_dwidth_converter_v2_1_19 = D:/modelsim10.05/Vivado2019.1_jiont/axi_dwidth_converter_v2_1_19
axi_emc_v3_0_19 = D:/modelsim10.05/Vivado2019.1_jiont/axi_emc_v3_0_19
axi_epc_v2_0_22 = D:/modelsim10.05/Vivado2019.1_jiont/axi_epc_v2_0_22
lib_bmg_v1_0_12 = D:/modelsim10.05/Vivado2019.1_jiont/lib_bmg_v1_0_12
axi_ethernetlite_v3_0_17 = D:/modelsim10.05/Vivado2019.1_jiont/axi_ethernetlite_v3_0_17
axi_ethernet_buffer_v2_0_20 = D:/modelsim10.05/Vivado2019.1_jiont/axi_ethernet_buffer_v2_0_20
axi_fifo_mm_s_v4_1_16 = D:/modelsim10.05/Vivado2019.1_jiont/axi_fifo_mm_s_v4_1_16
axi_fifo_mm_s_v4_2_1 = D:/modelsim10.05/Vivado2019.1_jiont/axi_fifo_mm_s_v4_2_1
axi_firewall_v1_0_7 = D:/modelsim10.05/Vivado2019.1_jiont/axi_firewall_v1_0_7
interrupt_control_v3_1_4 = D:/modelsim10.05/Vivado2019.1_jiont/interrupt_control_v3_1_4
axi_gpio_v2_0_21 = D:/modelsim10.05/Vivado2019.1_jiont/axi_gpio_v2_0_21
axi_hwicap_v3_0_23 = D:/modelsim10.05/Vivado2019.1_jiont/axi_hwicap_v3_0_23
axi_iic_v2_0_22 = D:/modelsim10.05/Vivado2019.1_jiont/axi_iic_v2_0_22
axi_intc_v4_1_13 = D:/modelsim10.05/Vivado2019.1_jiont/axi_intc_v4_1_13
axi_interconnect_v1_7_16 = D:/modelsim10.05/Vivado2019.1_jiont/axi_interconnect_v1_7_16
axi_master_burst_v2_0_7 = D:/modelsim10.05/Vivado2019.1_jiont/axi_master_burst_v2_0_7
axi_msg_v1_0_5 = D:/modelsim10.05/Vivado2019.1_jiont/axi_msg_v1_0_5
axi_mcdma_v1_0_5 = D:/modelsim10.05/Vivado2019.1_jiont/axi_mcdma_v1_0_5
axi_mcdma_v1_1_0 = D:/modelsim10.05/Vivado2019.1_jiont/axi_mcdma_v1_1_0
axi_memory_init_v1_0_0 = D:/modelsim10.05/Vivado2019.1_jiont/axi_memory_init_v1_0_0
axi_mm2s_mapper_v1_1_18 = D:/modelsim10.05/Vivado2019.1_jiont/axi_mm2s_mapper_v1_1_18
axi_mmu_v2_1_17 = D:/modelsim10.05/Vivado2019.1_jiont/axi_mmu_v2_1_17
axi_pcie_v2_9_1 = D:/modelsim10.05/Vivado2019.1_jiont/axi_pcie_v2_9_1
axi_protocol_checker_v2_0_5 = D:/modelsim10.05/Vivado2019.1_jiont/axi_protocol_checker_v2_0_5
axi_quad_spi_v3_2_18 = D:/modelsim10.05/Vivado2019.1_jiont/axi_quad_spi_v3_2_18
axi_sideband_util_v1_0_3 = D:/modelsim10.05/Vivado2019.1_jiont/axi_sideband_util_v1_0_3
axi_tft_v2_0_22 = D:/modelsim10.05/Vivado2019.1_jiont/axi_tft_v2_0_22
axi_timebase_wdt_v3_0_11 = D:/modelsim10.05/Vivado2019.1_jiont/axi_timebase_wdt_v3_0_11
axi_timer_v2_0_21 = D:/modelsim10.05/Vivado2019.1_jiont/axi_timer_v2_0_21
axi_traffic_gen_v2_0_20 = D:/modelsim10.05/Vivado2019.1_jiont/axi_traffic_gen_v2_0_20
axi_traffic_gen_v3_0_5 = D:/modelsim10.05/Vivado2019.1_jiont/axi_traffic_gen_v3_0_5
axi_uart16550_v2_0_21 = D:/modelsim10.05/Vivado2019.1_jiont/axi_uart16550_v2_0_21
axi_uartlite_v2_0_23 = D:/modelsim10.05/Vivado2019.1_jiont/axi_uartlite_v2_0_23
axi_usb2_device_v5_0_20 = D:/modelsim10.05/Vivado2019.1_jiont/axi_usb2_device_v5_0_20
axi_utils_v2_0_6 = D:/modelsim10.05/Vivado2019.1_jiont/axi_utils_v2_0_6
axi_vdma_v6_3_7 = D:/modelsim10.05/Vivado2019.1_jiont/axi_vdma_v6_3_7
xbip_pipe_v3_0_6 = D:/modelsim10.05/Vivado2019.1_jiont/xbip_pipe_v3_0_6
xbip_dsp48_addsub_v3_0_6 = D:/modelsim10.05/Vivado2019.1_jiont/xbip_dsp48_addsub_v3_0_6
xbip_addsub_v3_0_6 = D:/modelsim10.05/Vivado2019.1_jiont/xbip_addsub_v3_0_6
c_reg_fd_v12_0_6 = D:/modelsim10.05/Vivado2019.1_jiont/c_reg_fd_v12_0_6
c_addsub_v12_0_13 = D:/modelsim10.05/Vivado2019.1_jiont/c_addsub_v12_0_13
axi_vfifo_ctrl_v2_0_21 = D:/modelsim10.05/Vivado2019.1_jiont/axi_vfifo_ctrl_v2_0_21
axi_vip_v1_1_5 = D:/modelsim10.05/Vivado2019.1_jiont/axi_vip_v1_1_5
bs_switch_v1_0_0 = D:/modelsim10.05/Vivado2019.1_jiont/bs_switch_v1_0_0
canfd_v2_0_1 = D:/modelsim10.05/Vivado2019.1_jiont/canfd_v2_0_1
can_v5_0_22 = D:/modelsim10.05/Vivado2019.1_jiont/can_v5_0_22
cic_compiler_v4_0_14 = D:/modelsim10.05/Vivado2019.1_jiont/cic_compiler_v4_0_14
xbip_bram18k_v3_0_6 = D:/modelsim10.05/Vivado2019.1_jiont/xbip_bram18k_v3_0_6
mult_gen_v12_0_15 = D:/modelsim10.05/Vivado2019.1_jiont/mult_gen_v12_0_15
cmpy_v6_0_17 = D:/modelsim10.05/Vivado2019.1_jiont/cmpy_v6_0_17
c_mux_bit_v12_0_6 = D:/modelsim10.05/Vivado2019.1_jiont/c_mux_bit_v12_0_6
c_shift_ram_v12_0_13 = D:/modelsim10.05/Vivado2019.1_jiont/c_shift_ram_v12_0_13
c_mux_bus_v12_0_6 = D:/modelsim10.05/Vivado2019.1_jiont/c_mux_bus_v12_0_6
c_gate_bit_v12_0_6 = D:/modelsim10.05/Vivado2019.1_jiont/c_gate_bit_v12_0_6
xbip_counter_v3_0_6 = D:/modelsim10.05/Vivado2019.1_jiont/xbip_counter_v3_0_6
c_counter_binary_v12_0_13 = D:/modelsim10.05/Vivado2019.1_jiont/c_counter_binary_v12_0_13
c_compare_v12_0_6 = D:/modelsim10.05/Vivado2019.1_jiont/c_compare_v12_0_6
convolution_v9_0_14 = D:/modelsim10.05/Vivado2019.1_jiont/convolution_v9_0_14
cordic_v6_0_15 = D:/modelsim10.05/Vivado2019.1_jiont/cordic_v6_0_15
cpri_v8_10_0 = D:/modelsim10.05/Vivado2019.1_jiont/cpri_v8_10_0
xbip_dsp48_acc_v3_0_6 = D:/modelsim10.05/Vivado2019.1_jiont/xbip_dsp48_acc_v3_0_6
xbip_accum_v3_0_6 = D:/modelsim10.05/Vivado2019.1_jiont/xbip_accum_v3_0_6
c_accum_v12_0_13 = D:/modelsim10.05/Vivado2019.1_jiont/c_accum_v12_0_13
xbip_dsp48_multadd_v3_0_6 = D:/modelsim10.05/Vivado2019.1_jiont/xbip_dsp48_multadd_v3_0_6
dds_compiler_v6_0_18 = D:/modelsim10.05/Vivado2019.1_jiont/dds_compiler_v6_0_18
dft_v4_0_16 = D:/modelsim10.05/Vivado2019.1_jiont/dft_v4_0_16
dft_v4_1_1 = D:/modelsim10.05/Vivado2019.1_jiont/dft_v4_1_1
displayport_v7_0_11 = D:/modelsim10.05/Vivado2019.1_jiont/displayport_v7_0_11
displayport_v8_1_1 = D:/modelsim10.05/Vivado2019.1_jiont/displayport_v8_1_1
displayport_v9_0_1 = D:/modelsim10.05/Vivado2019.1_jiont/displayport_v9_0_1
xbip_dsp48_mult_v3_0_6 = D:/modelsim10.05/Vivado2019.1_jiont/xbip_dsp48_mult_v3_0_6
floating_point_v7_0_16 = D:/modelsim10.05/Vivado2019.1_jiont/floating_point_v7_0_16
div_gen_v5_1_15 = D:/modelsim10.05/Vivado2019.1_jiont/div_gen_v5_1_15
dp_videoaxi4s_bridge_v1_0_0 = D:/modelsim10.05/Vivado2019.1_jiont/dp_videoaxi4s_bridge_v1_0_0
dsp_macro_v1_0_0 = D:/modelsim10.05/Vivado2019.1_jiont/dsp_macro_v1_0_0
fir_compiler_v5_2_6 = D:/modelsim10.05/Vivado2019.1_jiont/fir_compiler_v5_2_6
duc_ddc_compiler_v3_0_15 = D:/modelsim10.05/Vivado2019.1_jiont/duc_ddc_compiler_v3_0_15
ernic_v1_0_1 = D:/modelsim10.05/Vivado2019.1_jiont/ernic_v1_0_1
etrnic_v1_0_3 = D:/modelsim10.05/Vivado2019.1_jiont/etrnic_v1_0_3
etrnic_v1_1_2 = D:/modelsim10.05/Vivado2019.1_jiont/etrnic_v1_1_2
fc32_rs_fec_v1_0_10 = D:/modelsim10.05/Vivado2019.1_jiont/fc32_rs_fec_v1_0_10
fec_5g_common_v1_0_1 = D:/modelsim10.05/Vivado2019.1_jiont/fec_5g_common_v1_0_1
fec_5g_common_v1_1_1 = D:/modelsim10.05/Vivado2019.1_jiont/fec_5g_common_v1_1_1
fir_compiler_v7_2_12 = D:/modelsim10.05/Vivado2019.1_jiont/fir_compiler_v7_2_12
flexo_100g_rs_fec_v1_0_10 = D:/modelsim10.05/Vivado2019.1_jiont/flexo_100g_rs_fec_v1_0_10
floating_point_v7_1_8 = D:/modelsim10.05/Vivado2019.1_jiont/floating_point_v7_1_8
g709_rs_encoder_v2_2_6 = D:/modelsim10.05/Vivado2019.1_jiont/g709_rs_encoder_v2_2_6
rs_toolbox_v9_0_7 = D:/modelsim10.05/Vivado2019.1_jiont/rs_toolbox_v9_0_7
g709_rs_decoder_v2_2_8 = D:/modelsim10.05/Vivado2019.1_jiont/g709_rs_decoder_v2_2_8
g709_fec_v2_3_5 = D:/modelsim10.05/Vivado2019.1_jiont/g709_fec_v2_3_5
g709_fec_v2_4_1 = D:/modelsim10.05/Vivado2019.1_jiont/g709_fec_v2_4_1
g975_efec_i4_v1_0_17 = D:/modelsim10.05/Vivado2019.1_jiont/g975_efec_i4_v1_0_17
g975_efec_i7_v2_0_18 = D:/modelsim10.05/Vivado2019.1_jiont/g975_efec_i7_v2_0_18
ieee802d3_200g_rs_fec_v1_0_6 = D:/modelsim10.05/Vivado2019.1_jiont/ieee802d3_200g_rs_fec_v1_0_6
ieee802d3_25g_rs_fec_v1_0_12 = D:/modelsim10.05/Vivado2019.1_jiont/ieee802d3_25g_rs_fec_v1_0_12
ieee802d3_400g_rs_fec_v1_0_6 = D:/modelsim10.05/Vivado2019.1_jiont/ieee802d3_400g_rs_fec_v1_0_6
ieee802d3_50g_rs_fec_v1_0_11 = D:/modelsim10.05/Vivado2019.1_jiont/ieee802d3_50g_rs_fec_v1_0_11
ieee802d3_50g_rs_fec_v2_0_0 = D:/modelsim10.05/Vivado2019.1_jiont/ieee802d3_50g_rs_fec_v2_0_0
ieee802d3_rs_fec_v1_0_15 = D:/modelsim10.05/Vivado2019.1_jiont/ieee802d3_rs_fec_v1_0_15
ieee802d3_rs_fec_v2_0_4 = D:/modelsim10.05/Vivado2019.1_jiont/ieee802d3_rs_fec_v2_0_4
ldpc_v2_0_3 = D:/modelsim10.05/Vivado2019.1_jiont/ldpc_v2_0_3
lte_3gpp_channel_estimator_v2_0_16 = D:/modelsim10.05/Vivado2019.1_jiont/lte_3gpp_channel_estimator_v2_0_16
lte_3gpp_mimo_decoder_v3_0_15 = D:/modelsim10.05/Vivado2019.1_jiont/lte_3gpp_mimo_decoder_v3_0_15
lte_3gpp_mimo_encoder_v4_0_14 = D:/modelsim10.05/Vivado2019.1_jiont/lte_3gpp_mimo_encoder_v4_0_14
tcc_encoder_3gpplte_v4_0_15 = D:/modelsim10.05/Vivado2019.1_jiont/tcc_encoder_3gpplte_v4_0_15
lte_dl_channel_encoder_v3_0_15 = D:/modelsim10.05/Vivado2019.1_jiont/lte_dl_channel_encoder_v3_0_15
lte_dl_channel_encoder_v4_0_0 = D:/modelsim10.05/Vivado2019.1_jiont/lte_dl_channel_encoder_v4_0_0
xfft_v7_2_9 = D:/modelsim10.05/Vivado2019.1_jiont/xfft_v7_2_9
lte_fft_v2_0_18 = D:/modelsim10.05/Vivado2019.1_jiont/lte_fft_v2_0_18
xfft_v9_1_2 = D:/modelsim10.05/Vivado2019.1_jiont/xfft_v9_1_2
lte_fft_v2_1_0 = D:/modelsim10.05/Vivado2019.1_jiont/lte_fft_v2_1_0
xbip_dsp48_multacc_v3_0_6 = D:/modelsim10.05/Vivado2019.1_jiont/xbip_dsp48_multacc_v3_0_6
lte_pucch_receiver_v2_0_16 = D:/modelsim10.05/Vivado2019.1_jiont/lte_pucch_receiver_v2_0_16
xbip_multadd_v3_0_14 = D:/modelsim10.05/Vivado2019.1_jiont/xbip_multadd_v3_0_14
lte_rach_detector_v3_1_5 = D:/modelsim10.05/Vivado2019.1_jiont/lte_rach_detector_v3_1_5
lte_ul_channel_decoder_v4_0_16 = D:/modelsim10.05/Vivado2019.1_jiont/lte_ul_channel_decoder_v4_0_16
mailbox_v2_1_11 = D:/modelsim10.05/Vivado2019.1_jiont/mailbox_v2_1_11
mdm_v3_2_16 = D:/modelsim10.05/Vivado2019.1_jiont/mdm_v3_2_16
iomodule_v3_0 = D:/modelsim10.05/Vivado2019.1_jiont/iomodule_v3_0
lmb_bram_if_cntlr_v4_0 = D:/modelsim10.05/Vivado2019.1_jiont/lmb_bram_if_cntlr_v4_0
lmb_v10_v3_0 = D:/modelsim10.05/Vivado2019.1_jiont/lmb_v10_v3_0
axi_lite_ipif_v3_0 = D:/modelsim10.05/Vivado2019.1_jiont/axi_lite_ipif_v3_0
mdm_v3_2 = D:/modelsim10.05/Vivado2019.1_jiont/mdm_v3_2
microblaze_mcs_v2_3_6 = D:/modelsim10.05/Vivado2019.1_jiont/microblaze_mcs_v2_3_6
noc_mc_ddr4_phy_v1_0_0 = D:/modelsim10.05/Vivado2019.1_jiont/noc_mc_ddr4_phy_v1_0_0
perf_axi_tg_v1_0_8 = D:/modelsim10.05/Vivado2019.1_jiont/perf_axi_tg_v1_0_8
polar_v1_0_3 = D:/modelsim10.05/Vivado2019.1_jiont/polar_v1_0_3
prc_v1_3_2 = D:/modelsim10.05/Vivado2019.1_jiont/prc_v1_3_2
processing_system7_vip_v1_0_7 = D:/modelsim10.05/Vivado2019.1_jiont/processing_system7_vip_v1_0_7
proc_sys_reset_v5_0_13 = D:/modelsim10.05/Vivado2019.1_jiont/proc_sys_reset_v5_0_13
pr_axi_shutdown_manager_v1_0_1 = D:/modelsim10.05/Vivado2019.1_jiont/pr_axi_shutdown_manager_v1_0_1
pr_bitstream_monitor_v1_0_1 = D:/modelsim10.05/Vivado2019.1_jiont/pr_bitstream_monitor_v1_0_1
pr_decoupler_v1_0_7 = D:/modelsim10.05/Vivado2019.1_jiont/pr_decoupler_v1_0_7
quadsgmii_v3_4_6 = D:/modelsim10.05/Vivado2019.1_jiont/quadsgmii_v3_4_6
rs_decoder_v9_0_16 = D:/modelsim10.05/Vivado2019.1_jiont/rs_decoder_v9_0_16
rs_encoder_v9_0_15 = D:/modelsim10.05/Vivado2019.1_jiont/rs_encoder_v9_0_15
rxaui_v4_4_6 = D:/modelsim10.05/Vivado2019.1_jiont/rxaui_v4_4_6
sd_fec_v1_1_3 = D:/modelsim10.05/Vivado2019.1_jiont/sd_fec_v1_1_3
sid_v8_0_14 = D:/modelsim10.05/Vivado2019.1_jiont/sid_v8_0_14
soft_ecc_proxy_v1_0_0 = D:/modelsim10.05/Vivado2019.1_jiont/soft_ecc_proxy_v1_0_0
spdif_v2_0_21 = D:/modelsim10.05/Vivado2019.1_jiont/spdif_v2_0_21
srio_gen2_v4_1_6 = D:/modelsim10.05/Vivado2019.1_jiont/srio_gen2_v4_1_6
switch_core_top_v1_0_7 = D:/modelsim10.05/Vivado2019.1_jiont/switch_core_top_v1_0_7
sync_ip = D:/modelsim10.05/Vivado2019.1_jiont/sync_ip
tcc_decoder_3gppmm_v2_0_18 = D:/modelsim10.05/Vivado2019.1_jiont/tcc_decoder_3gppmm_v2_0_18
tcc_encoder_3gpp_v5_0_15 = D:/modelsim10.05/Vivado2019.1_jiont/tcc_encoder_3gpp_v5_0_15
tmr_comparator_v1_0_2 = D:/modelsim10.05/Vivado2019.1_jiont/tmr_comparator_v1_0_2
tmr_sem_v1_0_8 = D:/modelsim10.05/Vivado2019.1_jiont/tmr_sem_v1_0_8
tri_mode_ethernet_mac_v9_0_14 = D:/modelsim10.05/Vivado2019.1_jiont/tri_mode_ethernet_mac_v9_0_14
tsn_temac_v1_0_4 = D:/modelsim10.05/Vivado2019.1_jiont/tsn_temac_v1_0_4
videoaxi4s_bridge_v1_0_5 = D:/modelsim10.05/Vivado2019.1_jiont/videoaxi4s_bridge_v1_0_5
viterbi_v9_1_11 = D:/modelsim10.05/Vivado2019.1_jiont/viterbi_v9_1_11
v_ccm_v6_0_15 = D:/modelsim10.05/Vivado2019.1_jiont/v_ccm_v6_0_15
v_cfa_v7_0_14 = D:/modelsim10.05/Vivado2019.1_jiont/v_cfa_v7_0_14
v_cresample_v4_0_14 = D:/modelsim10.05/Vivado2019.1_jiont/v_cresample_v4_0_14
v_dual_splitter_v1_0_9 = D:/modelsim10.05/Vivado2019.1_jiont/v_dual_splitter_v1_0_9
v_enhance_v8_0_15 = D:/modelsim10.05/Vivado2019.1_jiont/v_enhance_v8_0_15
v_gamma_v7_0_15 = D:/modelsim10.05/Vivado2019.1_jiont/v_gamma_v7_0_15
v_osd_v6_0_16 = D:/modelsim10.05/Vivado2019.1_jiont/v_osd_v6_0_16
v_rgb2ycrcb_v7_1_13 = D:/modelsim10.05/Vivado2019.1_jiont/v_rgb2ycrcb_v7_1_13
v_vid_sdi_tx_bridge_v2_0_0 = D:/modelsim10.05/Vivado2019.1_jiont/v_vid_sdi_tx_bridge_v2_0_0
v_ycrcb2rgb_v7_1_13 = D:/modelsim10.05/Vivado2019.1_jiont/v_ycrcb2rgb_v7_1_13
xbip_dsp48_macro_v3_0_17 = D:/modelsim10.05/Vivado2019.1_jiont/xbip_dsp48_macro_v3_0_17
xfft_v9_0_17 = D:/modelsim10.05/Vivado2019.1_jiont/xfft_v9_0_17
xsdbs_v1_0_2 = D:/modelsim10.05/Vivado2019.1_jiont/xsdbs_v1_0_2
zynq_ultra_ps_e_vip_v1_0_5 = D:/modelsim10.05/Vivado2019.1_jiont/zynq_ultra_ps_e_vip_v1_0_5

同时需要添加 ip 模块中 sim(前仿) 文件夹下的内容，simulation文件夹为后仿真,在每个ip的说明文档里有

如果只是临时仿真，可以在 simulate - start simulation -- librariese 中手动添加库的位置，此方法一次只能添加一个ip，不能直接添加联合仿真的总文件夹，否则无法识别

快捷键：

首次运行 tcl：tool-tcl-execute macro

修改后再次运行 tcl ： load - macro file

快速分组：选中信号，ctrl+g

修改行高：选中信号，右键properties-format-height

修改窗口排列方式：

变成堆叠：变成平铺：

缩小：O 放大：I

添加光标 A

查找group下的信号：ctrl+f

vivado 和 modesim 联合仿真快速修改重仿相关推荐

FPGA学习之路—Vivado与Modelsim联合仿真
Vivado与Modelsim联合仿真笔者在学习FPGA过程中遇到了如何使用Vivado和Modelsim进行联合仿真的问题,特此记录. 首先确定版本笔者Vivado用的是2018.3版本,先是随 ...
vivado和modelsim联合仿真实现占空比1:15的分频
上一讲我们看了偶数分频 vivado和modelsim联合仿真实现偶分频,只需要在clk计数到一半时进行翻转即可,这是占空比为50%的情况,如果占空比任意数值就需要重新设计 16需要从0计数到15=4 ...
vivado和modelsim联合仿真实现偶分频
首先创建一个工程,因为不在硬件上实现所以芯片型号随便选一个就行创建design文件div6.v,代码来源于以下视频,稍作修改. 在复位时给输出信号clk6赋值为0,不然输出不确定判断条件cnt为1 ...
关于Vivado和Modelsim联合仿真的爱恨情仇
关于Vivado和Modelsim联合仿真的爱恨情仇心路历程版本对应仿真设置错误解决关于使用modelsim查看状态转移图心路历程 vivado自带仿真工具虽然可以使用,但是每一次修改代码 ...
【FPGA】vivado和modelsim联合仿真
文章目录二.遇到的问题三. 参考资料: 二.遇到的问题 1. 错误一: # ** Fatal: (vsim-3693) The minimum time resolution limit (10f ...
Vivado和Modelsim联合仿真问题记录
目录写在前面 Modelsim安装 1.以管理员身份运行安装程序 2.去掉mgls.dll和mgl64s.dll文件"只读"属性,直接双击运行patch64_dll.bat 编译 ...
Vivado与modelsim联合仿真（2018.3---10.6c）
Vivado不同于Quartus自带仿真,但是个人觉得跑一些简单工程的仿真还是可以的,不过跑一些复杂工程的的仿真简直就是毫无体验感,建议使用第三方仿真软件进行联合仿真,这边主要推荐的Modelsim, ...
vivado 和 modelsim联合仿真
1)随便打开一个vivado工程, 2)配置3rd party, 设置install path, D:\modeltech64_10.6e\win64, 设置default compiled libr ...
vivado和modelsim联合仿真实现奇分频
代码来自以下视频并做了适当修改,老师讲得好像有点问题,有空再研究添加了复位模块两个计数器都是计数到4翻转,是五分频,一个是上升沿一个是下降沿最后实现得是在下降沿翻转而不是上升沿 FPGA分频器的 ...

vivado 和 modesim 联合仿真快速修改重仿

vivado 和 modesim 联合仿真快速修改重仿相关推荐

最新文章

热门文章