HDLBits 系列（32）Sequence recognition（序列检测）

原题复现

审题

状态转移图

我的设计

原题复现

原题复现：

Synchronous HDLC framing involves decoding a continuous bit stream of data to look for bit patterns that indicate the beginning and end of frames (packets). Seeing exactly 6 consecutive 1s (i.e., 01111110) is a "flag" that indicate frame boundaries. To avoid the data stream from accidentally containing "flags", the sender inserts a zero after every 5 consecutive 1s which the receiver must detect and discard. We also need to signal an error if there are 7 or more consecutive 1s.

Create a finite state machine to recognize these three sequences:

0111110: Signal a bit needs to be discarded (disc).
01111110: Flag the beginning/end of a frame (flag).
01111111...: Error (7 or more 1s) (err).

When the FSM is reset, it should be in a state that behaves as though the previous input were 0.

Here are some example sequences that illustrate the desired operation.

审题

根据题目来看，这是一个序列识别的一个问题，如果识别到序列有连续5个1（即1111_10），则disc有效；

如果有连续6个1（即1111_110），则flag有效；

如果有连续7个1或者更多的1，则err有效。

状态转移图

就是这样一个问题，我们根据上述波形图来画出状态转移图：

我的设计

根据状态转移图，很容易得到设计：

module top_module(input clk,input reset,    // Synchronous resetinput in,output disc,output flag,output err);localparam S0 = 0, S1 = 1, S2 = 2, S3 = 3, S4 = 4, S5 = 5, S6 = 6, DISC = 7, FLAG = 8, ERR = 9;reg [3:0] state, next_state;always@(*) begincase(state)S0: beginif(in) next_state = S1;else next_state = S0;endS1: beginif(in) next_state = S2;else next_state = S0;endS2: beginif(in) next_state = S3;else next_state = S0;endS3: beginif(in) next_state = S4;else next_state = S0;endS4: beginif(in) next_state = S5;else next_state = S0;endS5: beginif(in) next_state = S6;else next_state = DISC;endS6: beginif(in) next_state = ERR;else next_state = FLAG;endDISC: beginif(in) next_state = S1;else next_state = S0;endFLAG: beginif(in) next_state = S1;else next_state = S0;endERR: beginif(in) next_state = ERR;else next_state = S0;enddefault: beginnext_state = S0;endendcaseendalways@(posedge clk)beginif(reset) state <= S0;else state <= next_state;endassign disc = (state == DISC)?1:0;assign flag = (state == FLAG)?1:0;assign err = (state == ERR)?1:0;endmodule

测试成功！

这是序列检测的一个典型做法，校招可没少做这种题目，只是好像都还要比这个简单。