RRAM/ Near Memory Computing (NMC) Survey - Reading Notes 0707
Reading Notes of Resistive Random Access Memory – Day 2
Chapter 3 RRAM Characterization and Modeling
Overview of RRAM Physical Mechanism
A general picture for the filamentary switching mechanism.
- Forming: 对本征RRAM样本,加电压VformingV_{forming}Vforming,中间氧化层的O2−O^{2-}O2−被剥离,随电场漂移到电极,堆积到电极形成非晶中性氧原子或氧化膜,留下氧空穴VoV_oVo,完成forming过程。Forming过程类似于绝缘体的软击穿。氧空穴VoV_oVo形成Conductive Filament(CF)连接两电极,得到低阻态LRS。
- Reset: 对于单极型RRAM,加电压+Vreset+V_{reset}+Vreset,通过热效应使O2−O^{2-}O2−扩散,与氧空穴复合,使CF破裂,得到高阻态HRS;对于双极型RRAM,加电压−Vreset-V_{reset}−Vreset,通过电场使得O2−O^{2-}O2−漂移,与氧空穴符合,得到高阻态HRS。
- Set:重新加电压+Vset+V_{set}+Vset,剥离O2−O^{2-}O2−,VoV_oVo形成CF,得到低阻态LRS。
- 沉积形成的氧化物层多为多晶和非晶,CF多在晶粒边界形成
- O2−O^{2-}O2−与VoV_oVo复合后,剩余的VoV_oVo靠近底层电极,被称作Virtual Electrode
Materials and Electrical Characterization
有很多人研究RRAM device的I-V特性,大家基本确认在LRS中,主要呈现线性欧姆特性,但是在HRS中的模型并不统一,目前有Poole-Frenkel emission (log(I/V)∼V1/2log(I/V) \sim V^{1/2}log(I/V)∼V1/2),Schotty emission (logI∼V1/2logI \sim V^{1/2}logI∼V1/2),the space charge limited current characteristic (the Ohmic region I∼VI \sim VI∼V, and the Child’s square law region I∼V2I \sim V^2I∼V2)
HRS几种可能的电子迁移的方式:
- Schottky emission: 热电子注入导带
- Fowler-Nordheim tunneling: 电子通过隧道效应从阴极进入导带,通常在强电场环境下发生
- direct tunneling: 电子通过隧道效应直接从阴极进入阳极,通常在氧化层很薄(< 3nm)的条件下发生
此外还有 trap-assisted-tunneling (TAT) 提供的额外导电性。如果在氧化层中有大量的trap(比如VoV_oVo),那么会有这种方式产生的电流:
- tunneling from cathode to traps
- emission from trap to conductioin band, which is essentially the Poole-Frenkel emission
- F-N-like tunneling from trap to conduction band
- trap-to-trap hopping or tunneling
- tunneling from trap to anode
Electrons would seek the fastest transition paths among all the posibilities.
3.3 Numerial Modeling Using Kinetic Monte-Carlo Method
Kinetic Monte-Carlo方法(KMC方法)是一个分析RRAM的本征的随机转换过程的有效方法。
KMC仿真流程:
仿真软件给出了完整的forming => set => reset流程。学术界仍有争议的是,where the CF is ruptured.
一部分人认为是ruptured near the top electrode. 一部分人认为是ruptured near the bottom electrode.
3.4 Compact Modeling For Spice Simulation
There are several existing RRAM compact models [67, 68, 69, 70] that used a simplified physical picture of the CF formation and repture.
They present a representative model that has been calibrated with IMEC 's HfOx-based RRAM [71]
The I-V relationship of the RRAM model is expressed as:
I=I0exp(−gg0)sinh(VV0)I = I_0exp(-\frac{g}{g_0})sinh(\frac{V}{V_0})I=I0exp(−g0g)sinh(V0V)
用sinh表示,在电压很小的时候呈线性,在电压很大的时候呈指数。
但是问题在于,g是随时间变化的:
g有最小值gming_{min}gmin和最大值gmaxg_{max}gmax。最小值CF接近TE,最大值是CF不能再短的极限。
EagE_{ag}Eag/EarE_{ar}Ear: the activation energy for O2−O^{2-}O2− to migrate from one potential well to another in the generation/ recombination process
a0a_0a0: atomic hopping distance (qV/L)
γ\gammaγ: g-dependent local field enhancement factor. It considers the polarizability of high-k dielectrics and non-uniform potential distribution in the device structure.
T: temperature
dTdt+T−T0τth=V×ICth\frac{dT}{dt} + \frac{T-T_0}{\tau_{th}}=\frac{V\times I}{C_{th}}dtdT+τthT−T0=CthV×I
这个仿真模型和实验结果吻合得非常好(废话,参数都是在这基础上调的)。To simulate the pulse programming conditions in the one-transistor and one-resister (1T1R) configuration, the transistor is implemented using the PTM model [74] at 130 nm technology, to match the channel length that was used in IMEC’s test structure.
继续研究:
分别用[71]和[74]的130nm晶体管,以及[71] 及若干其他的RRAM模型,做1T1R的仿真
[74]这个[PTM][http://ptm.asu.edu/]的网站太优秀了,直接输进去想要的参数,就能把模型文件弄出来,很方便,很好。
Chapter 4 RRAM Array Architecture
1T1R Array
WL: word line; SL: source line; BL: bit line
In this design, each RRAM cell is in series with a cell selection transistor.
The typical cell area of 1T1R array is 12 F2F^2F2 if the W/L of the transistor is 1. 最小弄到6F2F^2F2 F: lithography feature size
注意到,set的时候,SL电压为0;reset的时候, SL的电压大于零。要想使晶体管开启,需要更大的WL电压。因此,set和reset不能在一行上同时做。所以,若干bits要写入的话,需要两步:先1写一次,再2写一次。[75]中有针对这个问题的解决方案。
1T1R RRAM面临的问题是,其编程电压和电流不随尺寸的减小而减小。这导致即便我们使用了更小尺寸的工艺,仍然需要维持一个比较大的宽长比。因此,将RRAM的编程电流降到10uA以下,编程电压降到1V以下很重要。
这里的电流应当是晶体管的驱动电流。由于RRAM的编程电流是不变的,当工艺尺寸减小时。晶体管的驱动电流也变小,要维持RRAM的编程电流,需要提高宽长比,相当于使用更大的晶体管面积(L是不变的,W翻倍)
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