HDLBits 系列（44）状态机补录

文章目录

前言
原题复现
题目解析
状态转移图
设计文件

前言

今天补一个状态机的题目，也是这个系列的题目之一，但是由于之前对题目有点疑惑，今天得到博友反馈，让我明白了这个题目的意思，记录一下。
原题链接

原题复现

Consider a finite state machine that is used to control some type of motor. The FSM has inputs x and y, which come from the motor, and produces outputs f and g, which control the motor. There is also a clock input called clk and a reset input called resetn.

The FSM has to work as follows. As long as the reset input is asserted, the FSM stays in a beginning state, called state A. When the reset signal is de-asserted, then after the next clock edge the FSM has to set the output f to 1 for one clock cycle. Then, the FSM has to monitor the x input. When x has produced the values 1, 0, 1 in three successive clock cycles, then g should be set to 1 on the following clock cycle. While maintaining g = 1 the FSM has to monitor the y input. If y has the value 1 within at most two clock cycles, then the FSM should maintain g = 1 permanently (that is, until reset). But if y does not become 1 within two clock cycles, then the FSM should set g = 0 permanently (until reset).

(The original exam question asked for a state diagram only. But here, implement the FSM.)

Module Declarationmodule top_module (input clk,input resetn,    // active-low synchronous resetinput x,input y,output f,output g
);

题目解析

当时没有明白的还是这一句话：
While maintaining g = 1 the FSM has to monitor the y input. If y has the value 1 within at most two clock cycles, then the FSM should maintain g = 1 permanently (that is, until reset). But if y does not become 1 within two clock cycles, then the FSM should set g = 0 permanently (until reset).
更确切的是这句话：
While maintaining g = 1 the FSM has to monitor the y input. If y has the value 1 within at most two clock cycles, then the FSM should maintain g = 1 permanently (that is, until reset).
是接下来的两个时钟周期内，有一个y为1就可以了，之后的输出永久为1，如果没有一个为1，则永久为0.
根据题目，给出状态转移图：

状态转移图

设计文件

module top_module (input clk,input resetn,    // active-low synchronous resetinput x,input y,output f,output g
); parameter A = 4'd0, S1 = 4'd1, S2 = 4'd2, S3 = 4'd3, S4 = 4'd4;parameter G_OUT= 4'd5, FOREVER_ONE = 4'd6, FOREVER_ZERO = 4'd7;parameter F_OUT = 4'd8;reg [3:0] current_state;reg [3:0] next_state;always@(posedge clk)beginif(resetn == 1'b0)begincurrent_state <= A;endelse begincurrent_state <= next_state;endendalways@(*)begincase(current_state)A:beginnext_state = F_OUT;endF_OUT:beginnext_state = S1;endS1:beginnext_state = x ? S2 : S1;endS2:beginnext_state = x ? S2 : S3;endS3:beginnext_state = x ? G_OUT: S1;end  G_OUT:beginnext_state = y ? FOREVER_ONE : S4;endS4:beginnext_state = y ? FOREVER_ONE : FOREVER_ZERO;endFOREVER_ONE:beginnext_state = FOREVER_ONE;endFOREVER_ZERO:beginnext_state = FOREVER_ZERO;enddefault:beginnext_state = A;endendcaseendassign f = (current_state == F_OUT);assign g = (current_state == S4 || current_state == G_OUT || current_state == FOREVER_ONE);endmodule