【FPGA实验】VGA显示

一. VGA介绍

VGA的全称是Video Graphics Array，即视频图形阵列，是一个使用模拟信号进行视频传

输的标准。早期的CRT显示器由于设计制造上的原因，只能接收模拟信号输入，因此计算机内

部的显卡负责进行数模转换，而VGA接口就是显卡上输出模拟信号的接口。如今液晶显示器虽

然可以直接接收数字信号，但是为了兼容显卡上的VGA接口，也大都支持VGA标准。

VGA接口定义及各引脚功能说明如图 18.1.2所示，我们一般只用到其中的1（RED）、2

（GREEN）、3（BLUE）、13（HSYNC）、14(VSYNC)信号。引脚1、2、3分别输出红、绿、蓝三原

色模拟信号，电压变化范围为 0~0.714V，0V代表无色，0.714V 代表满色；引脚13、14输出TTL

电平标准的行/场同步信号。

程中的同步时序分为行时序和场时序：

不同分辨率的VGA时序参数
时钟频率 = 行帧长 × 列帧长 * 刷新率,640 ×480 60HZ对应时钟频率= 800 ×525 × 60 = 25.2M，因此需要用分频时钟来做或者手动设置二分频。

颜色显示：

FPGA管脚输出的颜色数据位宽为16bit，数据格式为RGB565，即数据高5位表示红色，中间6位表示绿色，低5位表示蓝色。RGB565格式的数据一共可表示65536种颜色，此外常用的颜色数据格式还有RGB888，数据位宽越大，可以表示的颜色种类就越丰富。

VGA接口：

引脚分配：

二. VGA显示彩色条纹

分辨率控制部分：


```c
`define vga_640_480
`define vga_1920_1080
`define vga_1024_768`ifdef  vga_640_480//执行操作A`define H_Right_Border 8`define H_Front_Porch  8`define H_Sync_Time    96`define H_Back_Porch   40`define H_Left_Border  8`define H_Data_Time    640`define H_Total_Time   800`define V_Bottom_Border 8`define V_Front_Porch   2`define V_Sync_Time     2`define V_Back_Porch    25`define V_Top_Border    8`define V_Data_Time     480`define V_Total_Time    525`elsif  vga_1920_1080//执行操作B`define H_Right_Border 0`define H_Front_Porch  88`define H_Sync_Time    44`define H_Back_Porch   148`define H_Left_Border  0`define H_Data_Time    1920`define H_Total_Time   2200`define V_Bottom_Border 0`define V_Front_Porch   4`define V_Sync_Time     5`define V_Back_Porch    36`define V_Top_Border    0`define V_Data_Time     1080`define V_Total_Time    1125`elsif vga_1024_768 `define H_Right_Border 0`define H_Front_Porch  24`define H_Sync_Time    136`define H_Back_Porch   160`define H_Left_Border  0`define H_Data_Time    1024`define H_Total_Time   1344`define V_Bottom_Border 0 `define V_Front_Porch   3 `define V_Sync_Time     6 `define V_Back_Porch    29`define V_Top_Border    0 `define V_Data_Time     768 `define V_Total_Time    806`else`endif


```c
VAG驱动

`define vga_640_480`include "vga_para.v"module vga_ctrl(input                 clk         ,//时钟信号 //25.2MHZinput                 rst_n       ,//复位信号input         [23:0]  data_disp   ,output  reg   [10:0]  h_addr      ,//数据有效显示区域行地址output  reg   [10:0]  v_addr      ,//数据有效显示区域场地址output  reg           vsync       ,output  reg           hsync       ,output  reg   [7 :0]  vga_r       ,output  reg   [7 :0]  vga_b       ,output  reg   [7 :0]  vga_g       ,output  wire          vga_blk     ,output  wire          vga_sync    ,output  reg           vga_clk      //25.2MHZ
);//参数定义parameter   H_SYNC_START = 1,H_SYNC_STOP  = `H_Sync_Time ,H_DATA_START = `H_Sync_Time + `H_Back_Porch + `H_Left_Border,H_DATA_STOP  = `H_Sync_Time + `H_Back_Porch + `H_Left_Border + `H_Data_Time,V_SYNC_START = 1,V_SYNC_STOP  = `V_Sync_Time,V_DATA_START = `V_Sync_Time + `V_Back_Porch + `V_Top_Border,V_DATA_STOP  = `V_Sync_Time + `V_Back_Porch + `V_Top_Border + `V_Data_Time;//信号定义reg     [11:0]  cnt_h_addr  ;//行地址计数器wire            add_h_addr  ;wire            end_h_addr  ;reg     [11:0]  cnt_v_addr  ;//长地址计数器wire            add_v_addr  ;wire            end_v_addr  ;assign vga_sync = 1'b0;assign vga_blk = ~((cnt_h_addr<`H_Front_Porch + `H_Sync_Time + `H_Back_Porch)||(cnt_v_addr<`V_Front_Porch + `V_Sync_Time + `V_Back_Porch)); always@(posedge vga_clk or negedge rst_n)beginif(!rst_n)begincnt_h_addr <= 12'd0;endelse if(add_h_addr)beginif(end_h_addr)begincnt_h_addr <= 12'd0;endelse begincnt_h_addr <= cnt_h_addr + 12'd1;endendelse begincnt_h_addr <= 12'd0;endendassign add_h_addr = 1'b1;assign end_h_addr = add_h_addr && cnt_h_addr == `H_Total_Time - 1;always@(posedge vga_clk or negedge rst_n)beginif(!rst_n)begincnt_v_addr <= 12'd0;endelse if(add_v_addr)beginif(end_v_addr)begincnt_v_addr <= 12'd0;endelse begincnt_v_addr <= cnt_v_addr + 12'd1;endendelse begincnt_v_addr <= cnt_v_addr;endendassign add_v_addr = end_h_addr;assign end_v_addr = add_v_addr && cnt_v_addr == `V_Total_Time - 1;//行场同步信号always@(posedge vga_clk or negedge rst_n)beginif(!rst_n)beginhsync <= 1'b1;endelse if(cnt_h_addr == H_SYNC_START - 1)beginhsync <= 1'b0;endelse if(cnt_h_addr == H_SYNC_STOP - 1)beginhsync <= 1'b1;endelse beginhsync <= hsync;endendalways@(posedge vga_clk or negedge rst_n)beginif(!rst_n)beginvsync <= 1'b1;endelse if(cnt_v_addr == V_SYNC_START - 1)beginvsync <= 1'b0;endelse if(cnt_v_addr == V_SYNC_STOP - 1)beginvsync <= 1'b1;endelse beginvsync <= vsync;endendalways@(posedge clk or negedge rst_n)beginif(!rst_n)beginvga_clk =0;endelse beginvga_clk = ~vga_clk;endend //数据有效显示区域定义always@(posedge vga_clk or negedge rst_n)beginif(!rst_n)beginh_addr <= 11'd0;endelse if((cnt_h_addr >= H_DATA_START - 1) &&( cnt_h_addr <= H_DATA_STOP - 1))beginh_addr <= cnt_h_addr - H_DATA_START - 1;endelse beginh_addr <= 11'd0;endendalways@(posedge vga_clk or negedge rst_n)beginif(!rst_n)beginv_addr <= 11'd0;endelse if((cnt_v_addr >= V_DATA_START - 1) && (cnt_v_addr <= V_DATA_STOP - 1))beginv_addr <= cnt_v_addr - V_DATA_START -1;endelse beginv_addr <= 11'd0;endend//显示数据always@(posedge vga_clk or negedge rst_n)beginif(!rst_n)beginvga_r <= 8'b0;vga_g <= 8'b0;vga_b <= 8'b0;endelse if((cnt_h_addr >= H_DATA_START - 1) &&( cnt_h_addr <= H_DATA_STOP - 1) && (cnt_v_addr >= V_DATA_START - 1) && (cnt_v_addr <= V_DATA_STOP - 1))beginvga_r <= data_disp[23:16];vga_g <= data_disp[15: 8];vga_b <= data_disp[7 : 0];endelse beginvga_r <= 8'b0;vga_g <= 8'b0;vga_b <= 8'b0;endendendmodule

颜色显示：

module data_gen(input                   clk     ,//时钟信号input                   rst_n   ,//复位信号input       [10:0]      h_addr  ,//数据有效显示区域地址input       [10:0]      v_addr  ,//数据有效显示区域地址output  reg [23:0]      data_disp
);
//参数定义parameter   BLACK       = 24'h000000,RED         = 24'hFF0000,GREEN       = 24'h00FF00,BLUE        = 24'h0000FF,YELLOW      = 24'hFFFF00,SKY_BULE    = 24'h00FFFF,PURPLE      = 24'hFF00FF,GREY        = 24'hC0C0C0,WIGHT       = 24'hFFFFFF;always@(posedge clk or negedge rst_n)beginif(!rst_n)begindata_disp <= BLACK;endelse begincase(h_addr)0  : data_disp <= RED;80 : data_disp <= GREEN;160: data_disp <= BLUE;240: data_disp <= YELLOW;320: data_disp <= SKY_BULE;400: data_disp <= PURPLE;480: data_disp <= GREY;560: data_disp <= WIGHT;default:data_disp <= data_disp;endcaseendendendmodule

顶层模块：

module vga_top(input                  clk         ,//时钟信号input                  rst_n       ,//复位信号output  wire           vsync       ,output  wire           hsync       ,output  wire   [7 :0]  vga_r       ,output  wire   [7 :0]  vga_b       ,output  wire   [7 :0]  vga_g       ,output                 vga_blk     ,output  wire           vga_sync    ,output                 vga_clk
);wire     [23:0]      data_disp   ;wire     [10:0]      h_addr      ;wire     [10:0]      v_addr      ;data_gen u_data_gen(.clk        (vga_clk    ),//时钟信号.rst_n      (rst_n      ),//复位信号.h_addr     (h_addr     ),//数据有效显示区域地址.v_addr     (v_addr     ),//数据有效显示区域地址.data_disp  (data_disp  )
);vga_ctrl u_vga_ctrl(.clk         (clk       ),//时钟信号 25.2MHZ.rst_n       (rst_n     ),//复位信号.data_disp   (data_disp ),.h_addr      (h_addr    ),//数据有效显示区域行地址.v_addr      (v_addr    ),//数据有效显示区域场地址.vsync       (vsync     ),.hsync       (hsync     ),.vga_r       (vga_r     ),.vga_b       (vga_b     ),.vga_g       (vga_g     ),.vga_blk     (vga_blk   ),.vga_sync    (vga_sync  ),.vga_clk     (vga_clk   )
);endmodule

结果显示：

三字符显示

这里需要显示字符，需要用到汉字点阵工具，在这里我们使用取模软件“PCtoLCD2002”来获

取汉字“正点原子”的字模

姓名：

另存为bmp文件，再点击文件打开bpm文件，进入图像模式

生成字模：

{0020002000202020FC501020105013FE},
{108882221124422412124A207C100BFC},
{11FC1284100412881008E24810882250},
{1C502220E02024504010248800100906}

最终得到

0020002000200000000000000000000000000000000000000000000000000000
7E20002020200000000000000000000000000000000000000000000000000000
0220FC5010200000000000000000000000000000000000000000000000000000
0420105013FE000007F00FE000800FE007E01FFC07E007F007E007F000801FFC
0820108882220000081830180780301818183008181808181818081807803008
08A8112442240000100038180180300C381C2010381C1000381C100001802010
0AA412124A200000300000180180700C300C0020300C3000300C300001800020
0CA47C100BFCFFFF37F000600180301C300C0040300C37F0300C37F001800040
392211FC12840000380C01F00180382C300C0080300C380C300C380C01800080
C922100412880000300C001801800FCC300C0180300C300C300C300C01800180
0A221008E2480000300C000C0180001C300C0300300C300C300C300C01800300
0820108822500000300C380C01800018381803003818300C3818300C01800300
08201C502220000018183018018038301C1003801C1018181C10181801800380
0820E0202450000007E00FE00FF80FC007E0030007E007E007E007E00FF80300
28A0401024880000000000000000000000000000000000000000000000000000
1040001009060000000000000000000000000000000000000000000000000000

代码部分：

module vga_driver(
OSC_50,     //原CLK2_50时钟信号
VGA_CLK,    //VGA自时钟
VGA_HS,     //行同步信号
VGA_VS,     //场同步信号
VGA_BLANK,  //复合空白信号控制信号  当BLANK为低电平时模拟视频输出消隐电平，此时从R9~R0,G9~G0,B9~B0输入的所有数据被忽略
VGA_SYNC,   //符合同步控制信号      行时序和场时序都要产生同步脉冲
VGA_R,      //VGA绿色
VGA_B,      //VGA蓝色
VGA_G);     //VGA绿色input OSC_50;     //外部时钟信号CLK2_50output VGA_CLK,VGA_HS,VGA_VS,VGA_BLANK,VGA_SYNC;output [7:0] VGA_R,VGA_B,VGA_G;parameter H_FRONT = 16;     //行同步前沿信号周期长parameter H_SYNC = 96;      //行同步信号周期长parameter H_BACK = 48;      //行同步后沿信号周期长parameter H_ACT = 640;      //行显示周期长parameter H_BLANK = H_FRONT+H_SYNC+H_BACK;        //行空白信号总周期长parameter H_TOTAL = H_FRONT+H_SYNC+H_BACK+H_ACT;  //行总周期长耗时parameter V_FRONT = 11;     //场同步前沿信号周期长parameter V_SYNC = 2;       //场同步信号周期长parameter V_BACK = 31;      //场同步后沿信号周期长parameter V_ACT = 480;      //场显示周期长parameter V_BLANK = V_FRONT+V_SYNC+V_BACK;        //场空白信号总周期长parameter V_TOTAL = V_FRONT+V_SYNC+V_BACK+V_ACT;  //场总周期长耗时reg [10:0] H_Cont;        //行周期计数器reg [10:0] V_Cont;        //场周期计数器wire [7:0] VGA_R;         //VGA红色控制线wire [7:0] VGA_G;         //VGA绿色控制线wire [7:0] VGA_B;         //VGA蓝色控制线reg VGA_HS;reg VGA_VS;reg [10:0] X;             //当前行第几个像素点reg [10:0] Y;             //当前场第几行reg CLK_25;always@(posedge OSC_50)begin CLK_25=~CLK_25;         //时钟end assign VGA_SYNC = 1'b0;   //同步信号低电平assign VGA_BLANK = ~((H_Cont<H_BLANK)||(V_Cont<V_BLANK));  //当行计数器小于行空白总长或场计数器小于场空白总长时，空白信号低电平assign VGA_CLK = ~CLK_to_DAC;  //VGA时钟等于CLK_25取反assign CLK_to_DAC = CLK_25;always@(posedge CLK_to_DAC)beginif(H_Cont<H_TOTAL)           //如果行计数器小于行总时长H_Cont<=H_Cont+1'b1;      //行计数器+1else H_Cont<=0;              //否则行计数器清零if(H_Cont==H_FRONT-1)        //如果行计数器等于行前沿空白时间-1VGA_HS<=1'b0;             //行同步信号置0if(H_Cont==H_FRONT+H_SYNC-1) //如果行计数器等于行前沿+行同步-1VGA_HS<=1'b1;             //行同步信号置1if(H_Cont>=H_BLANK)          //如果行计数器大于等于行空白总时长X<=H_Cont-H_BLANK;        //X等于行计数器-行空白总时长   （X为当前行第几个像素点）else X<=0;                   //否则X为0endalways@(posedge VGA_HS)beginif(V_Cont<V_TOTAL)           //如果场计数器小于行总时长V_Cont<=V_Cont+1'b1;      //场计数器+1else V_Cont<=0;              //否则场计数器清零if(V_Cont==V_FRONT-1)       //如果场计数器等于场前沿空白时间-1VGA_VS<=1'b0;             //场同步信号置0if(V_Cont==V_FRONT+V_SYNC-1) //如果场计数器等于行前沿+场同步-1VGA_VS<=1'b1;             //场同步信号置1if(V_Cont>=V_BLANK)          //如果场计数器大于等于场空白总时长Y<=V_Cont-V_BLANK;        //Y等于场计数器-场空白总时长    （Y为当前场第几行）  else Y<=0;                   //否则Y为0endreg valid_yr;always@(posedge CLK_to_DAC)if(V_Cont == 10'd32)         //场计数器=32时valid_yr<=1'b1;           //行输入激活else if(V_Cont==10'd512)     //场计数器=512时valid_yr<=1'b0;           //行输入冻结wire valid_y=valid_yr;       //连线   reg valid_r;            always@(posedge CLK_to_DAC)   if((H_Cont == 10'd32)&&valid_y)     //行计数器=32时valid_r<=1'b1;                   //像素输入激活else if((H_Cont==10'd512)&&valid_y) //行计数器=512时 valid_r<=1'b0;                   //像素输入冻结wire valid = valid_r;               //连线wire[10:0] x_dis;     //像素显示控制信号wire[10:0] y_dis;     //行显示控制信号assign x_dis=X;       //连线Xassign y_dis=Y;       //连线Yparameterchar_line00=240'h0020002000200000000000000000000000000000000000000000000000000000,char_line01=240'h7E20002020200000000000000000000000000000000000000000000000000000,char_line02=240'h0220FC5010200000000000000000000000000000000000000000000000000000,char_line03=240'h0420105013FE000007F00FE000800FE007E01FFC07E007F007E007F000801FFC,char_line04=240'h0820108882220000081830180780301818183008181808181818081807803008,char_line05=240'h08A8112442240000100038180180300C381C2010381C1000381C100001802010,char_line06=240'h0AA412124A200000300000180180700C300C0020300C3000300C300001800020,char_line07=240'h0CA47C100BFCFFFF37F000600180301C300C0040300C37F0300C37F001800040,char_line08=240'h392211FC12840000380C01F00180382C300C0080300C380C300C380C01800080,char_line09=240'hC922100412880000300C001801800FCC300C0180300C300C300C300C01800180,char_line0a=240'h0A221008E2480000300C000C0180001C300C0300300C300C300C300C01800300,char_line0b=240'h0820108822500000300C380C01800018381803003818300C3818300C01800300,char_line0c=240'h08201C502220000018183018018038301C1003801C1018181C10181801800380,char_line0d=240'h0820E0202450000007E00FE00FF80FC007E0030007E007E007E007E00FF80300,char_line0e=240'h28A0401024880000000000000000000000000000000000000000000000000000,char_line0f=240'h1040001009060000000000000000000000000000000000000000000000000000;reg[7:0] char_bit;always@(posedge CLK_to_DAC)if(X==10'd144)char_bit<=9'd240;   //当显示到144像素时准备开始输出图像数据else if(X>10'd144&&X<10'd384)     //左边距屏幕144像素到416像素时    416=144+272（图像宽度）char_bit<=char_bit-1'b1;       //倒着输出图像信息reg[29:0] vga_rgb;                //定义颜色缓存always@(posedge CLK_to_DAC) if(X>10'd144&&X<10'd384)    //X控制图像的横向显示边界：左边距屏幕左边144像素  右边界距屏幕左边界416像素begin case(Y)            //Y控制图像的纵向显示边界：从距离屏幕顶部160像素开始显示第一行数据10'd160:if(char_line00[char_bit])vga_rgb<=30'b1111111111_0000000000_0000000000;  //如果该行有数据 则颜色为红色else vga_rgb<=30'b0000000000_0000000000_0000000000;                      //否则为黑色10'd162:if(char_line01[char_bit])vga_rgb<=30'b1111111111_0000000000_0000000000;else vga_rgb<=30'b0000000000_0000000000_0000000000;10'd163:if(char_line02[char_bit])vga_rgb<=30'b1111111111_0000000000_0000000000;else vga_rgb<=30'b0000000000_0000000000_0000000000;10'd164:if(char_line03[char_bit])vga_rgb<=30'b1111111111_0000000000_0000000000;else vga_rgb<=30'b0000000000_0000000000_0000000000;10'd165:if(char_line04[char_bit])vga_rgb<=30'b1111111111_0000000000_0000000000;else vga_rgb<=30'b0000000000_0000000000_0000000000; 10'd166:if(char_line05[char_bit])vga_rgb<=30'b1111111111_0000000000_0000000000;else vga_rgb<=30'b0000000000_0000000000_0000000000;10'd167:if(char_line06[char_bit])vga_rgb<=30'b1111111111_0000000000_0000000000;else vga_rgb<=30'b0000000000_0000000000_0000000000; 10'd168:if(char_line07[char_bit])vga_rgb<=30'b1111111111_0000000000_0000000000;else vga_rgb<=30'b0000000000_0000000000_0000000000;10'd169:if(char_line08[char_bit])vga_rgb<=30'b1111111111_0000000000_0000000000;else vga_rgb<=30'b0000000000_0000000000_0000000000; 10'd170:if(char_line09[char_bit])vga_rgb<=30'b1111111111_0000000000_0000000000;else vga_rgb<=30'b0000000000_0000000000_0000000000;10'd171:if(char_line0a[char_bit])vga_rgb<=30'b1111111111_0000000000_0000000000;else vga_rgb<=30'b0000000000_0000000000_0000000000;10'd172:if(char_line0b[char_bit])vga_rgb<=30'b1111111111_0000000000_0000000000;else vga_rgb<=30'b0000000000_0000000000_0000000000;10'd173:if(char_line0c[char_bit])vga_rgb<=30'b1111111111_0000000000_0000000000;else vga_rgb<=30'b0000000000_0000000000_0000000000;10'd174:if(char_line0d[char_bit])vga_rgb<=30'b1111111111_0000000000_0000000000;else vga_rgb<=30'b0000000000_0000000000_0000000000;10'd175:if(char_line0e[char_bit])vga_rgb<=30'b1111111111_0000000000_0000000000;else vga_rgb<=30'b0000000000_0000000000_0000000000;10'd176:if(char_line0f[char_bit])vga_rgb<=30'b1111111111_0000000000_0000000000;else vga_rgb<=30'b0000000000_0000000000_0000000000;default:vga_rgb<=30'h0000000000;   //默认颜色黑色endcase endelse  vga_rgb<=30'h000000000;             //否则黑色assign VGA_R=vga_rgb[23:16];assign VGA_G=vga_rgb[15:8];assign VGA_B=vga_rgb[7:0];
endmodule

结果如下:

四. 图片显示

由于一张640×480的24位的图片的大小超过了芯片的内存，无法把图片保存进去，故采用一张128*78的图片进行显示。
原图：

转换得到HEX文件

调用rom核来完成

设置位宽度为16位，大小为图片大小128×78 = 9984

取消勾选：

找到刚才生成的data1.hex文件

result：