/*-----------------------------------------------------------------------Date                :        2017-XX-XX
Description            :        Design for .-----------------------------------------------------------------------*/module vga_control
(//global clockinput                    clk,            //system clockinput                    rst_n,             //sync reset//vga interfaceinput            [10:0]    value_x,input            [10:0]    value_y,output            [23:0]    rgb,//rom interfaceoutput    reg        [15:0]    rom_addr,        //
    input            [23:0]    rom_q
); //--------------------------------
//Funtion :    display_区域           wire        display_addr;
assign        display_addr    =    ((value_x >= 8'd100 && value_x < 9'd300) && (value_y >= 8'd100 && value_y < 9'd300)) ? 1'b1 : 1'b0;//--------------------------------
//Funtion :    rgbassign        rgb                =    (display_addr == 1'b1) ? rom_q : 1'd0; //--------------------------------
//Funtion :    rom_addrwire        [10:0]        display_x;
wire        [10:0]        display_y;assign            display_x        =    value_x - 8'd100;
assign            display_y        =    value_y    - 8'd100;always @(posedge clk or negedge rst_n)
beginif(!rst_n)rom_addr <= 1'd0;else if(display_addr)rom_addr <= display_x  +  display_y*200;elserom_addr <= 1'd0;
endendmodule

//--------------------------------
//Funtion :    rgb//assign        rgb                =    (display_addr == 1'b1) ? rom_q : 1'd0;
assign        rgb                =    (display_addr == 1'b1) ? {3{gray}} : 1'd0; //--------------------------------
//Funtion :    转灰度处理
wire        [7:0]        gray;assign        gray = (rom_q[23:16]*19595 + rom_q[15:8]*38469 + rom_q[7:0]*7472) >> 16;