HDL语言：VERILOG
CPLD芯片：XC95144XL-10T100I
SRAM芯片：IS63lv1024
晶振：40M
LED2电路已经可行。

以下是程序：
module OprateSRAM(clk,key,Addr_OUT,_CE_OUT,_OE_OUT,_WE_OUT,LED2_Flash,LED5_Flash,DMX_out1,DATA_INOUT);
input clk;
input key;
output _CE_OUT;
output _OE_OUT;
output _WE_OUT;
output LED2_Flash;
output LED5_Flash;
output DMX_out1;
output[15:0] Addr_OUT;
inout[7:0] DATA_INOUT;
reg [15:0] Addr_OUT_reg;
reg _CE_OUT_reg;
reg _OE_OUT_reg;
reg _WE_OUT_reg;
reg DMX_out1_reg;
reg [7:0] DATA_WRITE_BUFFER;
wire [7:0] DATA_READ_BUFFER;
reg [7:0] DATA_READ_BUFFER2;
wire r_en = _WE_OUT & (~_CE_OUT) & (~_OE_OUT);
wire w_en = (~_WE_OUT) & (~_CE_OUT);

//reg SRAM_RE_WR_OK;
reg LED2_Flash_reg_1Hz_buffer; // buffer,middile
reg LED2_Flash_reg;        // putout
reg [21:0] LED2_Flash_1Hz_count; // count
reg LED5_Flash_reg;
reg [5:0] state;
reg WR_RD_Return;
parameter
IDLE    = 6'b000_001,
READY    = 6'b000_010,
WR_DataNew = 6'b000_100,
WR_AddrNew = 6'b001_000,
RD_DataNew = 6'b010_000,
RD_AddrNew = 6'b100_000,
   WR       = 1,
   RD     = 0;

assign LED2_Flash = LED2_Flash_reg;
assign LED5_Flash = LED5_Flash_reg;
assign DMX_out1 = DMX_out1_reg;
assign _WE_OUT   = _WE_OUT_reg;
assign _CE_OUT   = _CE_OUT_reg;
assign _OE_OUT   = _OE_OUT_reg;
assign DATA_INOUT = w_en? DATA_WRITE_BUFFER:8'bz;
assign DATA_READ_BUFFER = r_en? DATA_INOUT:8'bz;
assign Addr_OUT = Addr_OUT_reg;
initial
begin
   state <= IDLE;
   WR_RD_Return <= WR;
   Addr_OUT_reg <= 16'b0000_0000_0000_0000;
end
/*******************************************************************
* description: use to creat 1Hz wave,
*    LED2 flashing to show the CPLD running
*******************************************************************/
always @ (posedge clk)
begin
   if(LED2_Flash_1Hz_count == 3999999)
begin
   LED2_Flash_1Hz_count <= 0;
   LED2_Flash_reg_1Hz_buffer <= 1'b0;
end
else
begin
   LED2_Flash_1Hz_count <= LED2_Flash_1Hz_count + 22'b0001;
   LED2_Flash_reg_1Hz_buffer <= 1'b1;
end
end
/*****************************************************************
* LED2 Flashing
* thought LED2 to check the operate
******************************************************************/
always @ (posedge LED2_Flash_reg_1Hz_buffer)
begin
   if (DATA_READ_BUFFER2 == 8'b0000_0001)
   begin   // if Write and read SROM OK, LED2 will flashing
if(LED2_Flash_reg == 1)
       LED2_Flash_reg <= 1'b0;
else
   LED2_Flash_reg <= 1'b1;
   end
   else
    LED2_Flash_reg <= 1'b1;
///*
   if (key == 1'b0)
   begin   // here ,the key putdown ,LED5 flashing ,test LED5 hardware
if(LED5_Flash_reg == 1)
       LED5_Flash_reg <= 1'b0;
else
   LED5_Flash_reg <= 1'b1;
   end
   else
    LED5_Flash_reg <= 1'b1;
//*/
end
/*******************************************************************
*
*   key , then push the key ,write one time and read one time
* SRAM IS63LV1024, to test SRAM operate
*
*********************************************************************/
always @(posedge clk)
begin
//使用状态机的读写SRAM程序
case(state)
IDLE:
   begin
   _CE_OUT_reg <= 1'b0;
   _OE_OUT_reg <= 1'b1;
   _WE_OUT_reg <= 1'b1;
    DATA_READ_BUFFER2 <= DATA_READ_BUFFER;
    if(WR_RD_Return == WR)
      state <= WR_AddrNew;
    else if(WR_RD_Return == RD)
   state <= RD_AddrNew;
    else
   state <= 0;
   end
READY:
       begin
       Addr_OUT_reg <= 16'b0000_0000_0000_0000;
   DATA_WRITE_BUFFER   <= 8'b0000_0000;
   state <= IDLE;
   end
WR_AddrNew:
   begin
   //Addr_OUT_reg <= Addr_OUT_reg + 16'b1;
    //DATA_WRITE_BUFFER   <= DATA_WRITE_BUFFER + 8'b1;
       Addr_OUT_reg <= 16'b0000_0000_0000_0001;
   DATA_WRITE_BUFFER   <= 8'b0000_0001;
   state <= WR_DataNew;
   end
WR_DataNew:
   begin
    _CE_OUT_reg <= 1'b0;
    _WE_OUT_reg <= 1'b0;
    _OE_OUT_reg <= 1'bz;
    WR_RD_Return <= RD;
   state <= IDLE;
   end
RD_AddrNew:
   begin
   Addr_OUT_reg <= 16'b0000_0000_0000_0001;
   
   state <= RD_DataNew;
   end
RD_DataNew:
   begin
    _WE_OUT_reg <= 1'b1;
    _CE_OUT_reg <= 1'b0;
    _OE_OUT_reg <= 1'b0;
    WR_RD_Return <= 1'bz;
    state <= IDLE;   
   end  
endcase  
end
endmodule