版图绘制及Virtuoso的使用,周海峰 2008年9月24日,2019/4/18,共85页,2,典型深亚微米工艺流程 Design Rule的简介 Virtuoso软件的简介及使用 版图设计中的相关主题,2019/4/18,共85页,3,1 典型深亚微米工艺流程,这里介绍目前比较普通的N阱CMOS工艺流程，用到的wafer是p型衬底，所以需要用nWELL来构建p沟器件，而n型MOS管就构建在p衬底上，而对于SMIC工艺来讲，NMOS构建在nWELL的反版也就是pWELL中。,2019/4/18,共85页,4,第一张mask定义为n-well(or n-tub)mask a)离子注入：制造nwell。 b)扩散：在所有方向上扩散，扩散越深，横向也延伸越多。,2019/4/18,共85页,5,第二张mask定义为active mask。 有源区用来定义管子的栅以及允许注入的p型或者n型扩散的管子的源漏区。,2019/4/18,共85页,6,忽略版图中无法体现的一些mask：诸如channel stop、阈值电压调整等 要介绍的第三张mask为poly mask： 它包含了多晶硅栅以及需要腐蚀成的形状。这还用来定义源漏的自对准。,2019/4/18,共85页,7,第四张mask定义为n＋mask，用来定义需要注入n＋的区域。可以看到多晶硅栅用来作为源漏的自对准层。这里的注入为两次注入，首先轻掺杂注入，在栅上生成一层氧化层后再重掺杂注入，形成LDD结构。,2019/4/18,共85页,8,第五张mask是p＋mask。 p＋在Nwell中用来定义PMOS管或者走线；p＋在 Pwell中用来作为欧姆接触。LDD不必用来形成 PMOS，这是因为热载流子在PMOS中受影响小。,2019/4/18,共85页,9,第六张mask就是定义接触孔了。 首先腐蚀SiO2到需要接触的层的表面。其次要能够 使金属接触到扩散区或者多晶硅区。,2019/4/18,共85页,10,第七张mask就是金属1(metal1)了。 需要选择性刻蚀出电路所需要的连接关系。 至此，一个反相器的完整版图就完成了。,2019/4/18,共85页,11,2 Design Rule的简介,图解术语,2019/4/18,共85页,12,2019/4/18,共85页,13,2019/4/18,共85页,14,一个简单的例子,2019/4/18,共85页,15,3 Virtuoso软件的简介及使用,You use the Virtuoso layout tools to prepare custom integrated circuit designs. Create and edit polygons, paths, rectangles, circles, ellipses, donuts, pins, and contacts in layout cellviews Place cells into other cells to create hierarchical designs Connect a pin or group of pins in a net internally or externally Create special pcells or use SKILL language commands,2019/4/18,共85页,16,Starting the Layout Editor,To start the Virtuoso layout editor software, you must type the name of an executable in an xterm window. layout – includes the layout editor, Assura internactive verification products, plotting, and physical translators layoutPlus – includes all of the above, plus the Virtuoso compactor and Virtuoso XL icfb – includes all cadence custom IC design tools, front to back design environment,2019/4/18,共85页,17,Create Layout Cellview,File-New-Cellview,2019/4/18,共85页,18,Virtuoso Layout Editor Design Window,2019/4/18,共85页,19,Using the Icon Menu,2019/4/18,共85页,20,Controlling the Icon Menu,You can control CIW-Option-User… Where the icon menu appears Whether the menu appears at all Whether icon names appear,2019/4/18,共85页,21,Layout Editor 菜单(1),Abstract用于版图抽取，Dracula Interactive用于Dracula工具进行DRC等 Verify菜单下的DRC等是用于Diva工具的。,2019/4/18,共85页,22,Layout Editor 菜单(2),2019/4/18,共85页,23,Setting Up Your Environment,Setting Layout Editor Defaults: Before you can start working in the Virtuoso layout editor, several startup files must be initiated. Some of the things these files do include setting up your environment, pointing to libraries, and defining your plotters.,2019/4/18,共85页,24,Startup Files,File .cdsenv Purpose Holds application defaults for environment variables. User location ~/.cdsenv Sample location your_install_dir/tools/dfII/samples/.cdsenv System default location ./.cdsenv,2019/4/18,共85页,25,File .cdsinit Purpose A Cadence SKILL language file executed when the Cadence design framework II (DFII) product starts. User location ~/.cdsinit Sample location your_install_dir/tools/dfII/samples/local/cdsinit System default location ./.cdsinit File cds.lib Purpose Sets the paths to libraries and other cds.lib files. INCLUDE your_install_dir/share/cdssetup/cds.lib,2019/4/18,共85页,26,File .cdsplotinit Purpose Initialization script for plot operations. User location ~/.cdsplotinit Sample location your_install_dir/tools/plot/samples/cdsplotinit.sample System default location ./.cdsplotinit,2019/4/18,共85页,27,File display.drf Purpose Specifies how you want your layers to appear on your monitor and in your plots. User location ~/display.drf Sample location your_install_dir/share/cdssetup/dfII/default.drf System default location ./display.drf,2019/4/18,共85页,28,Using the Display Options Form,2019/4/18,共85页,29,Using the Layout Editor Options Form,2019/4/18,共85页,30,Layer Selection Window(LSW),The LSW lets you choose the design layer for each shape you create, make design layers visible or invisible, or make instances and pins selectable or unelectable.,2019/4/18,共85页,31,Setting Valid Layers,Choose Edit – Set Valid Layers in the LSW,2019/4/18,共85页,32,Making One Layer Selectable or Unselectable,In the LSW, click middle on the layer. The layer color disappears. The layer name is shaded, to show that the layer is also unselectable.,2019/4/18,共85页,33,Making All but One Layer Unselectable,In the LSW, press Shift and click middle on the layer you want to be the only selectable layer.,2019/4/18,共85页,34,Using Search,The Search command lets you search for objects with specific attributes or property values.,2019/4/18,共85页,35,Virtuoso下的快捷键的使用(1),Ctrl＋A 全选 Shift＋B Return，升到上一级视图 Ctrl＋C 中断某个命令，一般用ESC代替。 Shift＋C 裁切(chop)。 C 复制。复制某个图形 Ctrl＋D 取消选择。亦可点击空白处实现。 Ctrl＋F显示上层等级 Shift＋F显示所有等级 F fit，显示你画的所有图形 K 标尺工具 Shift＋K清除所有标尺。 L 标签工具,M 移动工具 Shift＋M 合并工具，Merge N 斜45对角＋正交。 Shift＋O 旋转工具。Rotate O 插入接触孔。 Ctrl＋P 插入引脚。 Pin Shift＋P 多边形工具。Polygon P 插入Path。路径。 Q 图形对象属性。选中一个图形先 R 矩形工具。绘制矩形图形。 S 拉伸工具。可以拉伸一个边。也可以选择要拉伸的组一起拉伸。 U 撤销。 Undo。 Shift＋U重复。Redo。撤销后反悔,2019/4/18,共85页,36,Virtuoso下的快捷键的使用(2),V 关联attach。将一个子图形(child)关联到一个父图形(parent)后，若移动parent，child也跟着移动；移动child，parent不会移动。 Ctrl＋W 关闭窗口。 Shift＋W下一个视图。 W 前一个视图。 Y 区域复制Yank。和copy有区别，copy只能复制完整图形对象。 Shift＋Y 黏贴Paste。配合Yank使用。 Ctrl＋Z 视图放大两倍。 Shift＋Z 视图缩小两倍。 Z 视图放大。,ESC键 撤销功能。 Tab键 平移视图Pan。按Tab，用鼠标点击视图区中某点，视图就会移至以该点为中心。 Delete键 删除。 BackSpace键 撤销上一点。这就不用因为Path一点画错而删除重画。可以撤销上一点。 Enter键 确定一个图形最后一点。也可以双击鼠标左键。 Ctrl＋方向键 移动Cell。 Shift＋方向键 移动鼠标。 方向键 移动视图。,2019/4/18,共85页,37,Design Access Problems,I Can’t Find a Library The library path in the cds.lib file is incorrect The library is not in the cds.lib file To fix either of these problems, - Edit your cds.lib file.,2019/4/18,共85页,38,I Can’t Open a Cellview,If you cannot open a cellview in a library, you might not have read access to the cellview files. To gain read access to the cellviews in a library, - Do one of the following: Change the access permissions using the Library Manager – Edit – Access Permissions form. Use the UNIX command chmod to change the access permissions in the UNIX directory containing the library.,2019/4/18,共85页,39,I Can’t Write to a Cellview,If you have write access to a library but cannot open a cellview to edit. You do not have write access for the cellview file Another user is editing the cellview and locked it -Do one of the following: Change the access permissions using the Library Manager – Edit – Access Permissions form. Use the UNIX command chmod to change the access permissions in the UNIX directory containing the library.,2019/4/18,共85页,40,Cell Instances Are Missing,A cellview often contains instances of cells from other design libraries. If you open a cellview that contains instances of cells from a library that the layout editor cannot find, the following happens: When you try to open the cellview, you see a warning dialog box listing cells that the layout editor cannot find When you close the dialog box, the cellview opens, but each area containing a missing cell displays a flashing box with an X,2019/4/18,共85页,41,These ares contain cell instances from a library that the layout editor cannot find. To include the missing cells, - Add the path to the library containing the cell masters to the cds.lib file.,2019/4/18,共85页,42,Right Mouse Button Doesn’t Work,By default, the right mouse button works as follow: To repeat the last command, click right once To zoom in, press and hold right and create a box To zoom out, press the Shift key and hold right and create a box To change options while using some editing commands, press and hold right,2019/4/18,共85页,43,If the right mouse button will not do any of these tasks, it is probably set to create strokes. To cancel the stroke-creation capability, you must exit and restart the Cadence software. To remove the stroke commands from your .cdsinit file. Type a semicolon (;) in front of stroke.il, defstrokes.il, def.strokes.,2019/4/18,共85页,44,How to Select Objects in a Dense Design,If you click on objects in a dense design and the layout editor does not select the object you want, try any of the following: If objects share the edge you chose, click again in the same place. If possible, move the cursor closer to another edge of the object and click. If possible, zoom in on the edge you want to select. Use the LSW,2019/4/18,共85页,45,About Messages,There are four types of messages:,2019/4/18,共85页,46,Working With Markers,To get information about a marker, use these commands: Verify - Markers - Explain displays the reason for the error or warning marker in a text window Verify - Markers - Find searches for and highlights each error or warning marker After you get the information you need, you can delete the marker using these commands Verify - Markers - Delete removes a specific marker Verify - Markers - Delete All removes all markers,2019/4/18,共85页,47,4 版图设计中的相关主题,Antenna Effect Dummy 的设计 Guard Ring 保护环的设计 Match的设计,2019/4/18,共85页,48,4.1 Antenna Effect,原因：大片面积的同层金属。导致：收集离子，提 高电势。结果：使氧化层击穿。解决如下：,2019/4/18,共85页,49,0.13um CMOS工艺中的天线规则,CT与有源区栅面积 VIA与有源区栅面积 累积Metal与有源区栅面积 有二极管保护的累积Metal与有源区栅面积 保护管面积大小对天线效应的影响,2019/4/18,共85页,50,4.2 Dummy 的设计,IC版图除了要体现电路的逻辑或功能确保LVS验证 正确外，还要增加一些与LVS(电路匹配)无关的 图形，以减小中间过程中的偏差，我们通常称这些 图形为dummy layer。有些dummy layer是为了防 止刻蚀时出现刻蚀不足或刻蚀过度而增加的，比如 metal density不足就需要增加一些metal dummy layer以增加metal密度。另外一些则是考虑到光的 反射与衍射，关键图形四周情况大致相当，避免因 曝光而影响到关键图形的尺寸。,2019/4/18,共85页,51,a、MOS dummy,在MOS两侧增加dummy poly，避免Length受到影响。 添加dummy管，可以提供更好的环境一致性,2019/4/18,共85页,52,b、RES dummy,类似于MOS dummy方法增加dummy，有时会在四周都加上。,2019/4/18,共85页,53,c、CAP dummy,2019/4/18,共85页,54,d、Interconnect,关键走线与左右或上下走线的屏蔽采用相同层或中间层连接VSS来处理。 也可增大两者间的间距来减少耦合。,2019/4/18,共85页,55,4.3 Guard Ring的设计,2019/4/18,共85页,56,保护环分两种：多数载流子保护环 、少数载流子保 护环 。少数载流子保护环是掺杂不同类型杂质，形 成反偏结提前收集引起闩锁的注入少数载流子。多 数载流子保护环是掺杂相同类型杂质，减小多数载 流子电流产生的降压。,2019/4/18,共85页,57,深阱guard ring的应用,SMIC提供深阱工艺(DNW)，可以用来有效隔离不同模块间的噪声。 这种隔离保护技术只应用在1.8V情况下。且只对NMOS管进行保护。,4.4、Match的设计,2019/4/18,共85页,59,a、MOS的match,对于大的宽长比的MOS管，常采用多指结构，降低栅电阻，减少噪声，提高工作的频率。 但是过多的fingers则是不利的。,2019/4/18,共85页,60,MOS管的对称性,差分对管：,2019/4/18,共85页,61,工艺梯度的影响,采用中心对称结构能够解决工艺梯度对电路性能的影响。 缺点是走线的复杂性增加，可能带来其他不利的寄生效应的影响。,2019/4/18,共85页,62,一维中心对称的MOS管layout,2019/4/18,共85页,63,其它一些MOS匹配的例子：,2019/4/18,共85页,64,交叉对称(1),2019/4/18,共85页,65,交叉对称(2),2019/4/18,共85页,66,b、RES 的匹配,一维对称结构：,2019/4/18,共85页,67,交叉对称,2019/4/18,共85页,68,c、PNP管对称：,Modeling RF IC Packages,2019/4/18,共85页,70,在PCS及无线通信中工作在射频段的器件日益增长，射频IC封装的寄生效应越发显得重要，诸如：阻抗失配、高频谐振以及pins和键合线之间的串扰等问题。这样有必要对系统进行精确的仿真，而精确的仿真需要这些寄生效应的精确模型。 对于IC封装有很多种类型，95％的IC封装采用SOIC(small outline IC)、QFP(quad flat pack)以及DIP(dual inline package)。基于这样的资讯，一款RF IC封装的建模工具被开发出来了。,2019/4/18,共85页,71,厂商提供的封装示意图,2019/4/18,共85页,72,启动,ZUEDA3% pkg & ZUEDA3% sourcing /opt/ic5033/tools/dfII/etc/pkg/init.coeffgen sourcing /opt/ic5033/tools/dfII/etc/pkg/init.pkg done. PKG的核心 物理几何尺寸建模模块 网状EM解决器 用来计算电容电感的3D EM解决器 后处理模块,2019/4/18,共85页,73,PKG支持的封装类型,SOIC 包括SSOP、TSSOP、VSO QFP 包括TQFP、LQFP DIP,2019/4/18,共85页,74,Package Physical Geometry Moedling,封装的体，一般是塑料或者陶瓷 lead frame，包括了pins和die的连接 键合线 die,2019/4/18,共85页,75,The PKG RF IC Package Modeler Form,2019/4/18,共85页,76,Option,2019/4/18,共85页,77,Package Dimension Setup,2019/4/18,共85页,78,Die Attach Setup,2019/4/18,共85页,79,Internal Lead Frame Setup,2019/4/18,共85页,80,Bond Wire Setup,2019/4/18,共85页,81,Parameter Extraction,2019/4/18,共85页,82,Macromodel Generation,最终在运行的目录下生成一个pkg.proj文件夹，cd进 去后可以找到我们需要的rfpkg.scs文件，或者上图 所填Macromodel Name.scs。这里建议填入rfpkg。 避免后面仿真时symbol与subckt名称不匹配。,2019/4/18,共85页,83,Simulation of Package Models in the Analog Circuit Design Environment,从rfExamples库中调用 rfpkg的symbol。左边代 表了封装外部的pins。 右边的端口代表了die上 的键合线的压焊块。,2019/4/18,共85页,84,修改库文件进行仿真,打开pkg生成的*.scs文件，在文件头尾分别添加如下语句： library any_name section tt ………… endsection tt endlibrary any_name 仿真时在添加仿真库文件时添加该*.scs文件即可。,谢谢！,

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