xilinx DDS ip 核测试使用

参考博客：数字信号处理（一）：Xilinx Vivado DDS IP核设计实例

DDS ip 0设置方法，其他默认设置。

DDS 1 设置情况，其他默认设置。

频率控制字：

主程序：

`timescale 1ns / 1ps
//
// Company:
// Engineer:
//
// Create Date: 2021/01/13 08:40:13
// Design Name:
// Module Name: dds_test
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//module dds_test(input sclk,  //100MHzinput rst_n,//单通道DDS信号输出output wire      dds1_tvalid,output wire [19:0]  dds1_sine,output wire [19:0]    dds1_cosine,output wire         m_axis_phase_tvalid,output wire [31:0]  m_axis_phase_tdata,//4通道DDS输出output wire m_axis_data_tvalid_m,output wire [47:0] m_axis_data_tdata_m,output wire m_axis_phase_tvalid_m,output wire [31:0] m_axis_phase_tdata_m,output wire [1:0] m_axis_data_tuser_m,output reg [19:0] m_dds_ch0_cosine,output reg [19:0] m_dds_ch0_sine,output reg [19:0] m_dds_ch1_cosine,output reg [19:0] m_dds_ch1_sine,output reg [19:0] m_dds_ch2_cosine,output reg [19:0] m_dds_ch2_sine,output reg [19:0] m_dds_ch3_cosine,output reg [19:0] m_dds_ch3_sine,output wire event_s_config_tlast_missing,output wire event_s_config_tlast_unexpected);//----------------------单通道DDS输出sine cosine-------------------//输出频率为1Mhzwire  [47:0]    m_axis_data_tdata;wire              m_axis_data_tvalid;assign dds1_sine  =m_axis_data_tdata[43:24];assign dds1_cosine=m_axis_data_tdata[19:0];dds_compiler_0 dds_single_out(.aclk(sclk),                                // input wire aclk.m_axis_data_tvalid(m_axis_data_tvalid),    // output wire m_axis_data_tvalid.m_axis_data_tdata(m_axis_data_tdata),      // output wire [47 : 0] m_axis_data_tdata.m_axis_phase_tvalid(m_axis_phase_tvalid),  // output wire m_axis_phase_tvalid.m_axis_phase_tdata(m_axis_phase_tdata)    // output wire [31 : 0] m_axis_phase_tdata);//------------------------4通道DDS输出sine cosine----------------------------//1------------1Mhz--------32'h28F5C2//2------------2Mhz--------51EB85//3------------3Mhz--------7AE147//4------------4MHz--------A3D70A//通道PINC配置  reg s_axis_config_tvalid;wire s_axis_config_tready;reg s_axis_config_tlast;reg [31:0] s_axis_config_tdata;reg [3:0] cnt;always @(posedge sclk)begin  //频率控制字的分时段选择if(rst_n==1'b0)begins_axis_config_tvalid<=1'b0;s_axis_config_tlast<=1'b0;s_axis_config_tdata<=32'h0;cnt<=4'b0;endelse begincase (cnt)4'd0:begins_axis_config_tvalid<=1'b0;s_axis_config_tlast<=1'b0;s_axis_config_tdata<=32'h0;cnt<=cnt+1'b1;end4'd1:begins_axis_config_tvalid<=1'b1;if(s_axis_config_tready==1'b1)begins_axis_config_tdata<=32'h28F5C2; //1Mhz的频率控制字cnt<=cnt+1'b1;endelse begincnt<=cnt;endend4'd2:beginif(s_axis_config_tready==1'b1)begins_axis_config_tdata<=32'h51EB85; //2Mhz的频率控制字cnt<=cnt+1'b1;endelse begincnt<=cnt;endend4'd3:beginif(s_axis_config_tready==1'b1)begins_axis_config_tdata<=32'h7AE147; //3Mhz的频率控制字cnt<=cnt+1'b1;endelse begincnt<=cnt;endend4'd4:beginif(s_axis_config_tready==1'b1)begins_axis_config_tdata<=32'hA3D70A; //4Mhz的频率控制字s_axis_config_tlast <= 1'b1;cnt<=cnt+1'b1;endelse begincnt<=cnt;endend4'd5: beginif(s_axis_config_tready==1'b1) begins_axis_config_tdata <= 32'h0;s_axis_config_tlast <= 1'b0;s_axis_config_tvalid <= 1'b0;cnt <= cnt + 1'b1;endelsecnt <= cnt;end4'd6: begincnt <= cnt;end endcaseendendalways @(posedge sclk)beginif(rst_n==1'b0)beginm_dds_ch0_cosine <= 20'd0;m_dds_ch0_sine <= 20'd0;m_dds_ch1_cosine <= 20'd0;m_dds_ch1_sine <= 20'd0;m_dds_ch2_cosine <= 20'd0;m_dds_ch2_sine <= 20'd0;m_dds_ch3_cosine <= 20'd0;m_dds_ch3_sine <= 20'd0;endelse begincase(m_axis_data_tuser_m)2'b00:beginm_dds_ch0_cosine <= m_axis_data_tdata_m[19:0];m_dds_ch0_sine <= m_axis_data_tdata_m[43:24];end2'b01:beginm_dds_ch1_cosine <= m_axis_data_tdata_m[19:0];m_dds_ch1_sine <= m_axis_data_tdata_m[43:24];end2'b10:beginm_dds_ch2_cosine <= m_axis_data_tdata_m[19:0];m_dds_ch2_sine <= m_axis_data_tdata_m[43:24];end2'b11:beginm_dds_ch3_cosine <= m_axis_data_tdata_m[19:0];m_dds_ch3_sine <= m_axis_data_tdata_m[43:24];endendcase endenddds_compiler_1 dds_four_out (.aclk(sclk),                                                        // input wire aclk.s_axis_config_tvalid(s_axis_config_tvalid),                        // input wire s_axis_config_tvalid.s_axis_config_tready(s_axis_config_tready),                        // output wire s_axis_config_tready.s_axis_config_tdata(s_axis_config_tdata),                          // input wire [31 : 0] s_axis_config_tdata.s_axis_config_tlast(s_axis_config_tlast),                          // input wire s_axis_config_tlast.m_axis_data_tvalid(m_axis_data_tvalid_m),                            // output wire m_axis_data_tvalid.m_axis_data_tready(1'b1),                            // input wire m_axis_data_tready.m_axis_data_tdata(m_axis_data_tdata_m),                              // output wire [47 : 0] m_axis_data_tdata.m_axis_data_tuser(m_axis_data_tuser_m),                              // output wire [1 : 0] m_axis_data_tuser.m_axis_phase_tvalid(m_axis_phase_tvalid_m),                          // output wire m_axis_phase_tvalid.m_axis_phase_tready(1'b1),                          // input wire m_axis_phase_tready.m_axis_phase_tdata(m_axis_phase_tdata_m),                            // output wire [31 : 0] m_axis_phase_tdata.event_s_config_tlast_missing(event_s_config_tlast_missing),        // output wire event_s_config_tlast_missing.event_s_config_tlast_unexpected(event_s_config_tlast_unexpected)  // output wire event_s_config_tlast_unexpected);endmodule

测试程序;

`timescale 1ns / 1ps
//
// Company:
// Engineer:
//
// Create Date: 2021/01/13 14:47:17
// Design Name:
// Module Name: dds_test_tb
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//module dds_test_tb();reg sclk;
reg rst_n;wire      dds1_tvalid;
wire [19:0] dds1_sine;
wire [19:0] dds1_cosine;
wire        m_axis_phase_tvalid;
wire [31:0] m_axis_phase_tdata;wire m_axis_data_tvalid_m;
wire [47:0] m_axis_data_tdata_m;
wire m_axis_phase_tvalid_m;
wire [31:0] m_axis_phase_tdata_m;
wire [1:0] m_axis_data_tuser_m;
wire [19:0] m_dds_ch0_cosine;
wire [19:0] m_dds_ch0_sine;
wire [19:0] m_dds_ch1_cosine;
wire [19:0] m_dds_ch1_sine;
wire [19:0] m_dds_ch2_cosine;
wire [19:0] m_dds_ch2_sine;
wire [19:0] m_dds_ch3_cosine;
wire [19:0] m_dds_ch3_sine;
wire event_s_config_tlast_missing;
wire event_s_config_tlast_unexpected;dds_test dut(.sclk(sclk),.rst_n(rst_n),.dds1_tvalid(dds1_tvalid),.dds1_sine(dds1_sine),.dds1_cosine(dds1_cosine),.m_axis_phase_tvalid(m_axis_phase_tvalid),.m_axis_phase_tdata(m_axis_phase_tdata),.m_axis_data_tvalid_m(m_axis_data_tvalid_m),.m_axis_data_tdata_m(m_axis_data_tdata_m),.m_axis_phase_tvalid_m(m_axis_phase_tvalid_m),.m_axis_phase_tdata_m(m_axis_phase_tdata_m),.m_axis_data_tuser_m(m_axis_data_tuser_m),.m_dds_ch0_cosine(m_dds_ch0_cosine),.m_dds_ch0_sine(m_dds_ch0_sine),.m_dds_ch1_cosine(m_dds_ch1_cosine),.m_dds_ch1_sine(m_dds_ch1_sine),.m_dds_ch2_cosine(m_dds_ch2_cosine),.m_dds_ch2_sine(m_dds_ch2_sine),.m_dds_ch3_cosine(m_dds_ch3_cosine),.m_dds_ch3_sine(m_dds_ch3_sine),.event_s_config_tlast_missing(event_s_config_tlast_missing),.event_s_config_tlast_unexpected(event_s_config_tlast_unexpected));initial begin#0 sclk = 0; rst_n = 1'b0;#1000 rst_n = 1'b1;
endalways #5 sclk = ~sclk;endmodule

仿真结果：

二.DDS 产生频率可控制变化的正弦余弦信号

dds设置，要求输出的sin 和cos的数据位宽为20.

其他默认。

`timescale 1ns / 1ps
//
// Company:
// Engineer:
//
// Create Date: 2021/01/12 14:45:26
// Design Name:
// Module Name: dds_sin_cos
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//module dds_sin_cos_data(input sclk,input [23:0] fre_ctrl_word);wire fre_ctrl_word_en;wire freq_out_en;wire [47:0] m_axis_data_tdata;wire [19:0] sin_data_out;wire [19:0] cos_data_out;wire [23:0]phase_data_out;wire       phase_data_en;assign  fre_ctrl_word_en=1'b1;assign  sin_data_out=m_axis_data_tdata[43:24];assign  cos_data_out=m_axis_data_tdata[19:0];dds_sin_cos dds_sin_cos_inst (.aclk(sclk),                                  // input wire aclk.s_axis_config_tvalid(fre_ctrl_word_en),  // input wire s_axis_config_tvalid.s_axis_config_tdata(fre_ctrl_word),    // input wire [23 : 0] s_axis_config_tdata.m_axis_data_tvalid(freq_out_en),      // output wire m_axis_data_tvalid.m_axis_data_tdata(m_axis_data_tdata),        // output wire [47 : 0] m_axis_data_tdata.m_axis_phase_tvalid(phase_data_en),    // output wire m_axis_phase_tvalid.m_axis_phase_tdata(phase_data_out)      // output wire [23 : 0] m_axis_phase_tdata
);endmodule

测试程序：

module dds_sin_cos_data_tb();reg sclk;reg [23:0]fre_ctrl_word;initial beginsclk=0;fre_ctrl_word='d0;#100fre_ctrl_word='h28f5;  //1Mhz#4000fre_ctrl_word='h19999; //10Mhz#4000fre_ctrl_word='h51eb; //2Mhz#4000fre_ctrl_word='h68;  //10khz#40000fre_ctrl_word='h28f5;  //1Mhzendalways #5 sclk=~sclk;dds_sin_cos_data  dds_sin_cos_inst(.sclk(sclk),.fre_ctrl_word(fre_ctrl_word));

测试结果;

xilinx DDS ip 核测试使用相关推荐

快速上手Xilinx DDR3 IP核（2）----MIG IP核的官方例程与读写测试模块（Native接口）
写在前面接上一篇文章(配置MIG IP过程): 快速上手Xilinx DDR3 IP核(1)----MIG IP核的介绍及配置(Native接口) DDR3系列文章: 快速上手Xilinx DDR3 ...
xilinx DMA IP核(一) —— loop测试代码注释
本篇笔记中的代码来自:米联科技的教程"第三季第一篇的DMA_LOOP环路测试" 硬件的连接如下图所示: 图:DMA Loop Block Design 橘色的线就是DMA加FIFO ...
基于vivado DDS ip核的DDS信号发生器（可调频调相）
基于Vivado DDS ip核的DDS信号发生器: 在Vivado软件中调出DDS ip核进行设置,很多参数可以参考xilinx官方手册,比较重要的是System Clock系统时钟和Phase W ...
快速上手Xilinx DDR3 IP核（3）----把MIG IP核封装成一个FIFO（上）（Native接口）
写在前面本文将把Xilinx的MIG IP核DDR3的Native接口进行二次封装,将其封装成一个类似FIFO的接口,使其应用起来更加方便简单. DDR3系列文章: 快速上手Xilinx DDR3 ...
快速上手Xilinx DDR3 IP核（4）----把MIG IP核封装成一个FIFO（下）（Native接口）
写在前面本文将把Xilinx的MIG IP核DDR3的Native接口进行二次封装,将其封装成一个类似FIFO的接口,使其应用起来更加方便简单. 本文为下篇,建议与上篇一起阅读,有利于理解: 快速上 ...
PCIe基础知识及Xilinx相关IP核介绍
补发以下以前学习PCIe总结的知识. PCIe学习笔记系列: PCIe基础知识及Xilinx相关IP核介绍概念了解:简单学习PCIe的数据链路与拓扑结构,另外看看有什么相关的IP核. [PG054] ...
（51）Xilinx Divider IP核配置（十一）（第11天）
(51)Xilinx Divider IP核配置(十一)(第11天) 1 文章目录 1)文章目录 2)FPGA初级课程介绍 3)FPGA初级课程架构 4)Xilinx Divider IP核配置(十一 ...
（50）Xilinx Multiplier IP核配置（十一）（第10天）
(50)Xilinx Multiplier IP核配置(十一)(第10天) 1 文章目录 1)文章目录 2)FPGA初级课程介绍 3)FPGA初级课程架构 4)Xilinx Multiplier IP ...
（49）Xilinx Subtracter IP核配置（十）（第10天）
(49)Xilinx Subtracter IP核配置(十)(第10天) 1 文章目录 1)文章目录 2)FPGA初级课程介绍 3)FPGA初级课程架构 4)Xilinx Subtracter IP核 ...

xilinx DDS ip 核测试使用

xilinx DDS ip 核测试使用相关推荐

最新文章

热门文章