top_tb.sv

`timescale 1ns/1ps
`include "uvm_macros.svh"                        //uvm宏import uvm_pkg::*;
`include "my_dut.sv"
`include "my_if.sv"
`include "my_transaction.sv"
`include "my_sequencer.sv"
`include "my_driver.sv"
`include "my_monitor.sv"
`include "my_agent.sv"
`include "my_model.sv"
`include "my_scoreboard.sv"
`include "my_env.sv"
`include "base_test.sv"
`include "my_case0.sv"
`include "my_case1.sv"module top_tb;reg clk;
reg rst_n;
reg[7:0] rxd;
reg rx_dv;
wire[7:0] txd;
wire tx_en;my_if input_if(clk, rst_n);                      //与i_agent的接口的例化
my_if output_if(clk, rst_n);                    //与o_agent的接口的例化dut my_dut(.clk(clk),.rst_n(rst_n),.rxd(input_if.data),.rx_dv(input_if.valid),.txd(output_if.data),.tx_en(output_if.valid));initial beginclk = 0;forever begin#100 clk = ~clk;end
endinitial beginrst_n = 1'b0;#1000;rst_n = 1'b1;
endinitial beginrun_test("my_case0");                             //运行测试用例，或者在questasim的tcl命令行写入"+UVM_TEST_NAME = my_case0"
endinitial beginuvm_config_db#(virtual my_if)::set(null, "uvm_test_top.env.i_agt.drv", "vif", input_if);                //config_db机制，用于参数传递uvm_config_db#(virtual my_if)::set(null, "uvm_test_top.env.i_agt.mon", "vif", input_if);uvm_config_db#(virtual my_if)::set(null, "uvm_test_top.env.o_agt.mon", "vif", output_if);
endendmodule

上述代码中uvm_config_db#(virtual my_if)::set(null, "uvm_test_top.env.i_agt.drv", "vif", input_if);和my_driver中的uvm_config_db#(virtual my_if)::get(this, "", "vif", vif)是一对，表示模块间的参数传递

my_dut.sv

简单的带有复位功能的同步收发

module dut(clk,rst_n, rxd,rx_dv,txd,tx_en);
input           clk;
input           rst_n;
input   [7:0]   rxd;
input           rx_dv;
output  [7:0]   txd;
output          tx_en;reg       [7:0]   txd;
reg             tx_en;always @(posedge clk) beginif(!rst_n) begintxd <= 8'b0;tx_en <= 1'b0;endelse begintxd <= rxd;tx_en <= rx_dv;end
end
endmodule

my_if.sv

接口

`ifndef MY_IF__SV
`define MY_IF__SVinterface my_if(input clk, input rst_n);logic [7:0] data;logic valid;
endinterface
`endif

basic_test.sv、my_case0.sv、my_case1.sv

包含了继承于uvm_test的基本测试平台类base_test，以及继承于base_test的两个测试平台my_case0 和my_case1

my_case0和my_case1使用不同的sequence

`ifndef BASE_TEST__SV                                       //条件编译，表示如果未定义宏BASE_TEST_SV，无分号
`define BASE_TEST__SV                                      //宏定义BASE_TEST_SV，无分号class base_test extends uvm_test;my_env         env;function new(string name = "base_test", uvm_component parent = null);super.new(name,parent);endfunctionextern virtual function void build_phase(uvm_phase phase);   //实例化phase，该类被注册后，build_phase可自动被调用，用于创建UVM树extern virtual function void report_phase(uvm_phase phase);    //打印报告phase，该类被注册后，build_phase可自动被调用`uvm_component_utils(base_test)                              //factory机制，将base_test类注册到UVM内部的一张表中，可自动调用各种phase
endclassfunction void base_test::build_phase(uvm_phase phase);super.build_phase(phase);env  =  my_env::type_id::create("env", this);                 //factory机制的实例化方式，仅限于被注册过的类
endfunctionfunction void base_test::report_phase(uvm_phase phase);uvm_report_server server;int err_num;super.report_phase(phase);server = get_report_server();err_num = server.get_severity_count(UVM_ERROR);if (err_num != 0) begin$display("TEST CASE FAILED");endelse begin$display("TEST CASE PASSED");end
endfunction
`endif

class my_case0 extends base_test;function new(string name = "my_case0", uvm_component parent = null);super.new(name,parent);endfunction extern virtual function void build_phase(uvm_phase phase); `uvm_component_utils(my_case0)
endclassfunction void my_case0::build_phase(uvm_phase phase);super.build_phase(phase);uvm_config_db#(uvm_object_wrapper)::set(this, "env.i_agt.sqr.main_phase", "default_sequence", case0_sequence::type_id::get());                    //表示my_case0测试环境下使用case0_sequence
endfunction`endif

class my_case1 extends base_test;function new(string name = "my_case1", uvm_component parent = null);super.new(name,parent);endfunction extern virtual function void build_phase(uvm_phase phase); `uvm_component_utils(my_case1)
endclassfunction void my_case1::build_phase(uvm_phase phase);super.build_phase(phase);uvm_config_db#(uvm_object_wrapper)::set(this, "env.i_agt.sqr.main_phase", "default_sequence", case1_sequence::type_id::get());
endfunction`endif

my_env.sv

`ifndef MY_ENV__SV
`define MY_ENV__SVclass my_env extends uvm_env;my_agent   i_agt;                                           //dut输入端agentmy_agent   o_agt;                                          //dut输出端agentmy_model   mdl;                                                //dut参考模型my_scoreboard scb;                                         //计分板，或是checkeruvm_tlm_analysis_fifo #(my_transaction) agt_scb_fifo;     //TLM通信FIFOuvm_tlm_analysis_fifo #(my_transaction) agt_mdl_fifo;uvm_tlm_analysis_fifo #(my_transaction) mdl_scb_fifo;function new(string name = "my_env", uvm_component parent);super.new(name, parent);endfunctionvirtual function void build_phase(uvm_phase phase);super.build_phase(phase);i_agt = my_agent::type_id::create("i_agt", this);o_agt = my_agent::type_id::create("o_agt", this);i_agt.is_active = UVM_ACTIVE;                                //UVM_ACTIVE表示该agent包含driver和sequencero_agt.is_active = UVM_PASSIVE;                           //UVM_PASSIVE表示该agent只有一个monitor，不包含drivermdl = my_model::type_id::create("mdl", this);scb = my_scoreboard::type_id::create("scb", this);agt_scb_fifo = new("agt_scb_fifo", this);                  //TLM fifo不属于uvm_component因此只能new例化agt_mdl_fifo = new("agt_mdl_fifo", this);mdl_scb_fifo = new("mdl_scb_fifo", this);endfunctionextern virtual function void connect_phase(uvm_phase phase);`uvm_component_utils(my_env)
endclassfunction void my_env::connect_phase(uvm_phase phase);super.connect_phase(phase);i_agt.ap.connect(agt_mdl_fifo.analysis_export);                         //i_agt到mdl的TLM FIFO通信mdl.port.connect(agt_mdl_fifo.blocking_get_export);mdl.ap.connect(mdl_scb_fifo.analysis_export);                          //mdl到scb的TLM FIFO通信scb.exp_port.connect(mdl_scb_fifo.blocking_get_export);o_agt.ap.connect(agt_scb_fifo.analysis_export);                          //o_agt到scb的TLM FIFO通信scb.act_port.connect(agt_scb_fifo.blocking_get_export);
endfunction`endif

my_agent.sv

注意my_agent中并未定义虚接口

`ifndef MY_AGENT__SV
`define MY_AGENT__SVclass my_agent extends uvm_agent ;my_sequencer  sqr;my_driver     drv;my_monitor    mon;uvm_analysis_port #(my_transaction)  ap;                                           //端口function new(string name, uvm_component parent);super.new(name, parent);endfunction extern virtual function void build_phase(uvm_phase phase);extern virtual function void connect_phase(uvm_phase phase);`uvm_component_utils(my_agent)
endclass function void my_agent::build_phase(uvm_phase phase);super.build_phase(phase);if (is_active == UVM_ACTIVE) beginsqr = my_sequencer::type_id::create("sqr", this);drv = my_driver::type_id::create("drv", this);endmon = my_monitor::type_id::create("mon", this);
endfunction function void my_agent::connect_phase(uvm_phase phase);super.connect_phase(phase);if (is_active == UVM_ACTIVE) begindrv.seq_item_port.connect(sqr.seq_item_export);                       //将端口成员变量uvm_driver::seq_item_port与端口成员变量uvm_sequencer::seq_item_export连接，用于sequence的传输endap = mon.ap;                                                              //agent发送端口与monitor的发送端口是同一个
endfunction`endif

my_sequencer.sv

用于打包、发送trans。

sequencer像一把枪，sequence就是弹夹，里面的子弹就是transaction。

而sequencer将transaction发射给driver

`ifndef MY_SEQUENCER__SV
`define MY_SEQUENCER__SVclass my_sequencer extends uvm_sequencer #(my_transaction);function new(string name, uvm_component parent);super.new(name, parent);endfunction `uvm_component_utils(my_sequencer)
endclass`endif

my_sequence.sv

两种sequence，case0_sequence 和case1_sequence 分别对应着两种测试平台my_case0和my_case1

class case0_sequence extends uvm_sequence #(my_transaction);my_transaction m_trans;function  new(string name= "case0_sequence");super.new(name);endfunction virtual task body();                                                  //sequence启动后会自动调用body()if(starting_phase != null) starting_phase.raise_objection(this);repeat (10) begin`uvm_do(m_trans)                                             //实例化m_trans并随机化，并传给sequencerend#100;if(starting_phase != null) starting_phase.drop_objection(this);endtask`uvm_object_utils(case0_sequence)                                       //factory注册，uvm_sequence继承自uvm_object
endclass

class case1_sequence extends uvm_sequence #(my_transaction);my_transaction m_trans;function  new(string name= "case1_sequence");super.new(name);endfunction virtual task body();if(starting_phase != null) starting_phase.raise_objection(this);                             //提起和撤销objection,starting_phase来自于uvm_sequence类repeat (10) begin`uvm_do_with(m_trans, { m_trans.pload.size() == 60;})                //加了硬约束的`uvm_doend#100;if(starting_phase != null) starting_phase.drop_objection(this);endtask`uvm_object_utils(case1_sequence)
endclass

my_transaction.sv

`ifndef MY_TRANSACTION__SV
`define MY_TRANSACTION__SVclass my_transaction extends uvm_sequence_item;                          //派生自uvm_sequence_item而不是uvm_transactionrand bit[47:0] dmac;rand bit[47:0] smac;rand bit[15:0] ether_type;rand byte      pload[];rand bit[31:0] crc;constraint pload_cons{pload.size >= 46;pload.size <= 1500;}function bit[31:0] calc_crc();return 32'h0;endfunctionfunction void post_randomize();crc = calc_crc;endfunction`uvm_object_utils_begin(my_transaction)                            //factory注册，注册后可直接调用copy,compare,print等函数，无需再手动定义`uvm_field_int(dmac, UVM_ALL_ON)`uvm_field_int(smac, UVM_ALL_ON)`uvm_field_int(ether_type, UVM_ALL_ON)`uvm_field_array_int(pload, UVM_ALL_ON)`uvm_field_int(crc, UVM_ALL_ON)`uvm_object_utils_endfunction new(string name = "my_transaction");super.new();endfunctionendclass
`endif

my_driver.sv

通过uvm_driver::seq_item_port.get_next_item(req);获取trans，并驱动dut，驱动完成后告知sequencer，以进行下一次uvm_sequencer::uvm_do()

`ifndef MY_DRIVER__SV
`define MY_DRIVER__SV
class my_driver extends uvm_driver#(my_transaction);virtual my_if vif;`uvm_component_utils(my_driver)function new(string name = "my_driver", uvm_component parent = null);super.new(name, parent);endfunctionvirtual function void build_phase(uvm_phase phase);super.build_phase(phase);if(!uvm_config_db#(virtual my_if)::get(this, "", "vif", vif))`uvm_fatal("my_driver", "virtual interface must be set for vif!!!")endfunctionextern task main_phase(uvm_phase phase);extern task drive_one_pkt(my_transaction tr);
endclasstask my_driver::main_phase(uvm_phase phase);vif.data <= 8'b0;vif.valid <= 1'b0;while(!vif.rst_n)@(posedge vif.clk);while(1) beginseq_item_port.get_next_item(req);                       //获取trans，这好像有点问题drive_one_pkt(req);seq_item_port.item_done();                           //驱动完成，通知sequencer可使uvm_do()结束end
endtasktask my_driver::drive_one_pkt(my_transaction tr);byte unsigned     data_q[];int  data_size;data_size = tr.pack_bytes(data_q) / 8; `uvm_info("my_driver", "begin to drive one pkt", UVM_LOW);repeat(3) @(posedge vif.clk);for ( int i = 0; i < data_size; i++ ) begin@(posedge vif.clk);vif.valid <= 1'b1;vif.data <= data_q[i]; end@(posedge vif.clk);vif.valid <= 1'b0;`uvm_info("my_driver", "end drive one pkt", UVM_LOW);
endtask`endif

my_monitor.sv

`ifndef MY_MONITOR__SV
`define MY_MONITOR__SV
class my_monitor extends uvm_monitor;virtual my_if vif;uvm_analysis_port #(my_transaction)  ap;`uvm_component_utils(my_monitor)function new(string name = "my_monitor", uvm_component parent = null);super.new(name, parent);endfunctionvirtual function void build_phase(uvm_phase phase);super.build_phase(phase);if(!uvm_config_db#(virtual my_if)::get(this, "", "vif", vif))`uvm_fatal("my_monitor", "virtual interface must be set for vif!!!")ap = new("ap", this);endfunctionextern task main_phase(uvm_phase phase);extern task collect_one_pkt(my_transaction tr);
endclasstask my_monitor::main_phase(uvm_phase phase);my_transaction tr;while(1) begintr = new("tr");collect_one_pkt(tr);ap.write(tr);end
endtasktask my_monitor::collect_one_pkt(my_transaction tr);byte unsigned data_q[$];byte unsigned data_array[];logic [7:0] data;logic valid = 0;int data_size;while(1) begin@(posedge vif.clk);if(vif.valid) break;end`uvm_info("my_monitor", "begin to collect one pkt", UVM_LOW);while(vif.valid) begindata_q.push_back(vif.data);@(posedge vif.clk);enddata_size  = data_q.size();   data_array = new[data_size];for ( int i = 0; i < data_size; i++ ) begindata_array[i] = data_q[i]; endtr.pload = new[data_size - 18]; //da sa, e_type, crcdata_size = tr.unpack_bytes(data_array) / 8; `uvm_info("my_monitor", "end collect one pkt", UVM_LOW);
endtask`endif

my_model.sv

`ifndef MY_MODEL__SV
`define MY_MODEL__SVclass my_model extends uvm_component;uvm_blocking_get_port #(my_transaction)  port;uvm_analysis_port #(my_transaction)  ap;extern function new(string name, uvm_component parent);extern function void build_phase(uvm_phase phase);extern virtual  task main_phase(uvm_phase phase);`uvm_component_utils(my_model)
endclass function my_model::new(string name, uvm_component parent);super.new(name, parent);
endfunction function void my_model::build_phase(uvm_phase phase);super.build_phase(phase);port = new("port", this);ap = new("ap", this);
endfunctiontask my_model::main_phase(uvm_phase phase);my_transaction tr;my_transaction new_tr;super.main_phase(phase);while(1) beginport.get(tr);new_tr = new("new_tr");new_tr.copy(tr);`uvm_info("my_model", "get one transaction, copy and print it:", UVM_LOW)new_tr.print();ap.write(new_tr);end
endtask
`endif

my_scoreboard.sv

`ifndef MY_SCOREBOARD__SV
`define MY_SCOREBOARD__SV
class my_scoreboard extends uvm_scoreboard;my_transaction  expect_queue[$];uvm_blocking_get_port #(my_transaction)  exp_port;uvm_blocking_get_port #(my_transaction)  act_port;`uvm_component_utils(my_scoreboard)extern function new(string name, uvm_component parent = null);extern virtual function void build_phase(uvm_phase phase);extern virtual task main_phase(uvm_phase phase);
endclass function my_scoreboard::new(string name, uvm_component parent = null);super.new(name, parent);
endfunction function void my_scoreboard::build_phase(uvm_phase phase);super.build_phase(phase);exp_port = new("exp_port", this);act_port = new("act_port", this);
endfunction task my_scoreboard::main_phase(uvm_phase phase);my_transaction  get_expect,  get_actual, tmp_tran;bit result;super.main_phase(phase);fork while (1) beginexp_port.get(get_expect);expect_queue.push_back(get_expect);endwhile (1) beginact_port.get(get_actual);if(expect_queue.size() > 0) begintmp_tran = expect_queue.pop_front();result = get_actual.compare(tmp_tran);if(result) begin `uvm_info("my_scoreboard", "Compare SUCCESSFULLY", UVM_LOW);endelse begin`uvm_error("my_scoreboard", "Compare FAILED");$display("the expect pkt is");tmp_tran.print();$display("the actual pkt is");get_actual.print();endendelse begin`uvm_error("my_scoreboard", "Received from DUT, while Expect Queue is empty");$display("the unexpected pkt is");get_actual.print();end endjoin
endtask
`endif

1. 使用Questasim搭建UVM验证环境

可参考

UVM系统验证基础知识0(Questasim搭建第一个UVM环境)

其中sim.do文件可加入一行view transcript 查看questasim命令行

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目录