80386 Programmer's Manual: Chapter 9 Exceptions and Interrupts(Personal Translation)

Chapter 9 Exceptions and Interrupts

1.interrupts are used to handle asynchronous events(异步事件) external to the processor(处理器外部的), but exceptions handle conditions detected by the processor itself in the course of executing instructions(处理执行指令过程中，处理器自己发现的状况).

interrupts分为Maskable interrupts(可屏蔽中断，通过INTR引脚发出信号)和Nonmaskable interrupts(不可屏蔽中断，通过NMI引脚发出信号)

exceptions有两种来源，processor detected(可细分为faults, traps, and aborts)与programmed(instructions INTO, INT 3, INT n, and BOUND可引发，也可叫做软件中断)

2.Exceptions are classified as faults, traps, or aborts depending on the way they are reported(报错方式) and whether restart of the instruction(重启导致异常的指令) that caused the exception is supported.

faults是在引起异常的指令之前报错。可在该指令前或者执行期间报错。允许重启指令
traps是检测到异常立马在指令边界报错
aborts不给报错精确位置，也不允许报错程序重启，是非常严重的错误，如 hardware errors and inconsistent or illegal values in system tables

9.1 Identifying Interrupts

每一个中断和异常都有一个唯一标识的编号。The NMI and the exceptions(只有INTR中断不在这范围？) recognized by the processor are assigned predetermined(预先确定的) identifiers in the range 0 through 31

Table 9-1. Interrupt and Exception ID AssignmentsIdentifier   Description0            Divide error 除法错误1            Debug exceptions 调试异常2            Nonmaskable interrupt 不可屏蔽中断3            Breakpoint (one-byte INT 3 instruction) 断点（一个字节的INT3指令）4            Overflow (INTO instruction) 溢出（INTO指令）5            Bounds check (BOUND instruction)边界检验（BOUND指令）6            Invalid opcode 非法操作符7            Coprocessor not available 协处理器不可用8            Double fault 双重错误9            (reserved) （保留）10           Invalid TSS 无效的TSS11           Segment not present 段不存在12           Stack exception 栈异常13           General protection 一般性保护14           Page fault 页错误15           (reserved) （保留）16           Coprecessor error 协处理器错误17-31        (reserved) （保留）32-255       Available for external interrupts via INTR pin 对通过INTR引脚触发的外部中断有效

谢谢马如风

9.2 Enabling and Disabling(启用和禁用) Interrupts

1.The processor services interrupts and exceptions only between the end of one instruction and the beginning of the next(一条结束后下一条开始前才处理，即两条指令之间)

2.While an NMI handler is executing, the processor ignores further interrupt signals at the NMI pin until the next IRET instruction is executed.

3.The IF (interrupt-enable flag) IF=0禁止INTR中断，IF=1运行INTR中断。CLI (Clear Interrupt-Enable Flag) and STI (Set Interrupt-Enable Flag) explicitly alter(显示更改) IF

4.The RF bit in EFLAGS controls the recognition of debug faults 每个给定指令最多引起一次调试错误，哪怕它多次重启

5.在MOV to SS和POP to SS指令之后，在改变SS的指令之后，在指令边界处抑制NMI, INTR, debug exceptions, and single-step traps

9.3 Priority(优先) Among Simultaneous(同时) Interrupts and Exceptions

Priority   Class of Interrupt or ExceptionHIGHEST    Faults except debug faults
Trap instructions INTO, INT n, INT 3
Debug traps for this instruction
Debug faults for next instruction
NMI interrupt
LOWEST     INTR interrupt

9.4 Interrupt Descriptor Table( 重点！)

1.The interrupt descriptor table (IDT) associates(联系) each interrupt or exception identifier(id) with a descriptor for the instructions that service the associated event(服务于相关事件的指令的描述符)

the IDT is an array of 8-byte descriptors. 为了在IDT中形成索引，处理器将interrupt or exception identifier乘以8。因为只有256个identifiers.
descriptors or identifiers??? descriptros is for instruction, identifiers is id
x8?

2.the processor locates(定位) the IDT by means(值) of the IDT register (IDTR). The instructions LIDT and SIDT operate on the IDTR. LIDT (Load IDT register) 用 memory operand(内存操作数)中的the linear base address and limit values 去加载 the IDT register. SIDT (Store IDT register) copies the base and limit value stored in IDTR to a memory location. Both instructions have one explicit operand: the address in memory of a 6-byte area

9.5 IDT Descriptors

1.IDT主要有三种描述符：

Task gates 任务门
Interrupt gates 中断门
Trap gates 陷阱门

格式如下

9.6 Interrupt Tasks and Interrupt Procedures(过程)( 重点! )

9.6.1 Interrupt Procedures

1.the processor uses the interrupt or exception identifier(id) to index a descriptor in the IDT. If the processor indexes to an interrupt gate or trap gate(见9.5)，它以类似于CALL一个调用门的方式调用处理程序；If the processor finds a task gate，它类似于CALL一个任务门的方式切换任务

中断门或陷阱门间接指向将在当前执行任务的上下文(context)中执行的过程？？？中断过程如下图：
很清晰的可以看到The selector of the gate指向GDT或LDT中的可执行段描述符。The offset field of the gate指向中断或异常处理程序的入口地址
2.中断或异常处理过程的控件传输使用stack存储返回原始过程所需的信息。中断在指向中断指令的指针之前将EFLAGS寄存器推入堆栈。如图：

3.从中断过程中返回。The IRET instruction is used to exit from an interrupt procedure

4.Interrupts that vector(中断该向量) through either interrupt gates or trap gates cause TF (the trap flag) to be reset after the current value of TF is saved on the stack as part of EFLAGS(存储TF值到栈后重置). 这样可以防止单步调试的时候影响中断响应

The difference between an interrupt gate and a trap gate is in the effect on IF (the interrupt-enable flag)中断门会重置IF防止其他中断妨碍current interrupt handler. 陷阱门不会重置IF

5.the privilege rule：the CPU does not permit an interrupt to transfer control(转移控制) to a procedure in a segment of lesser privilege (numerically greater privilege level(数字上越大，特权级别越低)) than the current privilege level.(比当前特权级别更低的特权段中的程序)。否则会引发a general protection exception

6.中断的发生一般是不可预测的。为了保证 the privilege rule不被侵犯，可以Place the handler in a conforming(符合要求) segment或者Place the handler procedure in a privilege level zero segment.

9.6.2 Interrupt Tasks

1.A task gate in the IDT points indirectly to a task，The selector of the gate points to a TSS descriptor in the GDT. 如下图

2.当 an interrupt or exception vectors(向量) 指向IDT中的a task gate时，会导致 a task switch(任务切换)。Handling an interrupt with a separate task(单独的任务) offers two advantages:

The entire context is saved automatically.
中断处理程序可以提供a separate address space与其他任务分离(via its LDT or page directory)

The interrupt task returns to the interrupted task by executing an IRET instruction.

3.there are actually two schedulers(调度程序):the software scheduler (part of the operating system) and the hardware scheduler (part of the processor’s interrupt mechanism). 软件调度的设计应该考虑无论何时启用中断，硬件调度器都可以分派中断任务。

9.8 Exception Conditions(异常状况？异常条件)

1.Each description classifies the exception as a fault, trap, or abort. 这种分类提供系统程序在异常发生时重启程序所需要的信息。

Faults：The CS and EIP values point to the instruction causing the fault.
Traps ：The CS and EIP values 动态指向引发trap的指令。如果程序流程发生改变，那CS与EIP就会指向那个改变(如指向JMP的跳转，而不是跳转之后的指令)
Aborts are used to report severe errors

2.会产生error code 的异常是：

后面略。。。

参考
80386 Programmer’s Manual
马如风对手册的翻译