ubuntu arm qt_Cyclone V SOC(ARM+FPGA)开发文档_之开发流程详解
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目录
Altera Cyclone V soc开发文档 之软硬件开发 1
Cyclone V开发流程介绍 5
专业术语 5
Cyclone V软件开发介绍 6
U-BOOT编译 6
Linux内核编译 7
安装QT库 7
配置内核 7
编译内核 8
驱动模块编译 9
Preloader 的生成 9
DTB文件生成 9
生成dtb所需文件 9
Dts文件生成命令 9
Dtb文件生成命令 10
DTS转换为DTB文件命令 10
修改FLASH分区 10
Jfss2文件系统镜像生成 12
启动代码与内核烧写 13
Linux Demo测试 15
文件系统裁剪 15
获取BusyBox源码 16
配置BusyBox 16
编译和安装 busybox 17
制作根文件系统 17
U-BOOT启动流程分析 19
uboot源码顶层目录 19
与平台相关的文件 20
与SOC目标板相关的硬件配置文件 20
SOC目标板参数配置文件 21
u-boot启动流程介绍 21
u-boot、内核、FPGA加载方式 23
HPS启动与BOOT ROM执行流程 24
HPS启动流程 24
Boot ROM介绍 24
BOOT ROM执行流程 25
DTB文件介绍 26
ARM DS-5软件介绍 27
编译器选择 27
PCI驱动开发及DEMO测试 27
官方参考链接 27
PCIe Root Port 28
所需安装包 28
内核增加PCIe驱动(打补丁) 29
内核配置MSI驱动 33
禁止MSI 33
使能MSI 33
编译Host system 和End point device 驱动 33
编译ThroughputLinux应用 33
Qsys Design and Generation 34
官方HW例程直接生成dts出错 35
PCIe DEMO测试流程 36
Root Port<->End Point 36
Discover End Point and Check Linux Kernel Modules 36
测试数据收发带宽 37
数据流向 37
PCIe开发流程 37
Build PCIe Root Port 37
Converting .sof to .rbf 38
Build Cyclone V GT PCIe End Point 39
软件开发时遇到的问题 39
FPGA文件问题 39
DTB文件问题 40
文件系统生成时指定的页与块大小与芯片不符 40
官方PCIe HW例程Quartus II编译出错 41
官方HW例程直接生成dts出错 41
U-BOOT启动参数缺少报错 43
Linux内核无法启动 43
Linux设备驱动与应用开发推荐书籍 44
Linux设备驱动开发 44
Linux应用程序开发 44
PCIe复位信号 45
SoC FPGA配置与启动 46
如何获取Linux各个版本内核代码 47
Q-II编译错误 47
HW文件类型说明 49
Programming FPGA With Quartus Programmer 51
创建和编译Preloader 55
Cyclone V Hard Processor System Technical Reference Manual 55
PCIE参考资料 55
signaltap使用指南 65
Preloader—>kernel执行过程 65
Cyclone V HPS Memory Map 66
驱动模块加载失败 66
查询PCIE设备信息 66
修改外部输入时钟频率 68
System Console验证PCIE硬件功能 68
MPU主频提高至800MHz 69
PCIe硬件改动 70
DSP复位信号 71
HPS GPIO信号 73
can't assign mem 74
DSP6654 PCIE配置 75
PCIE启动 75
决定PCIE RP或EP模式 78
DSP大端或小端模式 78
KeyStone Architecture DSP Bootloader 79
PCI Express (PCIe) Bootloader Operation 79
3.6.1 RBL Initialization Process 79
3.6.2 RBL Loading Process 79
3.6.3 RBL Hand-Over Process 80
DSP启动过程 80
Boot Processes 80
Reset Types and Device Initialization 80
Reset Types 81
Bootloader Features 81
PCIE调试总结 82
HPS GPIO配置 83
mSGDMA 协助PCIe完成数据收发 85
内核除零 87
Creating a DSP Boot Image for Host Boot 91
概述 91
步骤 92
工具 93
RC只要可以访问EP,通过写EP的MSI_IRQ寄存器就可以实现RC可不可以给EP端发送中断 95
BAR inbound地址 95
Linux下PCIE设备驱动 96
core1编译提示VFP register出错 96
Core1编译链接出错 96
device or resource busy 100
QSPI NOR FLASH擦除、写入操作 102
mtd_debug命令 104
mtd-utils命令简介 104
cat /proc/mtd 104
flash_erase 105
flash_eraseall 105
flashcp 105
mtd_debug 107
例一:如何测试nor flash 驱动 107
例二:如何测试nand flash 驱动 108
Cyclone V开发流程介绍
专业术语
术语
扩展
描述
Avalon-MM
Avalon Memory Mapped Interface
an address-based read/write interface typical of master–slave connections.
Avalon-ST
Avalon Streaming Interface
an interface that supports the unidirectional flow of data, including multiplexed streams, packets, and DSP data.
AMBA
Advanced Microcontroller Bus Architecture
AXI
Advanced eXtensible Interface
GIC
HPS Global Interrupt ControllerS
msi
Message Signal Interrupts
mSGDMA
Scatter-Gather DMA
HPS
Hard Processor System
RP-OCM
root port on-chip memory
Cyclone V软件开发介绍
https://rocketboards.org/foswiki/view/Documentation/AVCVGSRD150
根据GHRD的开发流程图可以看出,最终需要的执行文件有:
- Preloader,为u-boot做加载启动的文件
- U-boot,加载内核及FPGA配置文件
- Linux内核
- DTB文件
- Linux根文件系统
- FPGA配置文件
U-BOOT编译
1、进入工作路径下的u-boot源代码文件夹下
$cd /home/arvin/workdir/soc-fpga/u-boot-socfpga
2、将u-boot的源代码拷贝到该目录下,使用如下命令解压:
$tar xvzf u-boot-altera-2012.10.tgz
$make mrproper
$make socfpga_cyclone5_config
$make
编译完成后可发现当前目录已生成u-boot.bin,u-boot.img等镜像文件,其中u-boot.img需要烧到QSPI flash 里(可使用make menuconfig 命令对u-boot进行配置)。
Linux内核编译
内核编译之前需要对内核进行配置(裁剪),由于Linux源码支持很多设备驱动及很多厂商的平台,整个源码编译出来zImage非常大,故需要根据实际需求应用及目标板具有的硬件外设对内核进行配置,通常使用menuconfig或者xconfig来配置内核。
安装QT库
1、在make menuconfig命令前需要安装ncurse 库的支持, ubuntu中默认没有安装,需要安装一下。
$sudo apt-get install libncurses5-dev
2、make xconfig基于X11, 使用qt库, 在Ubuntu中先安装qt库:
$sudo apt-get install libqt3-headers libqt3-mt-dev
$sudo apt-get install build-essential kernel-package libncurses5-dev fakeroot g++
配置内核
进入工作路径下的内核源代码文件夹下
$cd /home/arvin/workdir/yocto/borax_310_LTSI/linux-socfpga
$make ARCH=arm socfpga_defconfig
$make ARCH=arm xconfig或menuconfig
make xconfig显示界面如下:
make menuconfig显示界面如下:
Ubuntu12.04在编译配置内核时提示:
arvin@socfpga:~/workdir/socfpga/kernel/linux-socfpga$ make xconfig
CHECK qt
*
* Could not find Qt via pkg-config.
* Please install either Qt 4.8 or 5.x. and make sure it's in PKG_CONFIG_PATH
*
make[1]: *** No rule to make target `scripts/kconfig/.tmp_qtcheck', needed by `scripts/kconfig/qconf.o'. Stop.
make: *** [xconfig] Error 2
解决方法:sudo apt-get install qt4-dev-tools
编译内核
注:如果在安装交叉编译器时未指定环境变量,则配置和编译内核时需指定平台及交叉编译器,命令如下所示:
$make ARCH=arm CROSS_COMPILE=/opt/linaro/gcc-linaro-arm-linux-gnueabihf-4.7-2012.11-20121123_linux/bin/arm-linux-gnueabihf- zImage
编译完后会在内核的路径下的arch/arm/boot路径下会有uImage这个内核镜像文件,如下图所示:
把这个文件拷贝到PC机与虚拟机的共享目录下,为我们的开发板启动做准备。
驱动模块编译
内核编译完后,还需要编译模块(在内核配置时未编译进内核的.ko文件),命令如下:
$ sudo make ARCH=arm modules
$ sudo make ARCH=arm modules_install install
Preloader 的生成
详细步骤请参考《Borax_Linux_design_V2.1(CN_com_0).pdf》说明
DTB文件生成
生成dtb所需文件
- soc_system.sopcinfo
- soc_system_board_info.xml
- hps_common_board_info.xml
这三个文件可从https://releases.rocketboards.org/release/2015.04/gsrd/bin下载,或者从Quartus II安装目录获取
(C:altera15.0embeddedexampleshardwarecv_soc_devkit_ghrd)
Dts文件生成命令
$ sopc2dts --input soc_system.sopcinfo
--output socfpga.dts --type dts
--board soc_system_board_info.xml
--board hps_common_board_info.xml
--bridge-removal all
--clocks
cd D:/Cyclonev/cv_soc_devkit_pcie/cv_soc_devkit_pcie
cd D:/Cyclonev/cv_soc_rp_full_design/cv_soc_rp_full_design
sopc2dts --input pcie_rp_ed_5csxfc6.sopcinfo --output socfpga15.0.dts -b pcie_rp_ed_5csxfc6_board_info.xml --board hps_common_board_info.xml --clocks --bridge-removal all
Dtb文件生成命令
sopc2dts --input pcie_rp_ed_5csxfc6.sopcinfo
--output socfpga.dts
--board pcie_rp_ed_5csxfc6_board_info.xml
--board hps_common_board_info.xml
--board hps_clock_info.xml
$ sopc2dts --input soc_system.sopcinfo
--output socfpga.dtb --type dtb
--board soc_system_board_info.xml
--board hps_common_board_info.xml
--bridge-removal all
--clocks
DTS转换为DTB文件命令
dtc -I dts -O dtb -o socfpga.dtb socfpga.dts
修改FLASH分区
由于我们的板子使用的是QSPI flash,所有的介质文件都是存放在QSPI FLASH里,所以需要对FLASH进行分区,修改方式有如下两种:
1、修改soc_system_board_info.xml文件
原始文件内容如下(默认为将FLASH分成2个区,第一个区为Flash 0 Raw Data,存放prl、u-boot、zImage、dtb文件等,起始地址为0x0,大小为0x800000,第二个区为Flash 1 jffs2 Filesystem,存放rootfs文件系统,起始地址为0x800000,大小为0x7800000):
<DTAppend name="partition@0" type="node" parentlabel="flash0"
newlabel="part0"/>
<DTAppend name="label" type="string" parentlabel="part0" val="Flash 0
Raw Data"/>
<DTAppend name="reg" parentlabel="part0">
<val type="hex">0x0</val>
<val type="hex">0x800000</val>
</DTAppend>
<DTAppend name="partition@800000" type="node" parentlabel="flash0"
newlabel="part1"/>
<DTAppend name="label" type="string" parentlabel="part1" val="Flash 1
jffs2 Filesystem"/>
<DTAppend name="reg" parentlabel="part1">
<val type="hex">0x800000</val>
<val type="hex">0x7800000</val>
</DTAppend>
更改如下(将FLASH分成3个区,第一个区为Flash 0 Raw Data,存放prl、u-boot、dtb、内核文件,起始地址为0x0,大小为0x800000,第二个区为Flash 1 jffs2 Filesystem,存放rootfs文件系统,起始地址为0x800000,大小为0x1000000,第三个区为FPGA IMAGE,存放
FPGA配置文件,起始地址为0x1800000,大小为0x800000):
<DTAppend name="partition@0" type="node" parentlabel="flash0"
newlabel="part0"/>
<DTAppend name="label" type="string" parentlabel="part0"
val="Flash 0 Raw Data"/>
<DTAppend name="reg" parentlabel="part0">
<val type="hex">0x0</val>
<val type="hex">0x800000</val>
</DTAppend>
<DTAppend name="partition@800000" type="node"
parentlabel="flash0" newlabel="part1"/>
<DTAppend name="label" type="string" parentlabel="part1"
val="Flash 1 jffs2 Filesystem"/>
<DTAppend name="reg" parentlabel="part1">
<val type="hex">0x800000</val>
<val type="hex">0x1000000</val>
</DTAppend>
<DTAppend name="partition@1800000" type="node"
parentlabel="flash0" newlabel="part2"/>
<DTAppend name="label" type="string"parentlabel="part2"
val="FPGA IMAGE"/>
<DTAppend name="reg" parentlabel="part2">
<val type="hex">0x1800000</val>
<val type="hex">0x800000</val>
</DTAppend>
2、修改dts文件
Label:表示分区名称
Reg:表示FLASH分区的起始地址及长度
partition@qspi-boot {
/* 8MB for raw data. */
label = "Flash 0 Raw Data";
reg = <0x0 0x100000>;
};
partition@qspi-rootfs {
/* Flash 0 jffs2 Filesystem. 16MB */
label = "Flash 0 jffs2 Filesystem";
reg = <0x100000 0xF00000>;
};
partition@qspi-rbf {
label = "FPGA Image";
reg = <0x1000000 0x1000000>;
};
打开Embedded Command Shell 终端,输入如下命令:
$ dtc -I dts -O dtb -o socfpga.dtb socfpga.dts
$ cd ~/cv_soc_devkit_ghrd
$ sopc2dts --input soc_system.sopcinfo
--output socfpga.dtb
--type dtb
--board soc_system_board_info.xml
--board hps_common_board_info.xml
--bridge-removal all
--clocks
生成socfpga.dtb 文件,内核启动之前需要加载该文件,dtb文件配置不对会导致内核无法启动,具体请查看内核启动信息:
$$ Flattened Device Tree blob at 00000100
Booting using the fdt blob at 0x00000100
Loading Device Tree to 03ff7000, end 03fffb0f ... OK
Starting kernel ...
内核起来后在超级终端可查看FLASH的分区信息:
Creating 3 MTD partitions on "spi2.0":
0x000000000000-0x000000800000 : "Flash 0 Raw Data"
0x000000800000-0x000001800000 : "Flash 1 jffs2 Filesystem"
0x000001800000-0x000002000000 : "FPGA IMAGE"
Jfss2文件系统镜像生成
将俊龙提供的mini文件系统解压到工作目录,使用如下命令生成烧录到QSPI FLASH的镜像文件(也可用busybox制作的文件系统,但过程比较复杂,前期调试用骏龙提供即可):
$cd /home/arvin/workdir/soc-fpga
$sudo mkfs.jffs2 -d rootfs/ --pagesize=0x100 --eraseblock=0x10000 -n -l –
output=./rfs_p100_e10000.jffs2
-s:表示QSPI FLASH的页大小(256Byte )
-e:表示QSPI FLASH的擦除的块大小(64K)
QPSI FLASH手册有说明,见“N25Q25_datasheet”
如果页大小及块大小指定不对内核起来会报如下错误:
jffs2: Node at 0x000006f4 with length 0x0000f906 would run over the end of the erase block
jffs2: Perhaps the file system was created with the wrong erase size?
jffs2: jffs2_scan_eraseblock(): Magic bitmask 0x1985 not found at 0x000006f8: 0xf906 instead
jffs2: jffs2_scan_eraseblock(): Magic bitmask 0x1985 not found at 0x000006fc: 0x23f4 instead
jffs2: jffs2_scan_eraseblock(): Magic bitmask 0x1985 not found at 0x00000700: 0x0011 instead
jffs2: jffs2_scan_eraseblock(): Magic bitmask 0x1985 not found at 0x00000704: 0x0001 instead
jffs2: jffs2_scan_eraseblock(): Magic bitmask 0x1985 not found at 0x00000708: 0x81ed instead
jffs2: jffs2_scan_eraseblock(): Magic bitmask 0x1985 not found at 0x0000070c: 0x03e8 instead
jffs2: jffs2_scan_eraseblock(): Magic bitmask 0x1985 not found at 0x00000710: 0x7f48 instead
jffs2: jffs2_scan_eraseblock(): Magic bitmask 0x1985 not found at 0x00000714: 0xea61 instead
jffs2: jffs2_scan_eraseblock(): Magic bitmask 0x1985 not found at 0x00000718: 0xea61 instead
jffs2: jffs2_scan_eraseblock(): Magic bitmask 0x1985 not found at 0x0000071c: 0xea61 instead
jffs2: Further such events for this erase block will not be printed
jffs2: jffs2_scan_eraseblock(): Magic bitmask 0x1985 not found at 0x00001000: 0x8fe8 instead
jffs2: jffs2_scan_eraseblock(): Magic bitmask 0x1985 not found at 0x00001004: 0xbdf5 instead
jffs2: jffs2_scan_eraseblock(): Magic bitmask 0x1985 not found at 0x00001008: 0x147e instead
启动代码与内核烧写
通过上面的介绍,整个板子的所需的介质文件已编译生成完成,清单如下:
- preloader-mkpimage.bin
- u-boot.img
- socfpga.dtb
- zImage
- rootfs_64k.jffs2
- fpga.rbf
其中我们QSPI FLASH分成了3个大区,每个文件在FALSH中的存放位置如下图所示:
第一次烧写打开Embedded Command Shell 终端,通过JTAG烧录到QSPI FLASH,命令如下:
- 查看输出Info 确认硬件连接正常:
quartus_hps –c 1 –o S
- 烧录preloader
quartus_hps –c 1 –o P ./socfpga/preloader-mkpimage.bin
- 烧录dtb文件
quartus_hps -c 1 -o P -a 0x50000 ./socfpga/socfpga.dtb
- 烧录u-boot
quartus_hps -c 1 -o PV -a 0x60000 ./socfpga/u-boot.img.bin
- 烧录FPGA配置文件
quartus_hps -c 1 -o PV -a 0x1800000 ./socfpga/fpga.rbf
- 烧录文件系统
quartus_hps -c 1 -o P -a 0x800000 rootfs_jffs2
- 烧录内核文件
quartus_hps -c 1 -o PV -a 0xa0000 zImage.bin
注:为加快烧录时间,可取消V
-p:烧录选项
-v:验证烧录数据是否正确
所有介质文件烧录完成后,板子断电并打开超级终端连上串口,再上电,u-boot起来再读取FALSH文件到SARAM前有5秒的中断时间,按任意键停止启动,如下图所示:
设置默认启动参数,命令如下:
setenv qspifpga sf probe ${qspiloadcs}; sf read ${fpgadata} ${qspifpgaaddr} ${fpgadatasize}; fpga load ${qspiloadcs} ${fpgadata} ${filesize};
setenv bootcmd run qspifpga; run bridge_enable_handoff; run qspiload; run qspiboot
保存启动参数
saveenv
输入boot重新启动。
Linux Demo测试
内核跟文件系统起来后,为验证整个Linux系统是否正常,编写一个简单的Demo测试程序,通过串口打印“Hello World”。将生成的可执行文件拷贝到U盘里,然后将U盘插入板子的USB口,在终端输入如下信息:
将U盘挂载到文件系统的/home/workdir目录下,执行Hello文件
root@socfpga:~$ mount -t vfat /dev/sda1 /home/workdir
root@socfpga:~$ ./Hello
串口输出信息“Hello world”
文件系统裁剪
使用Busybox裁剪文件系统,配置如下:
- PC机系统:Ubuntu 12.04 LTS
- 目标板:Altera Cyclone Soc
- Flash类型:QSPI Flash(32M)
- Busybox:busybox-1.23.2.tar.bz2
- 嵌入式交叉编译工具链:arm-linux-gnueabihf-
- 目标板根文件系统格式:jiffs2(在闪存上使用非常广泛的读/写文件系统)
- 根文件系统制作工具:mkfs.jffs2
获取BusyBox源码
从http://busybox.net/downloads/获取busybox源码包,使用如下命令解压:
tar -jxvf busybox-1.23.2.tar.bz2
cd busybox-1.23.2
make 目标
说明
help
显示 make 选项的完整列表
defconfig
启用默认的(通用)配置
allnoconfig
禁用所有的应用程序(空配置)
allyesconfig
启用所有的应用程序(完整配置)
allbareconfig
启用所有的应用程序,但是不包括子特性
config
基于文本的配置工具
menuconfig
N-curses(基于菜单的)配置工具
all
编译 BusyBox 二进制文件和文档(./docs)
busybox
编译 BusyBox 二进制文件
clean
清除源代码树
distclean
彻底清除源代码树
sizes
显示所启用的应用程序的文本/数据大小
配置BusyBox
//以图形界面进行选择配置
注意:在 Busybox Settings ---> Build Options 中注意下面两个选项:
[*]Build BusyBox as a static binary (no shared libs)
(arm-linux-gnueabihf- )Cross Compiler prefix
其中:
前者选项用于是否把busybox编译成静态链接的可执行文件。如果选择该选项,编译出来的 busybox就是静态链接的,运行时不依赖于动态库,但体积较大;清除该选项将得到动态链接的 busybox,体积较小,但需要动态库的支持。后者选项是用于选择 SDK 推荐的交叉编译器。
配置好后保存并退出。这个步骤中,可以对busybox进行裁剪,根据实际需要裁剪掉某些命令或者库,可以减小镜像文件的大小。
$make ARCH=arm CROSS_COMPILE=/opt/gcc-linaro-arm-linux-gnueabihf-4.9-2014.05_linux/bin/arm-linux-gnueabihf- menuconfig
编译和安装 busybox
使用如下命令编译、安装:
$make ARCH=arm CROSS_COMPILE=/opt/gcc-linaro-arm-linux-gnueabihf-4.9-
2014.05_linux/bin/arm-linux-gnueabihf-
$make ARCH=arm CROSS_COMPILE= /opt/gcc-linaro-arm-linux-gnueabihf-4.9-
2014.05_linux/bin/arm-linux-gnueabihf- install
编译并安装成功后,在 busybox 目录下的/home/arvin/workdir/soc-fpga/busybox-1.23.2/_install 目录下生成以下目录及文件,如下图所示:
制作根文件系统
具体操作步骤如下:
创建rootfs目录
cd /home/arvin/workdir/soc-fpga/busybox-1.23.2
mkdir socfpga_fs
cd socfpga_fs/
从BusyBox中获取相应文件夹到socfpga_fs中
cp -rfa ../_install/* .
创建文件系统中常用的目录
mkdir etc dev lib tmp var mnt home proc tmpfs
获取系统依赖库
注意此步骤获取的是交叉编译工具链目录下的lib目录下的so库。如果用错了系统依赖的库,会导致只有BusyBox编译出来的命令可以正常运行,而你自己的用户态程序运行时报错:Input/Output error。另外可用如下命令查看所需要的动态库:
arm-linux-gnueabihf-ar -d busybox | grep lib
如下图所示:
获取其它工具
如果需要某些特别的工具,可从网上下载源码,用交叉编译器编译,将可执行的bin文件,拷贝到socfpga_fs/bin/目录下即可。
添加系统运行所需要的模块驱动
我们自己编写的设备驱动如果在编译内核时是以模块的方式编译(不会编译进内核,使用时加载),其中这些模块的驱动默认在/home/arvin/workdir/soc-fpga/linux-socfpga-
3.12/lib/modules/的目录,把这些文件拷贝到socfpga_fs/lib/modules/目录下即可。
获取用户程序运行所依赖的库
如果某些应用程序接口编译成lib的形式,需要把这些文件拷贝到socfpga_fs/usr/lib/目录下。
生成根文件系统镜像
进入文件系统目录,输入如下命令:
cd /home/arvin/workdir/soc-fpga/busybox-1.23.2/socfpga_fs
sudo mkfs.jffs2 -d rootfs/ --pagesize=0x100 --eraseblock=0x10000 -n -l –
output=./rfs_p100_e10000.jffs2
到此,就生成了一个初级的rootfs_64k.jffs2根文件系统镜像文件了。
U-BOOT启动流程分析
uboot源码顶层目录
Folder
Description
api/
Architecture independent API for external applications
arch/
Architecture specific folder
board/
Board related files
common/
Different common files, such as SPL and U-Boot commands
disk/
Disk related files
doc/
Documentation folder, in text format
drivers/
Drivers folder
dts/
Device Tree related files
examples/
Example source code
fs/
Filesystem source code
include/
Include files
lib/
Various libraries, such as compression, random number generation etc.
nand_spl/
Files use when booting from NAND
net/
Network stack source code
post/
Power-on Self Test files
spl/
Preloader Files
test/
Test code
tools/
Host tools folder. The most important is mkimage
boards.cfg
Describes all the supported platforms in a tabular text format
与平台相关的文件
Folder
Description
arch/arm/cpu/armv7/socfpga/
Architecture specific files, like clock manager, interrupt controller etc
arch/arm/include/asm/arch-socfpga/
Include files for the architecture specific source code
board/altera/socfpga/
Board specific files - some generated by the Preloader Generator
board/altera/socfpga/sdram
Board specific DDRAM files - some generated by the Preloader Generator
与SOC目标板相关的硬件配置文件
Folder
File
Generated
Description
board/altera/socfpga/
build.h
yes
Preloader Build
Parameters
iocsr_config_arria5.c
yes
I/O Pin
Configuration Blob (Arria V)
iocsr_config_arria5.h
yes
iocsr_config_cyclone5.c
yes
I/O Pin
Configuration Blob (Cyclone V)
iocsr_config_cyclone5.h
yes
pinmux_config.h
yes
Pin Muxing
Parameters Header
pinmux_config_arria5.c
yes
Pin Muxing
Parameters (Arria V)
pinmux_config_cyclone5.c
yes
Pin Muxing
Parameters (Cyclone V)
pll_config.h
yes
Clocking Configuration
reset_config.h
yes
Reset Configuration
Makefile
Makefile
socfpga_common.c
Common Functions
socfpga_arria5.c
Displays Board
Name (Arria V)
socfpga_cyclone5.c
Displays Board
Name (Cyclone V)
timestamp_config.h
Timestamp File
board/altera/socfpga/sdram/
sdram_config.h
yes
SDRAM Configuration Parameters
Makefile
SDRAM Configuration Makefile
alt_types.h
SDRAM Configuration Source Code
sdram.h
sdram_io.h
sequencer.c
sequencer.h
sequencer_auto.h
sequencer_auto_ac_init.c
sequencer_auto_inst_init.c
sequencer_defines.h
system.h
tclrpt.c
tclrpt.h
SOC目标板参数配置文件
File
Description
doc/README.SOCFPGA
SoC specific readme file
doc/README.SPL
SPL specific readme file
include/configs/socfpga_arria5.h
Arria V configuration file
include/configs/socfpga_cyclone5.h
Cyclone V configuration file
include/configs/socfpga_common.h
Common configuration file for Cyclone V and Arria V
boards.cfg
File defining all the supported targets
注:其中2、3、4是与SOC相关的文件,如果需要对u-boot进行移植或更改配置,修改以上文件内容即可。
u-boot启动流程介绍
下图是u-boot的启动顺序流程,这对移植、调试u-boot有很大的帮助。
u-boot、内核、FPGA加载方式
更详细介绍请参考如下网址:
https://rocketboards.org/foswiki/view/Documentation/PreloaderUbootCustomization131?sortcol=0;table=3;up=0HYPERLINK "https://rocketboards.org/foswiki/view/Documentation/PreloaderUbootCustomization131?sortcol=0;table=3;up=0HYPERLINK%20%22https://rocketboards.org/foswiki/view/Documentation/PreloaderUbootCustomization131?sortcol=0;table=3;up=0%22$HYPERLINK%20%22https://rocketboards.org/foswiki/view/Documentation/PreloaderUbootCustomization131?sortcol=0;table=3;up=0%22sorted_table"$HYPERLINK "https://rocketboards.org/foswiki/view/Documentation/PreloaderUbootCustomization131?sortcol=0;table=3;up=0HYPERLINK%20%22https://rocketboards.org/foswiki/view/Documentation/PreloaderUbootCustomization131?sortcol=0;table=3;up=0%22$HYPERLINK%20%22https://rocketboards.org/foswiki/view/Documentation/PreloaderUbootCustomization131?sortcol=0;table=3;up=0%22sorted_table"sorted_table
HPS启动与BOOT ROM执行流程
HPS启动流程
HPS作为一个SoC器件,所有执行程序都要遵循严格的启动流程, HPS的启动是多阶段的流程,每一个阶段都会完成自己相应的工作并把下一阶段的执行代码引导起来。下图展示了一个典型的HPS的启动流程
系统复位(上电或者硬件复位)之后,HPS内部boot Rom开始在CPU0上执行(通过指定复位向量指定BOOT ROM区域实现自动执行BOOT ROM),完成工作并引导用户程序,当然用户程序的构架会因为具体引用有所差别!
Boot ROM介绍
总的来说,Boot ROM是HPS内核的一段ROM上固化的可执行程序,完成的工作是系统复位以后,执行引导preloader并把CPU使用权交给preloader 的过程!特殊情况是不需要执行preloader而直接引导应用程序,这种情况是可能的,比如DS-5中baremental HelloWorld程序,但是这种情况并没有实际运用意义:其一是限制了程序大小,容量受片上RAM限制;其二是运用程序基本只能够使用到MPU内部的寄存器,外设没有被初始化(没有相应的时钟)。所以更多的应用是Boot ROM 通过引导preloader把CPU使用权交给preloader进行后续的引导工作。
BOOT ROM除了引导用户软件外还完成的具体工作有:
1、使能指令缓存, branch predictor,浮点单元,NEON 向量单元[在ARM内部做过图形加速的可能比较熟悉]
2、设定看门狗0定时器,BOOT ROM保留适用,参考文档 page A-11
3、根据CLKSEL设定配置Main PLL 和外设PLL
4、根据BOOTSEL设定配置I/O pin的复用(此处应该只是完成了QSPI or SPI Flash or SDMMC controller 的pin的复用,更多的pin的复用需要根据preloader才能够完成设定 )
5、初始化FLASH Controller 到默认设置
BOOT ROM 引导的preloader来源分为三类:
1、片上RAM热启动,对应下图中的矩形框①
如果之前执行过一次preloader了,preloader会留在On-chip RAM 中,按下WARM reset 后,会首先选择从on-chip RAM 启动,此过程具有最高优先权,但是从on-chip RAM 启动时会对遗留的preloader代码进行CRC校验(具体是否校验用户可以通过warmramgrp配置决定),校验成功才会执行。防止了用户对ON-chip 里的内容进行更改!如校验失败,会选择从Flash中启动preloader,对应图中矩形框 ③
2、从FPGA部分冷启动,对应下图中的矩形框②
具有第二优先权,如果用户设定了bootsel从FPGA启动,则会等待FPGA配置成功[通过FPGA manager获取FPGA的状态]!HPS会通过 HPS-to-FPGA bridge执行位于 0xC0000000【相对于HPS-to-FPGA bridge偏移地址为0】的momory中的指令。对应着GHRD中on-chip memory的功用,这里大概知道即可。
3、从Flash 存储器启动,对应图中矩形框④
▲如果在Flash中找不到preloader的话,则会检验FPGA处的回调镜像(callback image)【这个image暂没有见到更多说明和使用】
▲依然不成功就只能坐等被复位了!见图中矩形框 ⑤ 、 ⑥
BOOT ROM执行流程
说明:
⑴只有冷启动才会选择从FPGA 引导
⑵不论热启动还是FPGA冷启动,如不成功都会进入到了红色框的QSPI启动中
⑶矩形框②中的yes 和 no 由bootsel 决定,矩形框③、④中最后具体是使用哪个FLASH存储器也由bootsel管脚决定。
本文参考:
①Altera Booting and Configuration Introduction Document: http://www.altera.com/literature/hb/cyclone-v/cv_5400A.pdf
DTB文件介绍
Device Tree由一系列被命名的结点(node)和属性(property)组成,而结点本身可包含子结点。所谓属性,其实就是成对出现的name和value。在Device Tree中,可描述的信息包括(原先这些信息大多被hard code到kernel中):
- CPU的数量和类别
- 内存基地址和大小
- 总线和桥
- 外设连接
- 中断控制器和中断使用情况
- GPIO控制器和GPIO使用情况
- Clock控制器和Clock使用情况
它基本上就是画一棵电路板上CPU、总线、设备组成的树,Bootloader会将这棵树传递给内核,然后内核可以识别这棵树,并根据它展开出Linux内核中的platform_device、i2c_client、spi_device等设备,而这些设备用到的内存、IRQ等资源,也被传递给了内核,内核会将这些资源绑定给展开的相应的设备。
基本格式如下:
/ {
node1 {
a-string-property = "A string";
a-string-list-property = "first string", "second string";
a-byte-data-property = [0x01 0x23 0x34 0x56];
child-node1 {
first-child-property;
second-child-property = <1>;
a-string-property = "Hello, world";
};
child-node2 {
};
};
node2 {
an-empty-property;
a-cell-property = <1 2 3 4>; /* each number (cell) is a uint32 */
child-node1 {
};
};
};
关于设备树的格式及标准请参考:http://elinux.org/Device_Tree_Usage
详细介绍请参考http://blog.csdn.net/tomtntlili/article/details/17994583
ARM DS-5软件介绍
编译器选择
打开一个工程,右键选择“Properties”->“C/C++ Build”的“Tool Chain Editor”窗口进行配置,如下图所示:
PCI驱动开发及DEMO测试
官方参考链接
https://rocketboards.org/foswiki/view/Projects/PCIeRootPortWithMSI
PCIe Root Port
The PCIe HIP module in the Arria 10 SoC is configured to operate as a root port. It provides Avalon slave bus interfaces to initiate configuration space (CRA) and memory space (TXS) accesses. It also provides Avalon master bus interfaces (BARx) to allow PCIe bus master devices to access SoC FPGA resources. Please refer to the PCIe HIP User's Guide for more information. The PCIe root port has been configured for Generation 2 speed and x4 lanes (Gen2 x4). One Base Address Register (BAR0) is enabled to allow PCIe bus master devices to access the system 1GB SDRAM and the 256kB on chip RAM, as well as route MSI messages to the HPS GIC.
所需安装包
The PCIe RP reference design sources and prebuilt binaries can be downloaded from here.
Folder
File
Description
bin
linux-socfpga-pcierd-16.0-a10-bin.tar.gz
Arria 10 binaries archive (including SD Card Image)
linux-socfpga-pcierd-16.0-cv-bin.tar.gz
Cyclone V binaries archive (including SD Card Image)
linux-socfpga-pcierd-16.0-av-bin.tar.gz
Arria V binaries archive (including SD Card Image)
hw
cv_ep_ram_gt_design.tar.gz
Cyclone V DMA End Point Design (including SOF file)
a10_soc_devkit_pcie.tar.gz
Arria 10 PCIe Root Port Design
cv_soc_devkit_pcie.tar.gz
Cyclone V PCIe Root Port Design
av_soc_devkit_pcie.tar.gz
Arria V PCIe Root Port Design
src
a10_soc_devkit_pcierd-src.tar.gz
Arria 10 Device tree source
cv_soc_devkit_pcierd-src.tar.gz
Cyclone V Device tree source and U-boot Script
av_soc_devkit_pcierd-src.tar.gz
Arria V Device tree source and U-boot Script
U-boot, Linux kernel and Yocto source packages are also provided through the git trees at https://github.com/altera-opensource, as shown in the table below.
Component
Git Address
Branch
Tag
Linux
linux-socfpga.git
socfpga-4.1-ltsi
ACDS16.0_REL_PCIE_PR
Angstrom
angstrom-socfpga.git
angstrom-v2014.12-socfpga_gsrd16.0
ACDS16.0_REL_GSRD_PR
Ref Design
linux-refdesigns.git
socfpga-16.0
ACDS16.0_REL_GSRD_PR
内核增加PCIe驱动(打补丁)
给内核打补丁,增加PCIe驱动:
arvin@arvin-socFpga:~/workdir/yocto/borax_310_LTSI/linux-socfpga$ git apply --check 0001-Add-PCIe-RP-and-MSI-drivers.patch
error: patch failed: arch/arm/configs/socfpga_defconfig:18
error: arch/arm/configs/socfpga_defconfig: patch does not apply
arvin@arvin-socFpga:~/workdir/yocto/borax_310_LTSI/linux-socfpga$make ARCH=arm socfpga_defconfig
$
$ configuration written to .config
$
补丁包内容解析:
http://www.hovercool.com/en/%E8%A7%A3%E6%9E%90linux_patch
强制给内核打补丁:
git apply --reject 001-Add-PCIe-RP-and-MSI-drivers.patch
git add arch/arm/Kconfig
git add arch/arm/configs/socfpga_defconfig
git add arch/arm/mach-socfpga/Kconfig
git add drivers/pci/Kconfig
git add drivers/pci/Makefile
git add drivers/pci/msi.c
使用詹共提供的内核包打补丁时提示如下:
arvin@arvin-socFpga:/opt/Cyclonev/borax_310_LTSI/linux-socfpga$ git apply --check 001-Add-PCIe-RP-and-MSI-drivers.patch
error: patch failed: arch/arm/configs/socfpga_defconfig:18
error: arch/arm/configs/socfpga_defconfig: patch does not apply
arvin@arvin-socFpga:~/workdir/yocto/borax_310_LTSI/linux-socfpga/linux-socfpga$ git apply --check 001-Add-PCIe-RP-and-MSI-drivers.patch
error: Documentation/devicetree/bindings/pci/altera-pcie-msi.txt: already exists in working directory
error: Documentation/devicetree/bindings/pci/altera-pcie.txt: already exists in working directory
error: patch failed: arch/arm/Kconfig:293
error: arch/arm/Kconfig: patch does not apply
error: patch failed: arch/arm/configs/socfpga_defconfig:18
error: arch/arm/configs/socfpga_defconfig: patch does not apply
error: patch failed: arch/arm/mach-socfpga/Kconfig:1
error: arch/arm/mach-socfpga/Kconfig: patch does not apply
error: patch failed: drivers/pci/Kconfig:119
error: drivers/pci/Kconfig: patch does not apply
error: patch failed: drivers/pci/Makefile:67
error: drivers/pci/Makefile: patch does not apply
error: drivers/pci/host/Kconfig: already exists in working directory
error: drivers/pci/host/Makefile: already exists in working directory
error: drivers/pci/host/pci-altera-msi.c: already exists in working directory
error: drivers/pci/host/pci-altera.c: already exists in working directory
error: drivers/pci/host/pci-altera.h: already exists in working directory
error: patch failed: drivers/pci/msi.c:31
error: drivers/pci/msi.c: patch does not apply
使用
arvin@arvin-socFpga:~/workdir/yocto/borax_310_LTSI/linux-socfpga/linux-socfpga$ git apply 001-Add-PCIe-RP-and-MSI-drivers.patch --reject
Checking patch Documentation/devicetree/bindings/pci/altera-pcie-msi.txt...
error: Documentation/devicetree/bindings/pci/altera-pcie-msi.txt: already exists in working directory
Checking patch Documentation/devicetree/bindings/pci/altera-pcie.txt...
error: Documentation/devicetree/bindings/pci/altera-pcie.txt: already exists in working directory
Checking patch arch/arm/Kconfig...
error: while searching for:
select ARM_PATCH_PHYS_VIRT
select AUTO_ZRELADDR
select COMMON_CLK
select MULTI_IRQ_HANDLER
select SPARSE_IRQ
select USE_OF
error: patch failed: arch/arm/Kconfig:293
Checking patch arch/arm/configs/socfpga_defconfig...
error: while searching for:
# CONFIG_IOSCHED_CFQ is not set
CONFIG_ARCH_SOCFPGA=y
CONFIG_ARM_THUMBEE=y
CONFIG_SMP=y
CONFIG_VMSPLIT_2G=y
CONFIG_NR_CPUS=2
error: patch failed: arch/arm/configs/socfpga_defconfig:18
Checking patch arch/arm/mach-socfpga/Kconfig...
error: while searching for:
config ARCH_SOCFPGA
bool "Altera SOCFPGA family" if ARCH_MULTI_V7
select ARCH_WANT_OPTIONAL_GPIOLIB
select ARM_AMBA
select ARM_GIC
error: patch failed: arch/arm/mach-socfpga/Kconfig:1
Checking patch drivers/pci/Kconfig...
error: while searching for:
config PCI_LABEL
def_bool y if (DMI || ACPI)
select NLS
error: patch failed: drivers/pci/Kconfig:119
Checking patch drivers/pci/Makefile...
error: while searching for:
obj-$(CONFIG_OF) += of.o
ccflags-$(CONFIG_PCI_DEBUG) := -DDEBUG
error: patch failed: drivers/pci/Makefile:67
Checking patch drivers/pci/host/Kconfig...
error: drivers/pci/host/Kconfig: already exists in working directory
Checking patch drivers/pci/host/Makefile...
error: drivers/pci/host/Makefile: already exists in working directory
Checking patch drivers/pci/host/pci-altera-msi.c...
error: drivers/pci/host/pci-altera-msi.c: already exists in working directory
Checking patch drivers/pci/host/pci-altera.c...
error: drivers/pci/host/pci-altera.c: already exists in working directory
Checking patch drivers/pci/host/pci-altera.h...
error: drivers/pci/host/pci-altera.h: already exists in working directory
Checking patch drivers/pci/msi.c...
error: while searching for:
/* Arch hooks */
#ifndef arch_msi_check_device
int arch_msi_check_device(struct pci_dev *dev, int nvec, int type)
{
return 0;
}
error: patch failed: drivers/pci/msi.c:31
Applying patch arch/arm/Kconfig with 1 reject...
Rejected hunk #1.
Applying patch arch/arm/configs/socfpga_defconfig with 1 reject...
Rejected hunk #1.
Applying patch arch/arm/mach-socfpga/Kconfig with 1 reject...
Rejected hunk #1.
Applying patch drivers/pci/Kconfig with 1 reject...
Rejected hunk #1.
Applying patch drivers/pci/Makefile with 1 reject...
Rejected hunk #1.
Applying patch drivers/pci/msi.c with 1 reject...
Rejected hunk #1.
Patch失败解决方法请参考:http://blog.csdn.net/sunnylgz/article/details/7660638
统一输出格式中,使用---表示旧文件,使用+++表示新文件;文件中的多个不同的文本或代码段,使用@@开始,@@结束的一行来开始;有-号的是删除的行,有+号的是新增的行
--- autoconf-2.7/acgeneral.m4 Wed Nov 22 11:42:00 1995 ## 旧文件
+++ autoconf-2.9/acgeneral.m4 Sat Mar 16 15:53:07 1996 ## 新文件
@@ -1,7 +1,7 @@ ## 第一段不同的地方,旧文件从1行开始,共7行;新文件从1行开始,共7行
dnl Parameterized macros. ## 无+—符号,是引用的内容
dnl Requires GNU m4.
dnl This file is part of Autoconf.
-dnl Copyright (C) 1992, 1993, 1994, 1995 Free Software Foundation, Inc. ## 删除的内容
+dnl Copyright (C) 1992, 1993, 1994, 1995, 1996 Free Software Foundation, Inc. ## 替换的内容
dnl
dnl This program is free software; you can redistribute it and/or modify
dnl it under the terms of the GNU General Public License as published by
@@ -51,7 +51,7 @@ ## 第二段不同之处
divert(-1)dnl Throw away output until AC_INIT is called.
changequote([, ])
-define(AC_ACVERSION, 2.7)
+define(AC_ACVERSION, 2.9)
dnl Some old m4′s don’t support m4exit. But they provide
dnl equivalent functionality by core dumping because of the
内核配置MSI驱动
禁止MSI
The following steps illustrate how to disable MSI.
- Go to Linux kernel top directory and type “make menuconfig“
- Disable Bus support->Message Signaled Interrupts (MSI and MSI-X)
- Save and exit
- Recompile kernel
使能MSI
The following steps illustrate how to enable MSI.
- Go to Linux kernel top directory and type “make menuconfig“
- Enable Bus support->Message Signaled Interrupts (MSI and MSI-X)
- Enable Bus support->PCI host controller drivers->Altera PCIe controller->Altera MSI-to-GIC support
- Save and exit
- Recompile kernel
编译Host system 和End point device 驱动
Both device drivers are built as Loadable Kernel Module (LKM), and load into Kernel at run time after system booted.
- download the modules.tar.gz to<path-to-your-Linux-kernel-directory>
- untar modules.tar.gz to <path-to-your-Linux-kernel-directory>
- cd <path-to-your-Linux-kernel-directory>/modules
- $ make KERNEL_SRC=<path-to-your-Linux-kernel-directory>
- Copy altera_rpde.ko and altera_epde.ko into SD card.
- Use insmod command to load these 2 kernel modules on SOCFPGA terminal.
编译ThroughputLinux应用
The application is compiled with ARM cross-compiler.
$ arm-linux-gnueabihf-gcc -o dmaxfer dmaxfer.c
官方dts转dtb文件出错
使用cv_soc_devkit_pcierd-src.tar.gz压缩包里提供的DTS文件编译出错,提示缺少节点,出错信息如下:
官方PCIe HW例程Quartus II编译出错
从https://rocketboards.org/foswiki/view/Projects/PCIeRootPortWithMSI
Qsys Design and Generation
pcie_rp_ed_5csxfc6.qsys is the Qsys top level design file. The design consists of a HPS subsystem, PCIe HIP, Modular SGDMA subsystem, and some peripherals designed for PCIe RP example.
The user is only required to perform Qsys generation for pcie_rp_ed_5csxfc6.qsys . Generated RTL will be contained in pcie_rp_ed_5csxfc6 folder.
下载如下的例程软件包:
压缩解压完后编译出现如下错误:
- ERR1
Error (10228): Verilog HDL error at pcie_rp_ed_5csxfc6_sysid_qsys.v(21): module "pcie_rp_ed_5csxfc6_sysid_qsys" cannot be declared more than once
Error: Quartus II 64-Bit Analysis & Synthesis was unsuccessful. 1 error, 12 warnings
Error: Peak virtual memory: 790 megabytes
Error: Processing ended: Tue Aug 09 15:01:52 2016
Error: Elapsed time: 00:04:22
Error: Total CPU time (on all processors): 00:07:15
Error (293001): Quartus II Full Compilation was unsuccessful. 3 errors, 12 warnings
- 解决方法:
D:Cyclonevcv_soc_rp_full_designcv_soc_rp_full_designpcie_rp_ed_5csxfc6synthesissubmodules目录下载存在多个pcie_rp_ed_5csxfc6_sysid_qsys.v文件,删除旧的文件,保留最新的一个文件即可。
官方HW例程直接生成dts出错
sopc2dts --input pcie_rp_ed_5csxfc6.sopcinfo
--output socfpga.dts
--board pcie_rp_ed_5csxfc6_board_info.xml
--board hps_clock_info.xml
提示如下错误:
sopc2dts --input pcie_rp_ed_5csxfc6.sopcinfo --output socfpga15.0.dts -b pcie_rp_ed_5csxfc6_board_info.xml --board hps_common_board_info.xml --clocks --bridge-removal all
将EDS版本升级到15.0.1,生成dts,提示如下:
使用詹工提供的kernel包,在打补丁时提示如下
PCIe DEMO测试流程
Root Port<->End Point
benchmark tests using the Cyclone V GT FPGA PCIe End Point design. The benchmarking software will use the root port and end point mSGDMA modules to move data to and from the system SDRAM and the on-chip RAM and report the results in a table.
Discover End Point and Check Linux Kernel Modules
First, check that the FPGA PCIe end point has been discovered by the PCIe root port and that the proper Linux kernel modules have been loaded. Use the following command and ensure that the Altera Corporation Device e001 andaltera_epdma entries appear as shown below:
root@arria10:~# /usr/sbin/lspci
00:00.0 PCI bridge: Altera Corporation Device e000 (rev 01)
01:00.0 Unassigned class [ff00]: Altera Corporation Device e001 (rev 0a)
root@arria10:~# lsmod
Module Size Used by
altera_epdma 4972 0
gpio_altera 4277 4
altera_sysid 1875 0
altera_rpdma 5581 0
该测试代码是rp与EP之间的SGDMA模块来搬运数据
测试数据收发带宽
Next, run the benchmarking software with the following commands ...
root@arria10:~# cd altera
root@arria10:~/altera# ls
dmaxfer
root@arria10:~/altera# ./dmaxfer
==================================================
PCIe throughput test
RP-OCM = Rootport On-Chip RAM
EP-OCM = Endpoint On-Chip RAM
RP-SYS = Rootport System Memory
==================================================
Source Destination Results (MB/s)
-----------------------------------------------------------
RP-DMA TX RP-OCM EP-OCM ####
RP-DMA RX EP-OCM RP-OCM ####
RP-DMA TX RP-SYS EP-OCM ####
RP-DMA RX EP-OCM RP-SYS ####
-----------------------------------------------------------
EP-DMA TX EP-OCM RP-OCM ####
EP-DMA RX RP-OCM EP-OCM ####
EP-DMA TX EP-OCM RP-SYS ####
EP-DMA RX RP-SYS EP-OCM ####
root@arria10:~/altera#
The "####" columns above will show the benchmarking results.
数据流向
The mSGDMA in the root point (RP-DMA) is used to push and pull data from the FPGA end point, and the mSGDMA in the FPGA end point (EP-DMA) is used to push and pull data from the root port. Source and destination for data transfers can be root port external system memory (RP-SYS), root port on-chip memory (RP-OCM), and end point on-chip memory (EP-OCM).
PCIe开发流程
Build PCIe Root Port
- Download the Project
For Arria 10, the project is available here: a10_pcie_soc_devkit.tar.gz
For Cyclone V, the project is available here: cv_pcie_soc_devkit.tar.gz
For Arria V, the project is available here: av_pcie_soc_devkit.tar.gz
- Build the project
The root port design is based on the Arria 10 GHRD. However, it can be applied on Cyclone V GHRD and Arria V GHRD as well.
For Arria 10, follow the instructions listed at Compiling Hardware Design, but replace the GHRD source code filea10_soc_devkit_ghrd.tar.gz with the file listed above.
For Cyclone V, follow the instructions listed at Compiling Hardware Design, but replace the GHRD source code filecv_soc_devkit_ghrd.tar.gz with the file listed above.
For Arria V, follow the instructions listed at Compiling Hardware Design, but replace the GHRD source code fileav_soc_devkit_ghrd.tar.gz with the file listed above.
详细操作请参考网站: https://rocketboards.org/foswiki/view/Documentation/GSRD160CompileHardwareDesign
注意:该步骤编译出来的~/cv_soc_devkit_ghrd/hps_isw_handoff在编译preloader及u-boot会用。
Converting .sof to .rbf
Several different options are available for converting the file:
- Using the command line tools from Quartus Programmer (installed by default with the SoC EDS or installed standalone) or from Quartus.
$ ~/altera/16.0/quartus/bin/quartus_cpf -c
~/cv_soc_devkit_ghrd/output_files/soc_system.sof
~/cv_soc_devkit_ghrd/output_files/soc_system.rbf
- Using the GUI converter, callable from either Quartus Programmer or Quartus by selecting the menu File -> Convert Programming Files.
1、Select the Programming File Type to be Raw Binary File (.rbf)
2、Select the Mode to be Fast Passive Parallel X8 or 16
3、Click on the SOF Data then click Add File and browse to the soc_system.sof file
4、Edit the desired name of the output file to be soc_system.rbf
5、Click the Generate button
Build Cyclone V GT PCIe End Point
- Download the Project
The project is available here: cv_ep_ram_gt_design.tar.gz
- Build the project
Perform a standard Quartus build flow (Generate system using the Qsys tool, then compile to generate the SOF file)
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