AES算法中S盒的FPGA实现 II
2024-05-12 12:36:12
AES算法中S盒的FPGA实现 II
语言 ： verilog EDA
工具 ： quartus
仿真 ： Modelsim
- AES算法中S盒的FPGA实现 II
- 一、引言
- 二、S盒的FPGA实现
- 2.1 write_data模块的FPGA实现
- 2.2 双端口RAM的调用
- 2.3 顶层模块
- 2.4 S盒实现工程的说明
- 三、S盒FPGA实现的仿真
一、引言
在 AES算法中S盒的FPGA实现 I 中简介了S盒的解释和具体的内容， 本篇博客， 主要讲解如何在FPGA中实现S盒。
二、S盒的FPGA实现
2.1 write_data模块的FPGA实现
module write_data(input clk ,input rst_n,input[1:0] Sbox_mode,input Sbox_write_en,output reg Sbox_ready,output reg[3:0] data0 , output reg[3:0] data1 ,output reg[3:0] data2 , output reg[3:0] data3 ,output reg[3:0] data4 , output reg[3:0] data5 ,output reg[3:0] data6 , output reg[3:0] data7 ,output reg[3:0] data8 , output reg[3:0] data9 ,output reg[3:0] data10, output reg[3:0] data11,output reg[3:0] data12, output reg[3:0] data13,output reg[3:0] data14, output reg[3:0] data15,output reg[3:0] data16, output reg[3:0] data17, output reg[3:0] data18,output reg[3:0] data19, output reg[3:0] data20,output reg[3:0] data21, output reg[3:0] data22,output reg[3:0] data23, output reg[3:0] data24,output reg[3:0] data25, output reg[3:0] data26,output reg[3:0] data27, output reg[3:0] data28,output reg[3:0] data29, output reg[3:0] data30,output reg[3:0] data31, output reg[3:0] wraddr,output reg wren
);parameter IDLE = 3'd0;parameter WRITE_CHOOSE = 3'd1;parameter WRITE_MODE1 = 3'd2;parameter WRITE_MODE2 = 3'd3;parameter WRITE_MODE3 = 3'd4;parameter WRITE_MODE4 = 3'd5; parameter WRITE_FINISH = 3'd6;parameter MODE1_DATA = 128'H02010704080F0E030D0A00090B06050C;parameter MODE2_DATA = 128'H050806030C07020B000A090D010F0E04; parameter MODE3_DATA = 128'H050C0607030802010B0A040D000F090E;parameter MODE4_DATA0= 128'H76ABD7FE2B670130C56F6BF27B777C63;parameter MODE4_DATA1= 128'HC072A49CAFA2D4ADF04759FA7DC982CA;parameter MODE4_DATA2= 128'H1531D871F1E5A534CCF73F362693FDB7;parameter MODE4_DATA3= 128'H75B227EBE28012079A059618C323C704;parameter MODE4_DATA4= 128'H842FE329B3D63B52A05A6E1B1A2C8309;parameter MODE4_DATA5= 128'HCF584C4A39BECB6A5BB1FC20ED00D153; parameter MODE4_DATA6= 128'HA89F3C507F02F94585334D43FBAAEFD0;parameter MODE4_DATA7= 128'HD2F3FF1021DAB6BCF5389D928F40A351;parameter MODE4_DATA8= 128'H73195D643D7EA7C41744975FEC130CCD;parameter MODE4_DATA9= 128'HDB0B5EDE14B8EE4688902A22DC4F8160;parameter MODE4_DATA10=128'H79E4959162ACD3C25C2406490A3A32E0; parameter MODE4_DATA11=128'H08AE7A65EAF4566CA94ED58D6D37C8E7; parameter MODE4_DATA12=128'H8A8BBD4B1F74DDE8C6B4A61C2E2578BA; parameter MODE4_DATA13=128'H9E1DC186B95735610EF6034866B53E70; parameter MODE4_DATA14=128'HDF2B55CEE9871E9B948ED9691198F8E1; parameter MODE4_DATA15=128'H16BB54B00F2D99416842E6BF0D89A18C; reg Sbox_write_en_reg;
wire Sbox_write_en_pos;
reg[2:0] state;
wire Sbox_ready_neg;assign Sbox_write_en_pos = Sbox_write_en && !Sbox_write_en_reg;always@(posedge clk or negedge rst_n)
beginif( !rst_n )Sbox_write_en_reg <= 0;else Sbox_write_en_reg <= Sbox_write_en;endalways@( posedge clk or negedge rst_n)
beginif( !rst_n ) beginstate <= 0;endelse begincase( state )IDLE :beginif(Sbox_write_en_pos) state <= WRITE_CHOOSE;elsestate <= IDLE;endWRITE_CHOOSE :beginif(Sbox_mode == 2'b0)state <= WRITE_MODE1;else if( Sbox_mode == 2'b1)state <= WRITE_MODE2;else if( Sbox_mode == 2'd2)state <= WRITE_MODE3;else if( Sbox_mode == 2'd3)state <= WRITE_MODE4; elsestate <= WRITE_MODE1; endWRITE_MODE1 :begin if( Sbox_ready_neg)state <= WRITE_FINISH;else state <= state;endWRITE_MODE2 :begin if( Sbox_ready_neg)state <= WRITE_FINISH;else state <= state;end WRITE_MODE3 :begin if( Sbox_ready_neg)state <= WRITE_FINISH;else state <= state;endWRITE_MODE4 :begin if( Sbox_ready_neg)state <= WRITE_FINISH;else state <= state;end WRITE_FINISH :beginstate <= IDLE;end default :beginstate <= IDLE;end endcaseendendreg[9:0] cnt;always@( posedge clk or negedge rst_n)
beginif( !rst_n ) beginSbox_ready <= 0;wraddr <= 0;wren <= 0; cnt <= 0;data0 <= 0;data1 <= 0;data2 <= 0;data3 <= 0;data4 <= 0;data5 <= 0;data6 <= 0;data7 <= 0;data8 <= 0;data9 <= 0;data10 <= 0;data11 <= 0;data12 <= 0;data13 <= 0;data14 <= 0;data15 <= 0;data16 <= 0;data17 <= 0;data18 <= 0;data19 <= 0;data20 <= 0;data21 <= 0;data22 <= 0;data23 <= 0;data24 <= 0;data25 <= 0;data26 <= 0;data27 <= 0;data28 <= 0;data29 <= 0;data30 <= 0;data31 <= 0;endelse beginif(state == WRITE_CHOOSE)Sbox_ready <= 1;elseif( state == WRITE_MODE1 ) beginif(cnt == 16) begincnt <= cnt;wren <= 0;Sbox_ready <= 0;endelse beginwren <= 1;cnt <= cnt +1;endif(wren == 1) beginwraddr <= wraddr +1;data0 <= MODE1_DATA[3:0];data1 <= MODE1_DATA[7:4]; data2 <= MODE1_DATA[11:8];data3 <= MODE1_DATA[15:12]; data4 <= MODE1_DATA[19:16];data5 <= MODE1_DATA[23:20]; data6 <= MODE1_DATA[27:24];data7 <= MODE1_DATA[31:28]; data8 <= MODE1_DATA[35:32];data9 <= MODE1_DATA[39:36]; data10 <= MODE1_DATA[43:40];data11 <= MODE1_DATA[47:44]; data12 <= MODE1_DATA[51:48];data13 <= MODE1_DATA[55:52]; data14 <= MODE1_DATA[59:56];data15 <= MODE1_DATA[63:60]; data16 <= MODE1_DATA[67:64];data17 <= MODE1_DATA[71:68]; data18 <= MODE1_DATA[75:72];data19 <= MODE1_DATA[79:76]; data20 <= MODE1_DATA[83:80];data21 <= MODE1_DATA[87:84]; data22 <= MODE1_DATA[91:88];data23 <= MODE1_DATA[95:92]; data24 <= MODE1_DATA[99:96];data25 <= MODE1_DATA[103:100]; data26 <= MODE1_DATA[107:104];data27 <= MODE1_DATA[111:108]; data28 <= MODE1_DATA[115:112];data29 <= MODE1_DATA[119:116]; data30 <= MODE1_DATA[123 :120];data31 <= MODE1_DATA[127:124]; endendelse if( state == WRITE_MODE2 ) beginif(cnt == 16) begincnt <= cnt;wren <= 0;Sbox_ready <= 0;endelse beginwren <= 1;cnt <= cnt +1;endif(wren == 1) beginwraddr <= wraddr +1;data0 <= MODE2_DATA[3:0];data1 <= MODE2_DATA[7:4]; data2 <= MODE2_DATA[11:8];data3 <= MODE2_DATA[15:12]; data4 <= MODE2_DATA[19:16];data5 <= MODE2_DATA[23:20]; data6 <= MODE2_DATA[27:24];data7 <= MODE2_DATA[31:28]; data8 <= MODE2_DATA[35:32];data9 <= MODE2_DATA[39:36]; data10 <= MODE2_DATA[43:40];data11 <= MODE2_DATA[47:44]; data12 <= MODE2_DATA[51:48];data13 <= MODE2_DATA[55:52]; data14 <= MODE2_DATA[59:56];data15 <= MODE2_DATA[63:60]; data16 <= MODE2_DATA[67:64];data17 <= MODE2_DATA[71:68]; data18 <= MODE2_DATA[75:72];data19 <= MODE2_DATA[79:76]; data20 <= MODE2_DATA[83:80];data21 <= MODE2_DATA[87:84]; data22 <= MODE2_DATA[91:88];data23 <= MODE2_DATA[95:92]; data24 <= MODE2_DATA[99:96];data25 <= MODE2_DATA[103:100]; data26 <= MODE2_DATA[107:104];data27 <= MODE2_DATA[111:108]; data28 <= MODE2_DATA[115:112];data29 <= MODE2_DATA[119:116]; data30 <= MODE2_DATA[123 :120];data31 <= MODE2_DATA[127:124]; endendelse if( state == WRITE_MODE3 ) beginif(cnt == 16) begincnt <= cnt;wren <= 0;Sbox_ready <= 0;endelse beginwren <= 1;cnt <= cnt +1;endif(wren == 1) beginwraddr <= wraddr +1;data0 <= MODE3_DATA[3:0];data1 <= MODE3_DATA[7:4]; data2 <= MODE3_DATA[11:8];data3 <= MODE3_DATA[15:12]; data4 <= MODE3_DATA[19:16];data5 <= MODE3_DATA[23:20]; data6 <= MODE3_DATA[27:24];data7 <= MODE3_DATA[31:28]; data8 <= MODE3_DATA[35:32];data9 <= MODE3_DATA[39:36]; data10 <= MODE3_DATA[43:40];data11 <= MODE3_DATA[47:44]; data12 <= MODE3_DATA[51:48];data13 <= MODE3_DATA[55:52]; data14 <= MODE3_DATA[59:56];data15 <= MODE3_DATA[63:60]; data16 <= MODE3_DATA[67:64];data17 <= MODE3_DATA[71:68]; data18 <= MODE3_DATA[75:72];data19 <= MODE3_DATA[79:76]; data20 <= MODE3_DATA[83:80];data21 <= MODE3_DATA[87:84]; data22 <= MODE3_DATA[91:88];data23 <= MODE3_DATA[95:92]; data24 <= MODE3_DATA[99:96];data25 <= MODE3_DATA[103:100]; data26 <= MODE3_DATA[107:104];data27 <= MODE3_DATA[111:108]; data28 <= MODE3_DATA[115:112];data29 <= MODE3_DATA[119:116]; data30 <= MODE3_DATA[123 :120];data31 <= MODE3_DATA[127:124]; endend else if( state == WRITE_MODE4 ) beginif(cnt == 16) begincnt <= cnt;wren <= 0;Sbox_ready <= 0;endelse beginwren <= 1;cnt <= cnt +1;endif(wren == 1) beginwraddr <= wraddr +1;case(wraddr) 4'd0:begin data0 <= MODE4_DATA0[3:0];data1 <= MODE4_DATA0[7:4]; data2 <= MODE4_DATA0[11:8];data3 <= MODE4_DATA0[15:12]; data4 <= MODE4_DATA0[19:16];data5 <= MODE4_DATA0[23:20]; data6 <= MODE4_DATA0[27:24];data7 <= MODE4_DATA0[31:28]; data8 <= MODE4_DATA0[35:32];data9 <= MODE4_DATA0[39:36]; data10 <= MODE4_DATA0[43:40];data11 <= MODE4_DATA0[47:44]; data12 <= MODE4_DATA0[51:48];data13 <= MODE4_DATA0[55:52]; data14 <= MODE4_DATA0[59:56];data15 <= MODE4_DATA0[63:60]; data16 <= MODE4_DATA0[67:64];data17 <= MODE4_DATA0[71:68]; data18 <= MODE4_DATA0[75:72];data19 <= MODE4_DATA0[79:76]; data20 <= MODE4_DATA0[83:80];data21 <= MODE4_DATA0[87:84]; data22 <= MODE4_DATA0[91:88];data23 <= MODE4_DATA0[95:92]; data24 <= MODE4_DATA0[99:96];data25 <= MODE4_DATA0[103:100]; data26 <= MODE4_DATA0[107:104];data27 <= MODE4_DATA0[111:108]; data28 <= MODE4_DATA0[115:112];data29 <= MODE4_DATA0[119:116]; data30 <= MODE4_DATA0[123 :120];data31 <= MODE4_DATA0[127:124]; end4'd1:begin data0 <= MODE4_DATA1[3:0];data1 <= MODE4_DATA1[7:4]; data2 <= MODE4_DATA1[11:8];data3 <= MODE4_DATA1[15:12]; data4 <= MODE4_DATA1[19:16];data5 <= MODE4_DATA1[23:20]; data6 <= MODE4_DATA1[27:24];data7 <= MODE4_DATA1[31:28]; data8 <= MODE4_DATA1[35:32];data9 <= MODE4_DATA1[39:36]; data10 <= MODE4_DATA1[43:40];data11 <= MODE4_DATA1[47:44]; data12 <= MODE4_DATA1[51:48];data13 <= MODE4_DATA1[55:52]; data14 <= MODE4_DATA1[59:56];data15 <= MODE4_DATA1[63:60]; data16 <= MODE4_DATA1[67:64];data17 <= MODE4_DATA1[71:68]; data18 <= MODE4_DATA1[75:72];data19 <= MODE4_DATA1[79:76]; data20 <= MODE4_DATA1[83:80];data21 <= MODE4_DATA1[87:84]; data22 <= MODE4_DATA1[91:88];data23 <= MODE4_DATA1[95:92]; data24 <= MODE4_DATA1[99:96];data25 <= MODE4_DATA1[103:100]; data26 <= MODE4_DATA1[107:104];data27 <= MODE4_DATA1[111:108]; data28 <= MODE4_DATA1[115:112];data29 <= MODE4_DATA1[119:116]; data30 <= MODE4_DATA1[123 :120];data31 <= MODE4_DATA1[127:124]; end4'd2:begin data0 <= MODE4_DATA2[3:0];data1 <= MODE4_DATA2[7:4]; data2 <= MODE4_DATA2[11:8];data3 <= MODE4_DATA2[15:12]; data4 <= MODE4_DATA2[19:16];data5 <= MODE4_DATA2[23:20]; data6 <= MODE4_DATA2[27:24];data7 <= MODE4_DATA2[31:28]; data8 <= MODE4_DATA2[35:32];data9 <= MODE4_DATA2[39:36]; data10 <= MODE4_DATA2[43:40];data11 <= MODE4_DATA2[47:44]; data12 <= MODE4_DATA2[51:48];data13 <= MODE4_DATA2[55:52]; data14 <= MODE4_DATA2[59:56];data15 <= MODE4_DATA2[63:60]; data16 <= MODE4_DATA2[67:64];data17 <= MODE4_DATA2[71:68]; data18 <= MODE4_DATA2[75:72];data19 <= MODE4_DATA2[79:76]; data20 <= MODE4_DATA2[83:80];data21 <= MODE4_DATA2[87:84]; data22 <= MODE4_DATA2[91:88];data23 <= MODE4_DATA2[95:92]; data24 <= MODE4_DATA2[99:96];data25 <= MODE4_DATA2[103:100]; data26 <= MODE4_DATA2[107:104];data27 <= MODE4_DATA2[111:108]; data28 <= MODE4_DATA2[115:112];data29 <= MODE4_DATA2[119:116]; data30 <= MODE4_DATA2[123 :120];data31 <= MODE4_DATA2[127:124]; end4'd3:begin data0 <= MODE4_DATA3[3:0];data1 <= MODE4_DATA3[7:4]; data2 <= MODE4_DATA3[11:8];data3 <= MODE4_DATA3[15:12]; data4 <= MODE4_DATA3[19:16];data5 <= MODE4_DATA3[23:20]; data6 <= MODE4_DATA3[27:24];data7 <= MODE4_DATA3[31:28]; data8 <= MODE4_DATA3[35:32];data9 <= MODE4_DATA3[39:36]; data10 <= MODE4_DATA3[43:40];data11 <= MODE4_DATA3[47:44]; data12 <= MODE4_DATA3[51:48];data13 <= MODE4_DATA3[55:52]; data14 <= MODE4_DATA3[59:56];data15 <= MODE4_DATA3[63:60]; data16 <= MODE4_DATA3[67:64];data17 <= MODE4_DATA3[71:68]; data18 <= MODE4_DATA3[75:72];data19 <= MODE4_DATA3[79:76]; data20 <= MODE4_DATA3[83:80];data21 <= MODE4_DATA3[87:84]; data22 <= MODE4_DATA3[91:88];data23 <= MODE4_DATA3[95:92]; data24 <= MODE4_DATA3[99:96];data25 <= MODE4_DATA3[103:100]; data26 <= MODE4_DATA3[107:104];data27 <= MODE4_DATA3[111:108]; data28 <= MODE4_DATA3[115:112];data29 <= MODE4_DATA3[119:116]; data30 <= MODE4_DATA3[123 :120];data31 <= MODE4_DATA3[127:124]; end 4'd4:begin data0 <= MODE4_DATA4[3:0];data1 <= MODE4_DATA4[7:4]; data2 <= MODE4_DATA4[11:8];data3 <= MODE4_DATA4[15:12]; data4 <= MODE4_DATA4[19:16];data5 <= MODE4_DATA4[23:20]; data6 <= MODE4_DATA4[27:24];data7 <= MODE4_DATA4[31:28]; data8 <= MODE4_DATA4[35:32];data9 <= MODE4_DATA4[39:36]; data10 <= MODE4_DATA4[43:40];data11 <= MODE4_DATA4[47:44]; data12 <= MODE4_DATA4[51:48];data13 <= MODE4_DATA4[55:52]; data14 <= MODE4_DATA4[59:56];data15 <= MODE4_DATA4[63:60]; data16 <= MODE4_DATA4[67:64];data17 <= MODE4_DATA4[71:68]; data18 <= MODE4_DATA4[75:72];data19 <= MODE4_DATA4[79:76]; data20 <= MODE4_DATA4[83:80];data21 <= MODE4_DATA4[87:84]; data22 <= MODE4_DATA4[91:88];data23 <= MODE4_DATA4[95:92]; data24 <= MODE4_DATA4[99:96];data25 <= MODE4_DATA4[103:100]; data26 <= MODE4_DATA4[107:104];data27 <= MODE4_DATA4[111:108]; data28 <= MODE4_DATA4[115:112];data29 <= MODE4_DATA4[119:116]; data30 <= MODE4_DATA4[123 :120];data31 <= MODE4_DATA4[127:124]; end 4'd5:begin data0 <= MODE4_DATA5[3:0];data1 <= MODE4_DATA5[7:4]; data2 <= MODE4_DATA5[11:8];data3 <= MODE4_DATA5[15:12]; data4 <= MODE4_DATA5[19:16];data5 <= MODE4_DATA5[23:20]; data6 <= MODE4_DATA5[27:24];data7 <= MODE4_DATA5[31:28]; data8 <= MODE4_DATA5[35:32];data9 <= MODE4_DATA5[39:36]; data10 <= MODE4_DATA5[43:40];data11 <= MODE4_DATA5[47:44]; data12 <= MODE4_DATA5[51:48];data13 <= MODE4_DATA5[55:52]; data14 <= MODE4_DATA5[59:56];data15 <= MODE4_DATA5[63:60]; data16 <= MODE4_DATA5[67:64];data17 <= MODE4_DATA5[71:68]; data18 <= MODE4_DATA5[75:72];data19 <= MODE4_DATA5[79:76]; data20 <= MODE4_DATA5[83:80];data21 <= MODE4_DATA5[87:84]; data22 <= MODE4_DATA5[91:88];data23 <= MODE4_DATA5[95:92]; data24 <= MODE4_DATA5[99:96];data25 <= MODE4_DATA5[103:100]; data26 <= MODE4_DATA5[107:104];data27 <= MODE4_DATA5[111:108]; data28 <= MODE4_DATA5[115:112];data29 <= MODE4_DATA5[119:116]; data30 <= MODE4_DATA5[123 :120];data31 <= MODE4_DATA5[127:124]; end4'd6:begin data0 <= MODE4_DATA6[3:0];data1 <= MODE4_DATA6[7:4]; data2 <= MODE4_DATA6[11:8];data3 <= MODE4_DATA6[15:12]; data4 <= MODE4_DATA6[19:16];data5 <= MODE4_DATA6[23:20]; data6 <= MODE4_DATA6[27:24];data7 <= MODE4_DATA6[31:28]; data8 <= MODE4_DATA6[35:32];data9 <= MODE4_DATA6[39:36]; data10 <= MODE4_DATA6[43:40];data11 <= MODE4_DATA6[47:44]; data12 <= MODE4_DATA6[51:48];data13 <= MODE4_DATA6[55:52]; data14 <= MODE4_DATA6[59:56];data15 <= MODE4_DATA6[63:60]; data16 <= MODE4_DATA6[67:64];data17 <= MODE4_DATA6[71:68]; data18 <= MODE4_DATA6[75:72];data19 <= MODE4_DATA6[79:76]; data20 <= MODE4_DATA6[83:80];data21 <= MODE4_DATA6[87:84]; data22 <= MODE4_DATA6[91:88];data23 <= MODE4_DATA6[95:92]; data24 <= MODE4_DATA6[99:96];data25 <= MODE4_DATA6[103:100]; data26 <= MODE4_DATA6[107:104];data27 <= MODE4_DATA6[111:108]; data28 <= MODE4_DATA6[115:112];data29 <= MODE4_DATA6[119:116]; data30 <= MODE4_DATA6[123 :120];data31 <= MODE4_DATA6[127:124]; end4'd7:begin data0 <= MODE4_DATA7[3:0];data1 <= MODE4_DATA7[7:4]; data2 <= MODE4_DATA7[11:8];data3 <= MODE4_DATA7[15:12]; data4 <= MODE4_DATA7[19:16];data5 <= MODE4_DATA7[23:20]; data6 <= MODE4_DATA7[27:24];data7 <= MODE4_DATA7[31:28]; data8 <= MODE4_DATA7[35:32];data9 <= MODE4_DATA7[39:36]; data10 <= MODE4_DATA7[43:40];data11 <= MODE4_DATA7[47:44]; data12 <= MODE4_DATA7[51:48];data13 <= MODE4_DATA7[55:52]; data14 <= MODE4_DATA7[59:56];data15 <= MODE4_DATA7[63:60]; data16 <= MODE4_DATA7[67:64];data17 <= MODE4_DATA7[71:68]; data18 <= MODE4_DATA7[75:72];data19 <= MODE4_DATA7[79:76]; data20 <= MODE4_DATA7[83:80];data21 <= MODE4_DATA7[87:84]; data22 <= MODE4_DATA7[91:88];data23 <= MODE4_DATA7[95:92]; data24 <= MODE4_DATA7[99:96];data25 <= MODE4_DATA7[103:100]; data26 <= MODE4_DATA7[107:104];data27 <= MODE4_DATA7[111:108]; data28 <= MODE4_DATA7[115:112];data29 <= MODE4_DATA7[119:116]; data30 <= MODE4_DATA7[123 :120];data31 <= MODE4_DATA7[127:124]; end 4'd8:begin data0 <= MODE4_DATA8[3:0];data1 <= MODE4_DATA8[7:4]; data2 <= MODE4_DATA8[11:8];data3 <= MODE4_DATA8[15:12]; data4 <= MODE4_DATA8[19:16];data5 <= MODE4_DATA8[23:20]; data6 <= MODE4_DATA8[27:24];data7 <= MODE4_DATA8[31:28]; data8 <= MODE4_DATA8[35:32];data9 <= MODE4_DATA8[39:36]; data10 <= MODE4_DATA8[43:40];data11 <= MODE4_DATA8[47:44]; data12 <= MODE4_DATA8[51:48];data13 <= MODE4_DATA8[55:52]; data14 <= MODE4_DATA8[59:56];data15 <= MODE4_DATA8[63:60]; data16 <= MODE4_DATA8[67:64];data17 <= MODE4_DATA8[71:68]; data18 <= MODE4_DATA8[75:72];data19 <= MODE4_DATA8[79:76]; data20 <= MODE4_DATA8[83:80];data21 <= MODE4_DATA8[87:84]; data22 <= MODE4_DATA8[91:88];data23 <= MODE4_DATA8[95:92]; data24 <= MODE4_DATA8[99:96];data25 <= MODE4_DATA8[103:100]; data26 <= MODE4_DATA8[107:104];data27 <= MODE4_DATA8[111:108]; data28 <= MODE4_DATA8[115:112];data29 <= MODE4_DATA8[119:116]; data30 <= MODE4_DATA8[123 :120];data31 <= MODE4_DATA8[127:124]; end4'd9:begin data0 <= MODE4_DATA9[3:0];data1 <= MODE4_DATA9[7:4]; data2 <= MODE4_DATA9[11:8];data3 <= MODE4_DATA9[15:12]; data4 <= MODE4_DATA9[19:16];data5 <= MODE4_DATA9[23:20]; data6 <= MODE4_DATA9[27:24];data7 <= MODE4_DATA9[31:28]; data8 <= MODE4_DATA9[35:32];data9 <= MODE4_DATA9[39:36]; data10 <= MODE4_DATA9[43:40];data11 <= MODE4_DATA9[47:44]; data12 <= MODE4_DATA9[51:48];data13 <= MODE4_DATA9[55:52]; data14 <= MODE4_DATA9[59:56];data15 <= MODE4_DATA9[63:60]; data16 <= MODE4_DATA9[67:64];data17 <= MODE4_DATA9[71:68]; data18 <= MODE4_DATA9[75:72];data19 <= MODE4_DATA9[79:76]; data20 <= MODE4_DATA9[83:80];data21 <= MODE4_DATA9[87:84]; data22 <= MODE4_DATA9[91:88];data23 <= MODE4_DATA9[95:92]; data24 <= MODE4_DATA9[99:96];data25 <= MODE4_DATA9[103:100]; data26 <= MODE4_DATA9[107:104];data27 <= MODE4_DATA9[111:108]; data28 <= MODE4_DATA9[115:112];data29 <= MODE4_DATA9[119:116]; data30 <= MODE4_DATA9[123 :120];data31 <= MODE4_DATA9[127:124]; end4'd10:begin data0 <= MODE4_DATA10[3:0];data1 <= MODE4_DATA10[7:4]; data2 <= MODE4_DATA10[11:8];data3 <= MODE4_DATA10[15:12]; data4 <= MODE4_DATA10[19:16];data5 <= MODE4_DATA10[23:20]; data6 <= MODE4_DATA10[27:24];data7 <= MODE4_DATA10[31:28]; data8 <= MODE4_DATA10[35:32];data9 <= MODE4_DATA10[39:36]; data10 <= MODE4_DATA10[43:40];data11 <= MODE4_DATA10[47:44]; data12 <= MODE4_DATA10[51:48];data13 <= MODE4_DATA10[55:52]; data14 <= MODE4_DATA10[59:56];data15 <= MODE4_DATA10[63:60]; data16 <= MODE4_DATA10[67:64];data17 <= MODE4_DATA10[71:68]; data18 <= MODE4_DATA10[75:72];data19 <= MODE4_DATA10[79:76]; data20 <= MODE4_DATA10[83:80];data21 <= MODE4_DATA10[87:84]; data22 <= MODE4_DATA10[91:88];data23 <= MODE4_DATA10[95:92]; data24 <= MODE4_DATA10[99:96];data25 <= MODE4_DATA10[103:100]; data26 <= MODE4_DATA10[107:104];data27 <= MODE4_DATA10[111:108]; data28 <= MODE4_DATA10[115:112];data29 <= MODE4_DATA10[119:116]; data30 <= MODE4_DATA10[123 :120];data31 <= MODE4_DATA10[127:124]; end4'd11:begin data0 <= MODE4_DATA11[3:0];data1 <= MODE4_DATA11[7:4]; data2 <= MODE4_DATA11[11:8];data3 <= MODE4_DATA11[15:12]; data4 <= MODE4_DATA11[19:16];data5 <= MODE4_DATA11[23:20]; data6 <= MODE4_DATA11[27:24];data7 <= MODE4_DATA11[31:28]; data8 <= MODE4_DATA11[35:32];data9 <= MODE4_DATA11[39:36]; data10 <= MODE4_DATA11[43:40];data11 <= MODE4_DATA11[47:44]; data12 <= MODE4_DATA11[51:48];data13 <= MODE4_DATA11[55:52]; data14 <= MODE4_DATA11[59:56];data15 <= MODE4_DATA11[63:60]; data16 <= MODE4_DATA11[67:64];data17 <= MODE4_DATA11[71:68]; data18 <= MODE4_DATA11[75:72];data19 <= MODE4_DATA11[79:76]; data20 <= MODE4_DATA11[83:80];data21 <= MODE4_DATA11[87:84]; data22 <= MODE4_DATA11[91:88];data23 <= MODE4_DATA11[95:92]; data24 <= MODE4_DATA11[99:96];data25 <= MODE4_DATA11[103:100]; data26 <= MODE4_DATA11[107:104];data27 <= MODE4_DATA11[111:108]; data28 <= MODE4_DATA11[115:112];data29 <= MODE4_DATA11[119:116]; data30 <= MODE4_DATA11[123 :120];data31 <= MODE4_DATA11[127:124]; end4'd12:begin data0 <= MODE4_DATA12[3:0];data1 <= MODE4_DATA12[7:4]; data2 <= MODE4_DATA12[11:8];data3 <= MODE4_DATA12[15:12]; data4 <= MODE4_DATA12[19:16];data5 <= MODE4_DATA12[23:20]; data6 <= MODE4_DATA12[27:24];data7 <= MODE4_DATA12[31:28]; data8 <= MODE4_DATA12[35:32];data9 <= MODE4_DATA12[39:36]; data10 <= MODE4_DATA12[43:40];data11 <= MODE4_DATA12[47:44]; data12 <= MODE4_DATA12[51:48];data13 <= MODE4_DATA12[55:52]; data14 <= MODE4_DATA12[59:56];data15 <= MODE4_DATA12[63:60]; data16 <= MODE4_DATA12[67:64];data17 <= MODE4_DATA12[71:68]; data18 <= MODE4_DATA12[75:72];data19 <= MODE4_DATA12[79:76]; data20 <= MODE4_DATA12[83:80];data21 <= MODE4_DATA12[87:84]; data22 <= MODE4_DATA12[91:88];data23 <= MODE4_DATA12[95:92]; data24 <= MODE4_DATA12[99:96];data25 <= MODE4_DATA12[103:100]; data26 <= MODE4_DATA12[107:104];data27 <= MODE4_DATA12[111:108]; data28 <= MODE4_DATA12[115:112];data29 <= MODE4_DATA12[119:116]; data30 <= MODE4_DATA12[123 :120];data31 <= MODE4_DATA12[127:124]; end4'd13:begin data0 <= MODE4_DATA13[3:0];data1 <= MODE4_DATA13[7:4]; data2 <= MODE4_DATA13[11:8];data3 <= MODE4_DATA13[15:12]; data4 <= MODE4_DATA13[19:16];data5 <= MODE4_DATA13[23:20]; data6 <= MODE4_DATA13[27:24];data7 <= MODE4_DATA13[31:28]; data8 <= MODE4_DATA13[35:32];data9 <= MODE4_DATA13[39:36]; data10 <= MODE4_DATA13[43:40];data11 <= MODE4_DATA13[47:44]; data12 <= MODE4_DATA13[51:48];data13 <= MODE4_DATA13[55:52]; data14 <= MODE4_DATA13[59:56];data15 <= MODE4_DATA13[63:60]; data16 <= MODE4_DATA13[67:64];data17 <= MODE4_DATA13[71:68]; data18 <= MODE4_DATA13[75:72];data19 <= MODE4_DATA13[79:76]; data20 <= MODE4_DATA13[83:80];data21 <= MODE4_DATA13[87:84]; data22 <= MODE4_DATA13[91:88];data23 <= MODE4_DATA13[95:92]; data24 <= MODE4_DATA13[99:96];data25 <= MODE4_DATA13[103:100]; data26 <= MODE4_DATA13[107:104];data27 <= MODE4_DATA13[111:108]; data28 <= MODE4_DATA13[115:112];data29 <= MODE4_DATA13[119:116]; data30 <= MODE4_DATA13[123 :120];data31 <= MODE4_DATA13[127:124]; end4'd14:begin data0 <= MODE4_DATA14[3:0];data1 <= MODE4_DATA14[7:4]; data2 <= MODE4_DATA14[11:8];data3 <= MODE4_DATA14[15:12]; data4 <= MODE4_DATA14[19:16];data5 <= MODE4_DATA14[23:20]; data6 <= MODE4_DATA14[27:24];data7 <= MODE4_DATA14[31:28]; data8 <= MODE4_DATA14[35:32];data9 <= MODE4_DATA14[39:36]; data10 <= MODE4_DATA14[43:40];data11 <= MODE4_DATA14[47:44]; data12 <= MODE4_DATA14[51:48];data13 <= MODE4_DATA14[55:52]; data14 <= MODE4_DATA14[59:56];data15 <= MODE4_DATA14[63:60]; data16 <= MODE4_DATA14[67:64];data17 <= MODE4_DATA14[71:68]; data18 <= MODE4_DATA14[75:72];data19 <= MODE4_DATA14[79:76]; data20 <= MODE4_DATA14[83:80];data21 <= MODE4_DATA14[87:84]; data22 <= MODE4_DATA14[91:88];data23 <= MODE4_DATA14[95:92]; data24 <= MODE4_DATA14[99:96];data25 <= MODE4_DATA14[103:100]; data26 <= MODE4_DATA14[107:104];data27 <= MODE4_DATA14[111:108]; data28 <= MODE4_DATA14[115:112];data29 <= MODE4_DATA14[119:116]; data30 <= MODE4_DATA14[123 :120];data31 <= MODE4_DATA14[127:124]; end 4'd15:begin data0 <= MODE4_DATA15[3:0];data1 <= MODE4_DATA15[7:4]; data2 <= MODE4_DATA15[11:8];data3 <= MODE4_DATA15[15:12]; data4 <= MODE4_DATA15[19:16];data5 <= MODE4_DATA15[23:20]; data6 <= MODE4_DATA15[27:24];data7 <= MODE4_DATA15[31:28]; data8 <= MODE4_DATA15[35:32];data9 <= MODE4_DATA15[39:36]; data10 <= MODE4_DATA15[43:40];data11 <= MODE4_DATA15[47:44]; data12 <= MODE4_DATA15[51:48];data13 <= MODE4_DATA15[55:52]; data14 <= MODE4_DATA15[59:56];data15 <= MODE4_DATA15[63:60]; data16 <= MODE4_DATA15[67:64];data17 <= MODE4_DATA15[71:68]; data18 <= MODE4_DATA15[75:72];data19 <= MODE4_DATA15[79:76]; data20 <= MODE4_DATA15[83:80];data21 <= MODE4_DATA15[87:84]; data22 <= MODE4_DATA15[91:88];data23 <= MODE4_DATA15[95:92]; data24 <= MODE4_DATA15[99:96];data25 <= MODE4_DATA15[103:100]; data26 <= MODE4_DATA15[107:104];data27 <= MODE4_DATA15[111:108]; data28 <= MODE4_DATA15[115:112];data29 <= MODE4_DATA15[119:116]; data30 <= MODE4_DATA15[123 :120];data31 <= MODE4_DATA15[127:124]; end endcaseendend else begincnt <=0;data1 <= 0;data1 <=0; data2 <=0;data3 <=0; data4 <=0;data5 <=0; data6 <=0;data7 <=0; data8 <=0;data9 <=0; data10 <=0;data11 <=0; data12 <=0;data13 <=0; data14 <=0;data15 <=0; data16 <=0;data17 <=0; data18 <=0;data19 <=0; data20 <=0;data21 <=0; data22 <=0;data23 <=0; data24 <=0;data25 <=0; data26 <=0;data27 <=0; data28 <=0;data29 <=0; data30 <=0;data31 <=0; wraddr <= 0;wren <= 0; endendendendmodule
2.2 双端口RAM的调用
2.3 顶层模块
module test_s_box(input clk,input rst_n,input[3:0] Sbox_4_addr0,input[3:0] Sbox_4_addr1, input[3:0] Sbox_4_addr2,input[3:0] Sbox_4_addr3,input[3:0] Sbox_4_addr4,input[3:0] Sbox_4_addr5,input[3:0] Sbox_4_addr6, input[3:0] Sbox_4_addr7,input[3:0] Sbox_4_addr8,input[3:0] Sbox_4_addr9,input[3:0] Sbox_4_addr10,input[3:0] Sbox_4_addr11, input[3:0] Sbox_4_addr12,input[3:0] Sbox_4_addr13,input[3:0] Sbox_4_addr14,input[3:0] Sbox_4_addr15,input[3:0] Sbox_4_addr16, input[3:0] Sbox_4_addr17,input[3:0] Sbox_4_addr18,input[3:0] Sbox_4_addr19,input[3:0] Sbox_4_addr20,input[3:0] Sbox_4_addr21, input[3:0] Sbox_4_addr22,input[3:0] Sbox_4_addr23,input[3:0] Sbox_4_addr24,input[3:0] Sbox_4_addr25,input[3:0] Sbox_4_addr26, input[3:0] Sbox_4_addr27,input[3:0] Sbox_4_addr28,input[3:0] Sbox_4_addr29, input[3:0] Sbox_4_addr30,input[3:0] Sbox_4_addr31, input[7:0] Sbox_8_addr, input Sbox_8_en,input[1:0] Sbox_mode, // 4 input Sbox_write_en,//input Sbox_read_en,output Sbox_ready,output reg[7:0] Sbox_8_Dout, output[127:0] Sbox_4_Dout );wire[3:0] data0 ;
wire[3:0] data1 ;
wire[3:0] data2 ;
wire[3:0] data3 ;
wire[3:0] data4 ;
wire[3:0] data5 ;
wire[3:0] data6 ;
wire[3:0] data7 ;
wire[3:0] data8 ;
wire[3:0] data9 ;
wire[3:0] data10;
wire[3:0] data11;
wire[3:0] data12;
wire[3:0] data13;
wire[3:0] data14;
wire[3:0] data15;
wire[3:0] data16;
wire[3:0] data17;
wire[3:0] data18;
wire[3:0] data19;
wire[3:0] data20;
wire[3:0] data21;
wire[3:0] data22;
wire[3:0] data23;
wire[3:0] data24;
wire[3:0] data25;
wire[3:0] data26;
wire[3:0] data27;
wire[3:0] data28;
wire[3:0] data29;
wire[3:0] data30;
wire[3:0] data31;wire[3:0] wraddr;
wire wren;wire[3:0] q_out0 ;
wire[3:0] q_out1 ;
wire[3:0] q_out2 ;
wire[3:0] q_out3 ;
wire[3:0] q_out4 ;
wire[3:0] q_out5 ;
wire[3:0] q_out6 ;
wire[3:0] q_out7 ;
wire[3:0] q_out8 ;
wire[3:0] q_out9 ;
wire[3:0] q_out10;
wire[3:0] q_out11;
wire[3:0] q_out12;
wire[3:0] q_out13;
wire[3:0] q_out14;
wire[3:0] q_out15;
wire[3:0] q_out16;
wire[3:0] q_out17;
wire[3:0] q_out18;
wire[3:0] q_out19;
wire[3:0] q_out20;
wire[3:0] q_out21;
wire[3:0] q_out22;
wire[3:0] q_out23;
wire[3:0] q_out24;
wire[3:0] q_out25;
wire[3:0] q_out26;
wire[3:0] q_out27;
wire[3:0] q_out28;
wire[3:0] q_out29;
wire[3:0] q_out30;
wire[3:0] q_out31;wire[7:0] S_box_D0 ;
wire[7:0] S_box_D1 ;
wire[7:0] S_box_D2 ;
wire[7:0] S_box_D3 ;
wire[7:0] S_box_D4 ;
wire[7:0] S_box_D5 ;
wire[7:0] S_box_D6 ;
wire[7:0] S_box_D7 ;
wire[7:0] S_box_D8 ;
wire[7:0] S_box_D9 ;
wire[7:0] S_box_D10;
wire[7:0] S_box_D11;
wire[7:0] S_box_D12;
wire[7:0] S_box_D13;
wire[7:0] S_box_D14;
wire[7:0] S_box_D15;wire[3:0] ADDR0 ;
wire[3:0] ADDR1 ;
wire[3:0] ADDR2 ;
wire[3:0] ADDR3 ;
wire[3:0] ADDR4 ;
wire[3:0] ADDR5 ;
wire[3:0] ADDR6 ;
wire[3:0] ADDR7 ;
wire[3:0] ADDR8 ;
wire[3:0] ADDR9 ;
wire[3:0] ADDR10;
wire[3:0] ADDR11;
wire[3:0] ADDR12;
wire[3:0] ADDR13;
wire[3:0] ADDR14;
wire[3:0] ADDR15;
wire[3:0] ADDR16;
wire[3:0] ADDR17;
wire[3:0] ADDR18;
wire[3:0] ADDR19;
wire[3:0] ADDR20;
wire[3:0] ADDR21;
wire[3:0] ADDR22;
wire[3:0] ADDR23;
wire[3:0] ADDR24;
wire[3:0] ADDR25;
wire[3:0] ADDR26;
wire[3:0] ADDR27;
wire[3:0] ADDR28;
wire[3:0] ADDR29;
wire[3:0] ADDR30;
wire[3:0] ADDR31;assign S_box_D0 = {q_out1 ,q_out0 };assign S_box_D1 = {q_out3 ,q_out2 };assign S_box_D2 = {q_out5 ,q_out4 };assign S_box_D3 = {q_out7 ,q_out6 };assign S_box_D4 = {q_out9 ,q_out8 };assign S_box_D5 = {q_out11,q_out10};assign S_box_D6 = {q_out13,q_out12};assign S_box_D7 = {q_out15,q_out14};assign S_box_D8 = {q_out17,q_out16};assign S_box_D9 = {q_out19,q_out18};assign S_box_D10 = {q_out21,q_out20};assign S_box_D11 = {q_out23,q_out22};assign S_box_D12 = {q_out25,q_out24};assign S_box_D13 = {q_out27,q_out26};assign S_box_D14 = {q_out29,q_out28};assign S_box_D15 = {q_out31,q_out30};assign ADDR0 = Sbox_8_en ? Sbox_8_addr[3:0] : Sbox_4_addr0 ;assign ADDR1 = Sbox_8_en ? Sbox_8_addr[3:0] : Sbox_4_addr1 ;assign ADDR2 = Sbox_8_en ? Sbox_8_addr[3:0] : Sbox_4_addr2 ;assign ADDR3 = Sbox_8_en ? Sbox_8_addr[3:0] : Sbox_4_addr3 ;assign ADDR4 = Sbox_8_en ? Sbox_8_addr[3:0] : Sbox_4_addr4 ;assign ADDR5 = Sbox_8_en ? Sbox_8_addr[3:0] : Sbox_4_addr5 ;assign ADDR6 = Sbox_8_en ? Sbox_8_addr[3:0] : Sbox_4_addr6 ;assign ADDR7 = Sbox_8_en ? Sbox_8_addr[3:0] : Sbox_4_addr7 ;assign ADDR8 = Sbox_8_en ? Sbox_8_addr[3:0] : Sbox_4_addr8 ;assign ADDR9 = Sbox_8_en ? Sbox_8_addr[3:0] : Sbox_4_addr9 ;assign ADDR10 = Sbox_8_en ? Sbox_8_addr[3:0] : Sbox_4_addr10;assign ADDR11 = Sbox_8_en ? Sbox_8_addr[3:0] : Sbox_4_addr11;assign ADDR12 = Sbox_8_en ? Sbox_8_addr[3:0] : Sbox_4_addr12;assign ADDR13 = Sbox_8_en ? Sbox_8_addr[3:0] : Sbox_4_addr13;assign ADDR14 = Sbox_8_en ? Sbox_8_addr[3:0] : Sbox_4_addr14;assign ADDR15 = Sbox_8_en ? Sbox_8_addr[3:0] : Sbox_4_addr15;assign ADDR16 = Sbox_8_en ? Sbox_8_addr[3:0] : Sbox_4_addr16;assign ADDR17 = Sbox_8_en ? Sbox_8_addr[3:0] : Sbox_4_addr17;assign ADDR18 = Sbox_8_en ? Sbox_8_addr[3:0] : Sbox_4_addr18;assign ADDR19 = Sbox_8_en ? Sbox_8_addr[3:0] : Sbox_4_addr19;assign ADDR20 = Sbox_8_en ? Sbox_8_addr[3:0] : Sbox_4_addr20;assign ADDR21 = Sbox_8_en ? Sbox_8_addr[3:0] : Sbox_4_addr21;assign ADDR22 = Sbox_8_en ? Sbox_8_addr[3:0] : Sbox_4_addr22;assign ADDR23 = Sbox_8_en ? Sbox_8_addr[3:0] : Sbox_4_addr23;assign ADDR24 = Sbox_8_en ? Sbox_8_addr[3:0] : Sbox_4_addr24;assign ADDR25 = Sbox_8_en ? Sbox_8_addr[3:0] : Sbox_4_addr25;assign ADDR26 = Sbox_8_en ? Sbox_8_addr[3:0] : Sbox_4_addr26;assign ADDR27 = Sbox_8_en ? Sbox_8_addr[3:0] : Sbox_4_addr27;assign ADDR28 = Sbox_8_en ? Sbox_8_addr[3:0] : Sbox_4_addr28;assign ADDR29 = Sbox_8_en ? Sbox_8_addr[3:0] : Sbox_4_addr29;assign ADDR30 = Sbox_8_en ? Sbox_8_addr[3:0] : Sbox_4_addr30;assign ADDR31 = Sbox_8_en ? Sbox_8_addr[3:0] : Sbox_4_addr31; //RAM INSTassign Sbox_4_Dout = {q_out31,q_out30,q_out29,q_out28,q_out27,q_out26,q_out25,q_out24,q_out23,q_out22,q_out21,q_out20,q_out19,q_out18,q_out17,q_out16,q_out15,q_out14,q_out13,q_out12,q_out11,q_out10,q_out9,q_out8,q_out7,q_out6,q_out5,q_out4,q_out3,q_out2,q_out1,q_out0};always@(*)
begincase(Sbox_8_addr[7:4])0: Sbox_8_Dout <= S_box_D0 ;1: Sbox_8_Dout <= S_box_D1 ;2: Sbox_8_Dout <= S_box_D2 ;3: Sbox_8_Dout <= S_box_D3 ;4: Sbox_8_Dout <= S_box_D4 ;5: Sbox_8_Dout <= S_box_D5 ;6: Sbox_8_Dout <= S_box_D6 ;7: Sbox_8_Dout <= S_box_D7 ; 8: Sbox_8_Dout <= S_box_D8 ;9: Sbox_8_Dout <= S_box_D9 ;10: Sbox_8_Dout <= S_box_D10;11: Sbox_8_Dout <= S_box_D11;12: Sbox_8_Dout <= S_box_D12;13: Sbox_8_Dout <= S_box_D13;14: Sbox_8_Dout <= S_box_D14;15: Sbox_8_Dout <= S_box_D15; endcaseendwrite_data write_data(.clk(clk),.rst_n(rst_n),.Sbox_mode(Sbox_mode),.Sbox_write_en(Sbox_write_en),.Sbox_ready(Sbox_ready),.data0 (data0 ),.data1 (data1 ),.data2 (data2 ),.data3 (data3 ),.data4 (data4 ),.data5 (data5 ),.data6 (data6 ),.data7 (data7 ),.data8 (data8 ),.data9 (data9 ),.data10(data10),.data11(data11),.data12(data12),.data13(data13),.data14(data14),.data15(data15),.data16(data16),.data17(data17),.data18(data18),.data19(data19),.data20(data20),.data21(data21),.data22(data22),.data23(data23),.data24(data24),.data25(data25),.data26(data26),.data27(data27),.data28(data28),.data29(data29),.data30(data30),.data31(data31),.wraddr(wraddr),.wren(wren)
);reg[3:0] wraddr_reg;always@( posedge clk or negedge rst_n)
beginif( ! rst_n ) wraddr_reg <= 0;elsewraddr_reg <= wraddr ;end fifo_ram#(
.USER_BLOCK("TRUE"),
.ADDR_WIDTH(4),
.BASE_WIDTH(4)
) fifo_ram_inst0
(
.wr_clk (clk ),
.wr_rst (!rst_n ),
.wr_addr (wraddr_reg ),
.data_in (data0 ),
.wr_en (wren ),
.rd_clk (clk ),
.rd_rst (!rst_n ),
.rd_addr (ADDR0 ),
.data_out (q_out0),
.rd_en (1'b1 ));fifo_ram#(
.USER_BLOCK("TRUE"),
.ADDR_WIDTH(4),
.BASE_WIDTH(4)
) fifo_ram_inst1
(
.wr_clk (clk ),
.wr_rst (!rst_n ),
.wr_addr (wraddr_reg ),
.data_in (data1 ),
.wr_en (wren ),
.rd_clk (clk ),
.rd_rst (!rst_n ),
.rd_addr (ADDR1 ),
.data_out (q_out1),
.rd_en (1'b1 ));fifo_ram#(
.USER_BLOCK("TRUE"),
.ADDR_WIDTH(4),
.BASE_WIDTH(4)
) fifo_ram_inst2
(
.wr_clk (clk ),
.wr_rst (!rst_n ),
.wr_addr (wraddr_reg ),
.data_in (data2 ),
.wr_en (wren ),
.rd_clk (clk ),
.rd_rst (!rst_n ),
.rd_addr (ADDR2 ),
.data_out (q_out2),
.rd_en (1'b1 ));fifo_ram#(
.USER_BLOCK("TRUE"),
.ADDR_WIDTH(4),
.BASE_WIDTH(4)
) fifo_ram_inst3
(
.wr_clk (clk ),
.wr_rst (!rst_n ),
.wr_addr (wraddr_reg ),
.data_in (data3 ),
.wr_en (wren ),
.rd_clk (clk ),
.rd_rst (!rst_n ),
.rd_addr (ADDR3 ),
.data_out (q_out3),
.rd_en (1'b1 ));fifo_ram#(
.USER_BLOCK("TRUE"),
.ADDR_WIDTH(4),
.BASE_WIDTH(4)
) fifo_ram_inst4
(
.wr_clk (clk ),
.wr_rst (!rst_n ),
.wr_addr (wraddr_reg ),
.data_in (data4 ),
.wr_en (wren ),
.rd_clk (clk ),
.rd_rst (!rst_n ),
.rd_addr (ADDR4 ),
.data_out (q_out4),
.rd_en (1'b1 ));fifo_ram#(
.USER_BLOCK("TRUE"),
.ADDR_WIDTH(4),
.BASE_WIDTH(4)
) fifo_ram_inst5
(
.wr_clk (clk ),
.wr_rst (!rst_n ),
.wr_addr (wraddr_reg ),
.data_in (data5 ),
.wr_en (wren ),
.rd_clk (clk ),
.rd_rst (!rst_n ),
.rd_addr (ADDR5 ),
.data_out (q_out5),
.rd_en (1'b1 ));fifo_ram#(
.USER_BLOCK("TRUE"),
.ADDR_WIDTH(4),
.BASE_WIDTH(4)
) fifo_ram_inst6
(
.wr_clk (clk ),
.wr_rst (!rst_n ),
.wr_addr (wraddr_reg ),
.data_in (data6 ),
.wr_en (wren ),
.rd_clk (clk ),
.rd_rst (!rst_n ),
.rd_addr (ADDR6 ),
.data_out (q_out6),
.rd_en (1'b1 ));fifo_ram#(
.USER_BLOCK("TRUE"),
.ADDR_WIDTH(4),
.BASE_WIDTH(4)
) fifo_ram_inst7
(
.wr_clk (clk ),
.wr_rst (!rst_n ),
.wr_addr (wraddr_reg ),
.data_in (data7 ),
.wr_en (wren ),
.rd_clk (clk ),
.rd_rst (!rst_n ),
.rd_addr (ADDR7 ),
.data_out (q_out7),
.rd_en (1'b1 ));fifo_ram#(
.USER_BLOCK("TRUE"),
.ADDR_WIDTH(4),
.BASE_WIDTH(4)
) fifo_ram_inst8
(
.wr_clk (clk ),
.wr_rst (!rst_n ),
.wr_addr (wraddr_reg ),
.data_in (data8 ),
.wr_en (wren ),
.rd_clk (clk ),
.rd_rst (!rst_n ),
.rd_addr (ADDR8 ),
.data_out (q_out8),
.rd_en (1'b1 ));fifo_ram#(
.USER_BLOCK("TRUE"),
.ADDR_WIDTH(4),
.BASE_WIDTH(4)
) fifo_ram_inst9
(
.wr_clk (clk ),
.wr_rst (!rst_n ),
.wr_addr (wraddr_reg ),
.data_in (data9 ),
.wr_en (wren ),
.rd_clk (clk ),
.rd_rst (!rst_n ),
.rd_addr (ADDR9 ),
.data_out (q_out9),
.rd_en (1'b1 ));fifo_ram#(
.USER_BLOCK("TRUE"),
.ADDR_WIDTH(4),
.BASE_WIDTH(4)
) fifo_ram_inst10
(
.wr_clk (clk ),
.wr_rst (!rst_n ),
.wr_addr (wraddr_reg ),
.data_in (data10 ),
.wr_en (wren ),
.rd_clk (clk ),
.rd_rst (!rst_n ),
.rd_addr (ADDR10 ),
.data_out (q_out10),
.rd_en (1'b1 ));fifo_ram#(
.USER_BLOCK("TRUE"),
.ADDR_WIDTH(4),
.BASE_WIDTH(4)
) fifo_ram_inst11
(
.wr_clk (clk ),
.wr_rst (!rst_n ),
.wr_addr (wraddr_reg ),
.data_in (data11 ),
.wr_en (wren ),
.rd_clk (clk ),
.rd_rst (!rst_n ),
.rd_addr (ADDR11 ),
.data_out (q_out11),
.rd_en (1'b1 ));fifo_ram#(
.USER_BLOCK("TRUE"),
.ADDR_WIDTH(4),
.BASE_WIDTH(4)
) fifo_ram_inst12
(
.wr_clk (clk ),
.wr_rst (!rst_n ),
.wr_addr (wraddr_reg ),
.data_in (data12 ),
.wr_en (wren ),
.rd_clk (clk ),
.rd_rst (!rst_n ),
.rd_addr (ADDR12 ),
.data_out (q_out12),
.rd_en (1'b1 ));fifo_ram#(
.USER_BLOCK("TRUE"),
.ADDR_WIDTH(4),
.BASE_WIDTH(4)
) fifo_ram_inst13
(
.wr_clk (clk ),
.wr_rst (!rst_n ),
.wr_addr (wraddr_reg ),
.data_in (data13 ),
.wr_en (wren ),
.rd_clk (clk ),
.rd_rst (!rst_n ),
.rd_addr (ADDR13 ),
.data_out (q_out13),
.rd_en (1'b1 ));fifo_ram#(
.USER_BLOCK("TRUE"),
.ADDR_WIDTH(4),
.BASE_WIDTH(4)
) fifo_ram_inst14
(
.wr_clk (clk ),
.wr_rst (!rst_n ),
.wr_addr (wraddr_reg ),
.data_in (data14 ),
.wr_en (wren ),
.rd_clk (clk ),
.rd_rst (!rst_n ),
.rd_addr (ADDR14 ),
.data_out (q_out14),
.rd_en (1'b1 ));fifo_ram#(
.USER_BLOCK("TRUE"),
.ADDR_WIDTH(4),
.BASE_WIDTH(4)
) fifo_ram_inst15
(
.wr_clk (clk ),
.wr_rst (!rst_n ),
.wr_addr (wraddr_reg ),
.data_in (data15 ),
.wr_en (wren ),
.rd_clk (clk ),
.rd_rst (!rst_n ),
.rd_addr (ADDR15 ),
.data_out (q_out15),
.rd_en (1'b1 ));fifo_ram#(
.USER_BLOCK("TRUE"),
.ADDR_WIDTH(4),
.BASE_WIDTH(4)
) fifo_ram_inst16
(
.wr_clk (clk ),
.wr_rst (!rst_n ),
.wr_addr (wraddr_reg ),
.data_in (data16 ),
.wr_en (wren ),
.rd_clk (clk ),
.rd_rst (!rst_n ),
.rd_addr (ADDR16 ),
.data_out (q_out16),
.rd_en (1'b1 ));fifo_ram#(
.USER_BLOCK("TRUE"),
.ADDR_WIDTH(4),
.BASE_WIDTH(4)
) fifo_ram_inst17
(
.wr_clk (clk ),
.wr_rst (!rst_n ),
.wr_addr (wraddr_reg ),
.data_in (data17 ),
.wr_en (wren ),
.rd_clk (clk ),
.rd_rst (!rst_n ),
.rd_addr (ADDR17 ),
.data_out (q_out17),
.rd_en (1'b1 ));fifo_ram#(
.USER_BLOCK("TRUE"),
.ADDR_WIDTH(4),
.BASE_WIDTH(4)
) fifo_ram_inst18
(
.wr_clk (clk ),
.wr_rst (!rst_n ),
.wr_addr (wraddr_reg ),
.data_in (data18 ),
.wr_en (wren ),
.rd_clk (clk ),
.rd_rst (!rst_n ),
.rd_addr (ADDR18 ),
.data_out (q_out18),
.rd_en (1'b1 ));fifo_ram#(
.USER_BLOCK("TRUE"),
.ADDR_WIDTH(4),
.BASE_WIDTH(4)
) fifo_ram_inst19
(
.wr_clk (clk ),
.wr_rst (!rst_n ),
.wr_addr (wraddr_reg ),
.data_in (data19 ),
.wr_en (wren ),
.rd_clk (clk ),
.rd_rst (!rst_n ),
.rd_addr (ADDR19 ),
.data_out (q_out19),
.rd_en (1'b1 ));fifo_ram#(
.USER_BLOCK("TRUE"),
.ADDR_WIDTH(4),
.BASE_WIDTH(4)
) fifo_ram_inst20
(
.wr_clk (clk ),
.wr_rst (!rst_n ),
.wr_addr (wraddr_reg ),
.data_in (data20 ),
.wr_en (wren ),
.rd_clk (clk ),
.rd_rst (!rst_n ),
.rd_addr (ADDR20 ),
.data_out (q_out20),
.rd_en (1'b1 ));fifo_ram#(
.USER_BLOCK("TRUE"),
.ADDR_WIDTH(4),
.BASE_WIDTH(4)
) fifo_ram_inst21
(
.wr_clk (clk ),
.wr_rst (!rst_n ),
.wr_addr (wraddr_reg ),
.data_in (data21),
.wr_en (wren ),
.rd_clk (clk ),
.rd_rst (!rst_n ),
.rd_addr (ADDR21),
.data_out (q_out21),
.rd_en (1'b1 ));fifo_ram#(
.USER_BLOCK("TRUE"),
.ADDR_WIDTH(4),
.BASE_WIDTH(4)
) fifo_ram_inst22
(
.wr_clk (clk ),
.wr_rst (!rst_n ),
.wr_addr (wraddr_reg ),
.data_in (data22 ),
.wr_en (wren ),
.rd_clk (clk ),
.rd_rst (!rst_n ),
.rd_addr (ADDR22 ),
.data_out (q_out22),
.rd_en (1'b1 ));fifo_ram#(
.USER_BLOCK("TRUE"),
.ADDR_WIDTH(4),
.BASE_WIDTH(4)
) fifo_ram_inst23
(
.wr_clk (clk ),
.wr_rst (!rst_n ),
.wr_addr (wraddr_reg ),
.data_in (data23 ),
.wr_en (wren ),
.rd_clk (clk ),
.rd_rst (!rst_n ),
.rd_addr (ADDR23 ),
.data_out (q_out23),
.rd_en (1'b1 ));fifo_ram#(
.USER_BLOCK("TRUE"),
.ADDR_WIDTH(4),
.BASE_WIDTH(4)
) fifo_ram_inst24
(
.wr_clk (clk ),
.wr_rst (!rst_n ),
.wr_addr (wraddr_reg ),
.data_in (data24 ),
.wr_en (wren ),
.rd_clk (clk ),
.rd_rst (!rst_n ),
.rd_addr (ADDR24 ),
.data_out (q_out24),
.rd_en (1'b1 ));fifo_ram#(
.USER_BLOCK("TRUE"),
.ADDR_WIDTH(4),
.BASE_WIDTH(4)
) fifo_ram_inst25
(
.wr_clk (clk ),
.wr_rst (!rst_n ),
.wr_addr (wraddr_reg ),
.data_in (data25 ),
.wr_en (wren ),
.rd_clk (clk ),
.rd_rst (!rst_n ),
.rd_addr (ADDR25),
.data_out (q_out25),
.rd_en (1'b1 ));fifo_ram#(
.USER_BLOCK("TRUE"),
.ADDR_WIDTH(4),
.BASE_WIDTH(4)
) fifo_ram_inst26
(
.wr_clk (clk ),
.wr_rst (!rst_n ),
.wr_addr (wraddr_reg ),
.data_in (data26),
.wr_en (wren ),
.rd_clk (clk ),
.rd_rst (!rst_n ),
.rd_addr (ADDR26 ),
.data_out (q_out26),
.rd_en (1'b1 ));fifo_ram#(
.USER_BLOCK("TRUE"),
.ADDR_WIDTH(4),
.BASE_WIDTH(4)
) fifo_ram_inst27
(
.wr_clk (clk ),
.wr_rst (!rst_n ),
.wr_addr (wraddr_reg ),
.data_in (data27 ),
.wr_en (wren ),
.rd_clk (clk ),
.rd_rst (!rst_n ),
.rd_addr (ADDR27 ),
.data_out (q_out27),
.rd_en (1'b1 ));fifo_ram#(
.USER_BLOCK("TRUE"),
.ADDR_WIDTH(4),
.BASE_WIDTH(4)
) fifo_ram_inst28
(
.wr_clk (clk ),
.wr_rst (!rst_n ),
.wr_addr (wraddr_reg ),
.data_in (data28 ),
.wr_en (wren ),
.rd_clk (clk ),
.rd_rst (!rst_n ),
.rd_addr (ADDR28 ),
.data_out (q_out28),
.rd_en (1'b1 ));fifo_ram#(
.USER_BLOCK("TRUE"),
.ADDR_WIDTH(4),
.BASE_WIDTH(4)
) fifo_ram_inst29
(
.wr_clk (clk ),
.wr_rst (!rst_n ),
.wr_addr (wraddr_reg ),
.data_in (data29 ),
.wr_en (wren ),
.rd_clk (clk ),
.rd_rst (!rst_n ),
.rd_addr (ADDR29 ),
.data_out (q_out29),
.rd_en (1'b1 ));fifo_ram#(
.USER_BLOCK("TRUE"),
.ADDR_WIDTH(4),
.BASE_WIDTH(4)
) fifo_ram_inst30
(
.wr_clk (clk ),
.wr_rst (!rst_n ),
.wr_addr (wraddr_reg ),
.data_in (data30),
.wr_en (wren ),
.rd_clk (clk ),
.rd_rst (!rst_n ),
.rd_addr (ADDR30 ),
.data_out (q_out30),
.rd_en (1'b1 ));fifo_ram#(
.USER_BLOCK("TRUE"),
.ADDR_WIDTH(4),
.BASE_WIDTH(4)
) fifo_ram_inst31
(
.wr_clk (clk ),
.wr_rst (!rst_n ),
.wr_addr (wraddr_reg ),
.data_in (data31),
.wr_en (wren ),
.rd_clk (clk ),
.rd_rst (!rst_n ),
.rd_addr (ADDR31 ),
.data_out (q_out31),
.rd_en (1'b1 ));endmodule2.4 S盒实现工程的说明
主模块（test_s_box）分为两部分，一部分调用双端口RAM ip核，例化了32个位宽4bit,深度16的双端口RAM，用于存储32 个 S-Box 的总空间为 256 字节（=8×256bit）的数据。RAM的读地址为ADDR0-ADDR31，主模块中通过数据选择器实现了读地址的逻辑以及实现了输出信号Sbox_4_Dout和Sbox_8_Dout的逻辑。
RAM写地址、写使能和写数据的产生由另一部分write_data模块来实现，主要功能是通过输入不同的模式指令实现不同参数的切换，同时产生写地址、写使能和写数据输入到主模块的32个RAM中，完成不同模式下参数的写RAM，供读数据。write_data模块中，使用状态机实现输入不同的模式下，选择对应的参数，同时生成写地址、写使能和写数据。
三、S盒FPGA实现的仿真
部分仿真的输入如下：
#100Sbox_8_addr = 8'h22; #100Sbox_8_addr = 8'h33;#100Sbox_8_addr = 8'h44; #100Sbox_8_addr = 8'h55;Sbox_write_en= 1;#10000Sbox_write_en = 0;
如上红框中是s盒的输出。
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