基于FPGA的自动售货机Verilog开发Modelsim仿真

部分参考代码

(末尾附文件)

module  Sell(input clk,input reset_n,input yiyuan_set,input wuyuan_set,input shiyuan_set,input ok_set_r,input [3:0] good_sel,input [7:0] good_price,output [3:0] current_price,output [3:0] current_num,output [3:0] money_shi,output [3:0] money_ge,output [3:0] final_num,output right_led,output wrong_led,output ok_set_vaild_r
);reg right_led_r;
reg wrong_led_r;
reg ok_set_vaild;
reg [3:0] good_num_1;
reg [3:0] good_num_2;
reg [3:0] good_num_3;
reg [3:0] good_num_4;reg [3:0] current_price_r;
reg [3:0] current_num_r;
reg [3:0] money_shi_r;
reg [3:0] money_ge_r;
reg [3:0] final_num_r;reg [7:0] total;
reg [7:0] charge;wire [3:0] total_ge;
wire [3:0] total_shi;
wire [3:0] total_bai;wire [3:0] charge_ge;
wire [3:0] charge_shi;
wire [3:0] charge_bai;BinToDec BinToDec_total(.clk                  (clk),.reset_n              (reset_n),.bin                  (total),.one                    (total_ge),.ten                 (total_shi),.hun                    (total_bai)
);BinToDec BinToDec_charge(.clk                 (clk),.reset_n              (reset_n),.bin                  (charge),.one                   (charge_ge),.ten                    (charge_shi),.hun                   (charge_bai)
);reg [6:0] current_state, next_state;
parameter   IDLE = 7'd00,     M10 = 7'd10,              M20 = 7'd20,          M30 = 7'd30,          M40 = 7'd40,          M50 = 7'd50,          M60 = 7'd60,M70 = 7'd70,M80 = 7'd80,M90 = 7'd90,M100 = 7'd100,M110 = 7'd110,M_OK = 7'd120,M_NEXT = 7'd121;always@(posedge clk or negedge reset_n) beginif(~reset_n)current_state <= IDLE;elsecurrent_state <= next_state;
endalways@(yiyuan_set or wuyuan_set or shiyuan_set or ok_set_r) beginif(~reset_n) beginnext_state <= IDLE;endelse begincase(current_state) IDLE:beginif(yiyuan_set)next_state <= M10;else if(wuyuan_set)next_state <= M50;else if(shiyuan_set)next_state <= M100;elsenext_state <= current_state;endM10:begin                      if(yiyuan_set)next_state <= M20;else if(wuyuan_set)next_state <= M60;elsenext_state <= current_state;endM20:begin                       if(yiyuan_set)next_state <= M30;else if(wuyuan_set)next_state <= M70;else if(ok_set_r)next_state <= M_OK;elsenext_state <= current_state;endM30:beginif(yiyuan_set)next_state <= M40;else if(wuyuan_set)next_state <= M80;else if(ok_set_r)next_state <= M_OK;elsenext_state <= current_state;endM40:beginif(yiyuan_set)next_state <= M50;else if(wuyuan_set)next_state <= M90;else if(ok_set_r)next_state <= M_OK;elsenext_state <= current_state;endM50:beginif(yiyuan_set)next_state <= M60;else if(wuyuan_set)next_state <= M100;else if(ok_set_r)next_state <= M_OK;elsenext_state <= current_state;endM60:beginif(yiyuan_set)next_state <= M70;else if(wuyuan_set)next_state <= M110;else if(ok_set_r)next_state <= M_OK;elsenext_state <= current_state;end          M70:beginif(yiyuan_set)next_state <= M80;else if(ok_set_r)next_state <= M_OK;elsenext_state <= current_state;endM80:beginif(yiyuan_set)next_state <= M90;else if(ok_set_r)next_state <= M_OK;elsenext_state <= current_state;endM90:beginif(yiyuan_set)next_state <= M100;else if(ok_set_r)next_state <= M_OK;elsenext_state <= current_state;endM100:beginif(yiyuan_set)next_state <= M110;else if(ok_set_r)next_state <= M_OK;elsenext_state <= current_state;endM110:beginif(ok_set_r)next_state <= M_OK;elsenext_state <= current_state;endM_OK:beginnext_state <= M_NEXT;          endM_NEXT:beginif(ok_set_r)next_state <= IDLE;elsenext_state <= current_state;enddefault:next_state <= IDLE;endcaseend
end

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提取码：s1tv

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基于FPGA的自动售货机Verilog开发Modelsim仿真

部分参考代码

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