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1. static void bitbang_work(struct work_struct *work)
2. {
3. struct spi_bitbang    *bitbang =
4. container_of(work, struct spi_bitbang, work);
5. unsigned long        flags;
6. int            do_setup = -1;
7. int            (*setup_transfer)(struct spi_device *,
8. struct spi_transfer *);
9. setup_transfer = bitbang->setup_transfer;
10. spin_lock_irqsave(&bitbang->lock, flags);
11. bitbang->busy = 1;
12. while (!list_empty(&bitbang->queue)) {
13. struct spi_message    *m;
14. struct spi_device    *spi;
15. unsigned        nsecs;
16. struct spi_transfer    *t = NULL;
17. unsigned        tmp;
18. unsigned        cs_change;
19. int            status;
20. m = container_of(bitbang->queue.next, struct spi_message,
21. queue);
22. list_del_init(&m->queue);
23. spin_unlock_irqrestore(&bitbang->lock, flags);
24. /* FIXME this is made-up ... the correct value is known to
25. * word-at-a-time bitbang code, and presumably chipselect()
26. * should enforce these requirements too?
27. */
28. nsecs = 100;
29. spi = m->spi;
30. tmp = 0;
31. cs_change = 1;
32. status = 0;
33. list_for_each_entry (t, &m->transfers, transfer_list) {
34. /* override speed or wordsize? */
35. if (t->speed_hz || t->bits_per_word)
36. do_setup = 1;
37. /* init (-1) or override (1) transfer params */
38. if (do_setup != 0) {
39. if (!setup_transfer) {
40. status = -ENOPROTOOPT;
41. break;
42. }
43. status = setup_transfer(spi, t);
44. if (status < 0)
45. break;
46. }
47. /* set up default clock polarity, and activate chip;
48. * this implicitly updates clock and spi modes as
49. * previously recorded for this device via setup().
50. * (and also deselects any other chip that might be
51. * selected ...)
52. */
53. if (cs_change) {
54. bitbang->chipselect(spi, BITBANG_CS_ACTIVE);
55. ndelay(nsecs);
56. }
57. cs_change = t->cs_change;
58. if (!t->tx_buf && !t->rx_buf && t->len) {
59. status = -EINVAL;
60. break;
61. }
62. /* transfer data. the lower level code handles any
63. * new dma mappings it needs. our caller always gave
64. * us dma-safe buffers.
65. */
66. if (t->len) {
67. /* REVISIT dma API still needs a designated
68. * DMA_ADDR_INVALID; ~0 might be better.
69. */
70. if (!m->is_dma_mapped)
71. t->rx_dma = t->tx_dma = 0;
72. status = bitbang->txrx_bufs(spi, t);
73. }
74. if (status > 0)
75. m->actual_length += status;
76. if (status != t->len) {
77. /* always report some kind of error */
78. if (status >= 0)
79. status = -EREMOTEIO;
80. break;
81. }
82. status = 0;
83. /* protocol tweaks before next transfer */
84. if (t->delay_usecs)
85. udelay(t->delay_usecs);
86. if (!cs_change)
87. continue;
88. if (t->transfer_list.next == &m->transfers)
89. break;
90. /* sometimes a short mid-message deselect of the chip
91. * may be needed to terminate a mode or command
92. */
93. ndelay(nsecs);
94. bitbang->chipselect(spi, BITBANG_CS_INACTIVE);
95. ndelay(nsecs);
96. }
97. m->status = status;
98. m->complete(m->context);
99. /* restore speed and wordsize if it was overridden */
100. if (do_setup == 1)
101. setup_transfer(spi, NULL);
102. do_setup = 0;
103. /* normally deactivate chipselect ... unless no error and
104. * cs_change has hinted that the next message will probably
105. * be for this chip too.
106. */
107. if (!(status == 0 && cs_change)) {
108. ndelay(nsecs);
109. bitbang->chipselect(spi, BITBANG_CS_INACTIVE);
110. ndelay(nsecs);
111. }
112. spin_lock_irqsave(&bitbang->lock, flags);
113. }
114. bitbang->busy = 0;
115. spin_unlock_irqrestore(&bitbang->lock, flags);
116. }