MIPI -- mipi_CSI-2_specification

https://www.mipi.org/specifications/csi-2

Figures… vii
Tables… xiv
Release History… xvi
1 Introduction …1
1.1 Scope …1
1.2 Purpose …1
2 Terminology …2
2.1 Use of Special Terms …2
2.2 Definitions …2
2.3 Abbreviations…3
2.4 Acronyms…3
3 References …5
4 Overview of CSI-2…7
5 CSI-2 Layer Definitions…9
6 Camera Control Interface (CCI) …11
6.1 CCI (I2C) Data Transfer Protocol …12
6.1.1 CCI (I2C) Message Type…12
6.1.2 CCI (I2C) Read/Write Operations…13
6.2 CCI (I3C) Data Transfer Protocol…19
6.2.1 CCI (I3C SDR) Data Transfer Protocol…19
6.2.2 CCI (I3C DDR) Data Transfer Protocol…27
6.3 CCI (I3C) Error Detection and Recovery…37
6.3.1 CCI (I3C SDR) Error Detection and Recovery Method…37
6.3.2 CCI (I3C DDR) Error Detection and Recovery Method…39
6.3.3 Error Detection and Recovery for CCI (I3C) Master Devices …45
6.4 CCI (I2C) Slave Addresses…45
6.5 CCI (I3C) Slave Addresses…45
6.6 CCI Multi-Byte Registers …46
6.6.1 Overview …46
6.6.2 Transmission Byte Order for Multi-Byte Register Values…48
6.6.3 Multi-Byte Register Protocol (Informative) …49
6.7 CCI I/O Electrical and Timing Specifications …53
7 Physical Layer …57
7.1 D-PHY Physical Layer Option …57
7.1.1 D-PHY v2.1 Compatibility with D-PHY v2.0 (Informative) …58
7.2 C-PHY Physical Layer Option…58
8 Multi-Lane Distribution and Merging …59
8.1 Lane Distribution for the D-PHY Physical Layer Option…63
8.2 Lane Distribution for the C-PHY Physical Layer Option…66
8.3 Multi-Lane Interoperability …68
8.3.1 C-PHY Lane De-Skew …70
iv Copyright © 2005-2018 MIPI Alliance, Inc.
All rights reserved.
Confidential
9 Low Level Protocol…71
9.1 Low Level Protocol Packet Format …72
9.1.1 Low Level Protocol Long Packet Format…72
9.1.2 Low Level Protocol Short Packet Format …77
9.2 Data Identifier (DI) …78
9.3 Virtual Channel Identifier …78
9.4 Data Type (DT)…79
9.5 Packet Header Error Correction Code for D-PHY Physical Layer Option…80
9.5.1 General Hamming Code Applied to Packet Header …80
9.5.2 Hamming-Modified Code …81
9.5.3 ECC Generation on TX Side …85
9.5.4 Applying ECC on RX Side (Informative) …86
9.6 Checksum Generation…87
9.7 Packet Spacing…90
9.8 Synchronization Short Packet Data Type Codes…90
9.8.1 Frame Synchronization Packets…91
9.8.2 Line Synchronization Packets …91
9.9 Generic Short Packet Data Type Codes …93
9.10 Packet Spacing Examples Using the Low Power State …93
9.11 Latency Reduction and Transport Efficiency (LRTE) …97
9.11.1 Interpacket Latency Reduction (ILR)…97
9.11.2 Using ILR and Enhanced Transport Efficiency Together…102
9.11.3 LRTE Register Tables…103
9.12 Data Scrambling …105
9.12.1 CSI-2 Scrambling for D-PHY …106
9.12.2 CSI-2 Scrambling for C-PHY…107
9.12.3 Scrambling Details …110
9.13 Packet Data Payload Size Rules …114
9.14 Frame Format Examples…114
9.15 Data Interleaving …118
9.15.1 Data Type Interleaving …118
9.15.2 Virtual Channel Identifier Interleaving…121
10 Color Spaces …123
10.1 RGB Color Space Definition …123
10.2 YUV Color Space Definition…123
11 Data Formats …125
11.1 Generic 8-bit Long Packet Data Types …127
11.1.1 Null and Blanking Data …127
11.1.2 Embedded Information…127
11.1.3 Generic Long Packet Data Types 1 Through 4…128
11.2 YUV Image Data …129
11.2.1 Legacy YUV420 8-bit …129
11.2.2 YUV420 8-bit…132
11.2.3 YUV420 10-bit…136
11.2.4 YUV422 8-bit…138
11.2.5 YUV422 10-bit…140
11.3 RGB Image Data…142
11.3.1 RGB888…143
11.3.2 RGB666…145
11.3.3 RGB565…147
11.3.4 RGB555…149
11.3.5 RGB444…150
11.4 RAW Image Data…151
11.4.1 RAW6 …152
11.4.2 RAW7 …153
11.4.3 RAW8 …154
11.4.4 RAW10 …155
11.4.5 RAW12 …157
11.4.6 RAW14 …158
11.4.7 RAW16 …160
11.4.8 RAW20 …161
11.5 User Defined Data Formats …163
12 Recommended Memory Storage…165
12.1 General/Arbitrary Data Reception…165
12.2 RGB888 Data Reception …166
12.3 RGB666 Data Reception …166
12.4 RGB565 Data Reception …167
12.5 RGB555 Data Reception …167
12.6 RGB444 Data Reception …168
12.7 YUV422 8-bit Data Reception …168
12.8 YUV422 10-bit Data Reception …169
12.9 YUV420 8-bit (Legacy) Data Reception…170
12.10 YUV420 8-bit Data Reception …171
12.11 YUV420 10-bit Data Reception …172
12.12 RAW6 Data Reception…173
12.13 RAW7 Data Reception…173
12.14 RAW8 Data Reception…174
12.15 RAW10 Data Reception…174
12.16 RAW12 Data Reception…175
12.17 RAW14 Data Reception…175
12.18 RAW16 Data Reception…176
12.19 RAW20 Data Reception…176
Annex A JPEG8 Data Format (informative)…177
A.1 Introduction…177
A.2 JPEG Data Definition …178
A.3 Image Status Information …179
A.4 Embedded Images…181
A.5 JPEG8 Non-standard Markers …182
A.6 JPEG8 Data Reception …182
Annex B CSI-2 Implementation Example (informative) …183
B.1 Overview…183
B.2 CSI-2 Transmitter Detailed Block Diagram …184
B.3 CSI-2 Receiver Detailed Block Diagram…185
vi Copyright © 2005-2018 MIPI Alliance, Inc.
All rights reserved.
Confidential
B.4 Details on the D-PHY Implementation…186
B.4.1 CSI-2 Clock Lane Transmitter…187
B.4.2 CSI-2 Clock Lane Receiver…188
B.4.3 CSI-2 Data Lane Transmitter…189
B.4.4 CSI-2 Data Lane Receiver…191
Annex C CSI-2 Recommended Receiver Error Behavior (informative) …193
C.1 Overview…193
C.2 D-PHY Level Error…194
C.3 Packet Level Error …195
C.4 Protocol Decoding Level Error…196
Annex D CSI-2 Sleep Mode (informative) …197
D.1 Overview…197
D.2 SLM Command Phase …197
D.3 SLM Entry Phase…198
D.4 SLM Exit Phase …198
Annex E Data Compression for RAW Data Types (normative) …199
E.1 Predictors …201
E.1.1 Predictor1 …201
E.1.2 Predictor2 …202
E.2 Encoders …203
E.2.1 Coder for 10–8–10 Data Compression …203
E.2.2 Coder for 10–7–10 Data Compression …205
E.2.3 Coder for 10–6–10 Data Compression …208
E.2.4 Coder for 12-10-12 Data Compression …211
E.2.5 Coder for 12–8–12 Data Compression …213
E.2.6 Coder for 12–7–12 Data Compression …216
E.2.7 Coder for 12–6–12 Data Compression …219
E.3 Decoders …222
E.3.1 Decoder for 10–8–10 Data Compression …222
E.3.2 Decoder for 10–7–10 Data Compression …225
E.3.3 Decoder for 10–6–10 Data Compression …228
E.3.4 Decoder for 12–10–12 Data Compression …231
E.3.5 Decoder for 12–8–12 Data Compression …234
E.3.6 Decoder for 12–7–12 Data Compression …237
E.3.7 Decoder for 12–6–12 Data Compression …241
Annex F JPEG Interleaving (informative) …245
Annex G Scrambler Seeds for Lanes 9 and Above…249
Annex H Guidance on CSI-2 Over C-PHY ALP and PPI …251
H.1 CSI-2 with C-PHY ALP Mode …251
H.1.1 Concepts of ALP Mode and Legacy LP Mode …251
H.1.2 Burst Examples Using ALP Mode…254
H.1.3 Transmission and Reception of ALP Commands Through the PPI…259
H.1.4 Multi-Lane Operation Using ALP Mode…265
H.1.5 Concurrent LP and ALP Operation…267

Figures
Figure 1 CSI-2 and CCI Transmitter and Receiver Interface for D-PHY …7
Figure 2 CSI-2 and CCI Transmitter and Receiver Interface for C-PHY…8
Figure 3 CSI-2 Layer Definitions…9
Figure 4 CCI (I2C) Single Read from Random Location …13
Figure 5 CCI (I2C) Single Read from Current Location…14
Figure 6 CCI (I2C) Sequential Read Starting from Random Location…15
Figure 7 CCI (I2C) Sequential Read Starting from Current Location …16
Figure 8 CCI (I2C) Single Write to Random Location …17
Figure 9 CCI (I2C) Sequential Write Starting from Random Location …18
Figure 10 CCI (I3C SDR) Single Read from Random Location…21
Figure 11 CCI (I3C SDR) Single Read from Current Location …22
Figure 12 CCI (I3C SDR) Sequential Read Starting from Random Location…23
Figure 13 CCI (I3C SDR) Sequential Read Starting from Current Location…24
Figure 14 CCI (I3C SDR) Single Write to Random Location…25
Figure 15 CCI (I3C SDR) Sequential Write Starting from Random Location…26
Figure 16 CCI (I3C DDR) Sequential Read from Random Location: 8-bit LENGTH & INDEX…30
Figure 17 CCI (I3C DDR) Sequential Read from Random Location: 16-bit LENGTH & INDEX…31
Figure 18 CCI (I3C DDR) Concatenated Sequential Read, Random Location: 8-bit LENGTH & INDEX…33
Figure 19 CCI (I3C DDR) Concatenated Sequential Read, Random Location: 16-bit LENGTH & INDEX…34
Figure 20 CCI (I3C DDR) Sequential Write Starting from Random Location …36
Figure 21 Example of SS0 Error Detection…38
Figure 22 Example of SD0 Error Detection…40
Figure 23 Example of SD1 Error Detection…42
Figure 24 Example of MD0 Error Detection…44
Figure 25 Corruption of 32-bit Register During Read Message …47
Figure 26 Corruption of 32-bit Register During Write Message…47
Figure 27 Example 16-bit Register Write…48
Figure 28 Example 32-bit Register Write (Address Not Shown)…48
Figure 29 Example 64-bit Register Write (Address Not Shown)…48
Figure 30 Example 16-bit Register Read …49
Figure 31 Example 32-bit Register Read …50
Figure 32 Example 16-bit Register Write…51
Figure 33 Example 32-bit Register Write…52
Figure 34 CCI I/O Timing …55
Figure 35 Conceptual Overview of the Lane Distributor Function for D-PHY…59
Figure 36 Conceptual Overview of the Lane Distributor Function for C-PHY …60
Figure 37 Conceptual Overview of the Lane Merging Function for D-PHY…61
Figure 38 Conceptual Overview of the Lane Merging Function for C-PHY…62
Figure 39 Two Lane Multi-Lane Example for D-PHY …63
Figure 40 Three Lane Multi-Lane Example for D-PHY …64
Figure 41 N-Lane Multi-Lane Example for D-PHY …65
Figure 42 N-Lane Multi-Lane Example for D-PHY Short Packet Transmission…66
Figure 43 Two Lane Multi-Lane Example for C-PHY…67
Figure 44 Three Lane Multi-Lane Example for C-PHY …67
Figure 45 General N-Lane Multi-Lane Distribution for C-PHY…67
Figure 46 One Lane Transmitter and N-Lane Receiver Example for D-PHY…68
Figure 47 M-Lane Transmitter and N-Lane Receiver Example (M<N) for D-PHY…68
Figure 48 M-Lane Transmitter and One Lane Receiver Example for D-PHY…69
Figure 49 M-Lane Transmitter and N-Lane Receiver Example (N<M) for D-PHY…69
Figure 50 Example of Digital Logic to Align All RxDataHS…70
Figure 51 Low Level Protocol Packet Overview …71
Figure 52 Long Packet Structure for D-PHY Physical Layer Option …72
Figure 53 Long Packet Structure for C-PHY Physical Layer Option…73
Figure 54 Packet Header Lane Distribution for C-PHY Physical Layer Option…74
Figure 55 Minimal Filler Byte Insertion Requirements for Three Lane C-PHY…76
Figure 56 Short Packet Structure for D-PHY Physical Layer Option …77
Figure 57 Short Packet Structure for C-PHY Physical Layer Option …77
Figure 58 Data Identifier Byte…78
Figure 59 Logical Channel Block Diagram (Receiver)…78
Figure 60 Interleaved Video Data Streams Examples …79
Figure 61 26-bit ECC Generation Example …80
Figure 62 64-bit ECC Generation on TX Side …85
Figure 63 26-bit ECC Generation on TX Side …85
Figure 64 64-bit ECC on RX Side Including Error Correction…86
Figure 65 26-bit ECC on RX Side Including Error Correction…87
Figure 66 Checksum Transmission Byte Order…87
Figure 67 Checksum Generation for Long Packet Payload Data…88
Figure 68 Definition of 16-bit CRC Shift Register …88
Figure 69 16-bit CRC Software Implementation Example …89
Figure 70 Packet Spacing…90
Figure 71 Example Interlaced Frame Using LS/SE Short Packet and Line Counting …92
Figure 72 Multiple Packet Example …93
Figure 73 Single Packet Example…94
Figure 74 Line and Frame Blanking Definitions…94
Figure 75 Vertical Sync Example …95
Figure 76 Horizontal Sync Example …96
Figure 77 Interpacket Latency Reduction Using LRTE EPD…97
Figure 78 LRTE Efficient Packet Delimiter Example for CSI-2 Over C-PHY (2 Lanes)…99
Figure 79 Example of LRTE EPD for CSI-2 Over D-PHY – Option 1…100
Figure 80 Example of LRTE EPD for CSI-2 Over D-PHY – Option 2…101
Figure 81 Using EPD and ALPS Together …102
Figure 82 System Diagram Showing Per-Lane Scrambling…105
Figure 83 Example of Data Bursts in Two Lanes Using the D-PHY Physical Layer…106
Figure 84 Example of Data Bursts in Two Lanes Using the C-PHY Physical Layer…107
Figure 85 Generating Tx Sync Type as Seed Index (Single Lane View) …108
Figure 86 Generating Tx Sync Type Using the C-PHY Physical Layer…109
Figure 87 PRBS LFSR Serial Implementation Example…112
Figure 88 General Frame Format Example …115
Figure 89 Digital Interlaced Video Example…116
Figure 90 Digital Interlaced Video with Accurate Synchronization Timing Information …117
Figure 91 Interleaved Data Transmission using Data Type Value…118
Figure 92 Packet Level Interleaved Data Transmission …119
Figure 93 Frame Level Interleaved Data Transmission…120
Figure 94 Interleaved Data Transmission using Virtual Channels …121
Figure 95 Byte Packing Pixel Data to C-PHY Symbol Illustration…126
Figure 96 Frame Structure with Embedded Data at the Beginning and End of the Frame …128
Figure 97 Legacy YUV420 8-bit Transmission…129
Figure 98 Legacy YUV420 8-bit Pixel to Byte Packing Bitwise Illustration…130
Figure 99 Legacy YUV420 Spatial Sampling for H.261, H.263 and MPEG 1…130
Figure 100 Legacy YUV420 8-bit Frame Format …131
Figure 101 YUV420 8-bit Data Transmission Sequence …132
Figure 102 YUV420 8-bit Pixel to Byte Packing Bitwise Illustration …133
Figure 103 YUV420 Spatial Sampling for H.261, H.263 and MPEG 1…134
Figure 104 YUV420 Spatial Sampling for MPEG 2 and MPEG 4 …134
Figure 105 YUV420 8-bit Frame Format…135
Figure 106 YUV420 10-bit Transmission …136
Figure 107 YUV420 10-bit Pixel to Byte Packing Bitwise Illustration …137
Figure 108 YUV420 10-bit Frame Format…137
Figure 109 YUV422 8-bit Transmission …138
Figure 110 YUV422 8-bit Pixel to Byte Packing Bitwise Illustration …138
Figure 111 YUV422 Co-sited Spatial Sampling…139
Figure 112 YUV422 8-bit Frame Format …139
Figure 113 YUV422 10-bit Transmitted Bytes…140
Figure 114 YUV422 10-bit Pixel to Byte Packing Bitwise Illustration …140
Figure 115 YUV422 10-bit Frame Format …141
Figure 116 RGB888 Transmission …143
Figure 117 RGB888 Transmission in CSI-2 Bus Bitwise Illustration…143
Figure 118 RGB888 Frame Format…144
Figure 119 RGB666 Transmission with 18-bit BGR Words …145
Figure 120 RGB666 Transmission on CSI-2 Bus Bitwise Illustration…145
Figure 121 RGB666 Frame Format…146
Figure 122 RGB565 Transmission with 16-bit BGR Words …147
Figure 123 RGB565 Transmission on CSI-2 Bus Bitwise Illustration…147
Figure 124 RGB565 Frame Format…148
Figure 125 RGB555 Transmission on CSI-2 Bus Bitwise Illustration…149
Figure 126 RGB444 Transmission on CSI-2 Bus Bitwise Illustration…150
Figure 127 RAW6 Transmission …152
Figure 128 RAW6 Data Transmission on CSI-2 Bus Bitwise Illustration …152
Figure 129 RAW6 Frame Format…152
Figure 130 RAW7 Transmission …153
Figure 131 RAW7 Data Transmission on CSI-2 Bus Bitwise Illustration …153
Figure 132 RAW7 Frame Format…153
Figure 133 RAW8 Transmission …154
Figure 134 RAW8 Data Transmission on CSI-2 Bus Bitwise Illustration …154
Figure 135 RAW8 Frame Format…154
Figure 136 RAW10 Transmission …155
Figure 137 RAW10 Data Transmission on CSI-2 Bus Bitwise Illustration …155
Figure 138 RAW10 Frame Format…156
Figure 139 RAW12 Transmission …157
Figure 140 RAW12 Transmission on CSI-2 Bus Bitwise Illustration…157
Figure 141 RAW12 Frame Format…157
Figure 142 RAW14 Transmission …158
Figure 143 RAW14 Transmission on CSI-2 Bus Bitwise Illustration…158
Figure 144 RAW14 Frame Format…159
Figure 145 RAW16 Transmission …160
Figure 146 RAW16 Transmission on CSI-2 Bus Bitwise Illustration…160
Figure 147 RAW16 Frame Format…160
Figure 148 RAW20 Transmission …161
Figure 149 RAW20 Transmission on CSI-2 Bus Bitwise Illustration…161
Figure 150 RAW20 Frame Format…162
Figure 151 User Defined 8-bit Data (128 Byte Packet) …163
Figure 152 User Defined 8-bit Data Transmission on CSI-2 Bus Bitwise Illustration…163
Figure 153 Transmission of User Defined 8-bit Data…163
Figure 154 General/Arbitrary Data Reception …165
Figure 155 RGB888 Data Format Reception …166
Figure 156 RGB666 Data Format Reception …166
Figure 157 RGB565 Data Format Reception …167
Figure 158 RGB555 Data Format Reception …167
Figure 159 RGB444 Data Format Reception …168
Figure 160 YUV422 8-bit Data Format Reception …168
Figure 161 YUV422 10-bit Data Format Reception …169
Figure 162 YUV420 8-bit Legacy Data Format Reception…170
Figure 163 YUV420 8-bit Data Format Reception …171
Figure 164 YUV420 10-bit Data Format Reception …172
Figure 165 RAW6 Data Format Reception …173
Figure 166 RAW7 Data Format Reception …173
Figure 167 RAW8 Data Format Reception …174
Figure 168 RAW10 Data Format Reception …174
Figure 169 RAW12 Data Format Reception …175
Figure 170 RAW 14 Data Format Reception …175
Figure 171 RAW16 Data Format Reception …176
Figure 172 RAW20 Data Format Reception …176
Figure 173 JPEG8 Data Flow in the Encoder …177
Figure 174 JPEG8 Data Flow in the Decoder …177
Figure 175 EXIF Compatible Baseline JPEG DCT Format…178
Figure 176 Status Information Field in the End of Baseline JPEG Frame…180
Figure 177 Example of TN Image Embedding Inside the Compressed JPEG Data Block …181
Figure 178 JPEG8 Data Format Reception …182
Figure 179 Implementation Example Block Diagram and Coverage…183
Figure 180 CSI-2 Transmitter Block Diagram …184
Figure 181 CSI-2 Receiver Block Diagram …185
Figure 182 D-PHY Level Block Diagram…186
Figure 183 CSI-2 Clock Lane Transmitter …187
Figure 184 CSI-2 Clock Lane Receiver …188
Figure 185 CSI-2 Data Lane Transmitter …189
Figure 186 CSI-2 Data Lane Receiver …191
Figure 187 SLM Synchronization …198
Figure 188 Data Compression System Block Diagram…200
Figure 189 Pixel Order of the Original Image…201
Figure 190 Example Pixel Order of the Original Image …201
Figure 191 Data Type Interleaving: Concurrent JPEG and YUV Image Data …245
Figure 192 Virtual Channel Interleaving: Concurrent JPEG and YUV Image Data …246
Figure 193 Example JPEG and YUV Interleaving Use Cases …247
Figure 194 Comparing Data Burst Timing of Legacy LP mode versus ALP Mode…251
Figure 195 ALP Mode General Burst Format …252
Figure 196 High-Speed and ALP-Pause Wake Receiver Example…253
Figure 197 Examples of Bursts to Send High-Speed Data and ALP Commands…255
Figure 198 State Transitions for an HS Data Burst …256
Figure 199 State Transitions to Enter the ULPS State…257
Figure 200 State Transitions to Exit from the ULPS State…258
Figure 201 PPI Example: HS Signals for Transmission of Data, Sync and ALP Commands…259
Figure 202 PPI Example Transmit Side Timing for an HS Data Burst …260
Figure 203 PPI Example Receive Side Timing for an HS Data Burst…261
Figure 204 PPI Example Transmit Side Timing to Enter the ULPS State…262
Figure 205 PPI Example Receive Side Timing to Enter the ULPS State…263
Figure 206 PPI Example Transmit Side Timing to Exit from the ULPS State…263
Figure 207 PPI Example Receive Side Timing to Exit from the ULPS State …264
Figure 208 Example Showing a Data Transmission Burst using Three Lanes…266
Figure 209 Example Showing an ALP Command Burst using Three Lanes…266
Figure 210 Automatic Selection of ALP Operation or LP Operation…267

Tables
Table 1 CCI (I2C) Read/Write Operations …13
Table 2 CCI (I3C SDR) Read/Write Operations …20
Table 3 CCI (I3C DDR) Read/Write Operations…28
Table 4 CCI (I3C DDR) Read/Write Operation Command Codes…29
Table 5 CCI (I3C SDR) Slave Error Types …37
Table 6 CCI (I3C DDR) Slave Error Types…39
Table 7 CCI (I3C DDR) Master Error Type …43
Table 8 CCI I/O Electrical Specifications …53
Table 9 CCI I/O Timing Specifications …54
Table 10 Data Type Classes…79
Table 11 ECC Syndrome Association Matrix…81
Table 12 ECC Parity Generation Rules …83
Table 13 Synchronization Short Packet Data Type Codes …90
Table 14 Generic Short Packet Data Type Codes…93
Table 15 LRTE Transmitter Registers for CSI-2 Over C-PHY…103
Table 16 LRTE Transmitter Registers for CSI-2 Over D-PHY…104
Table 17 Symbol Sequence Values Per Sync Type…108
Table 18 Fields That Are Not Scrambled …110
Table 19 D-PHY Scrambler PRBS Initial Seed Values for Lanes 1 Through 8 …110
Table 20 C-PHY Scrambler PRBS Initial Seed Values for Lanes 1 Through 8…111
Table 21 Example of the PRBS Bit-at-a-Time Shift Sequence …113
Table 22 Example PRBS LFSR Byte Sequence for D-PHY Physical Layer …113
Table 23 Example PRBS LFSR Byte Sequence for C-PHY Physical Layer…114
Table 24 Primary and Secondary Data Formats Definitions …125
Table 25 Generic 8-bit Long Packet Data Types …127
Table 26 YUV Image Data Types…129
Table 27 Legacy YUV420 8-bit Packet Data Size Constraints …129
Table 28 YUV420 8-bit Packet Data Size Constraints…132
Table 29 YUV420 10-bit Packet Data Size Constraints…136
Table 30 YUV422 8-bit Packet Data Size Constraints…138
Table 31 YUV422 10-bit Packet Data Size Constraints…140
Table 32 RGB Image Data Types …142
Table 33 RGB888 Packet Data Size Constraints…143
Table 34 RGB666 Packet Data Size Constraints…145
Table 35 RGB565 Packet Data Size Constraints…147
Table 36 RAW Image Data Types …151
Table 37 RAW6 Packet Data Size Constraints…152
Table 38 RAW7 Packet Data Size Constraints…153
Table 39 RAW8 Packet Data Size Constraints…154
Table 40 RAW10 Packet Data Size Constraints …155
Table 41 RAW12 Packet Data Size Constraints …157
Table 42 RAW14 Packet Data Size Constraints …158
Table 43 RAW16 Packet Data Size Constraints …160
Table 44 RAW20 Packet Data Size Constraints …161
Table 45 User Defined 8-bit Data Types …164
Table 46 Status Data Padding…179
Table 47 JPEG8 Additional Marker Codes Listing …182
Table 48 Initial Seed Values for Lanes 9 through 32…249
Table 49 ALP Code Definitions used by CSI-2…258

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