`include "defines.v"module zet_core (input clk,input rst,// interruptsinput  intr,output inta,input  nmi,output nmia,// interfaceoutput [19:0] cpu_adr_o,input  [15:0] iid_dat_i,input  [15:0] cpu_dat_i,output [15:0] cpu_dat_o,output        cpu_byte_o,input         cpu_block,output        cpu_mem_op,output        cpu_m_io,output        cpu_we_o,output [19:0] pc  // for debugging purposes);

module zet_exec (input         clk,input         rst,input [`IR_SIZE-1:0] ir,input [15:0]  off,input [15:0]  imm,output [15:0] cs,output [15:0] ip,output        of,output        zf,output        cx_zero,input [15:0]  memout,output [15:0] wr_data,output [19:0] addr,output        we,output        m_io,output        byteop,input         block,output        div_exc,input         wrip0,output        ifl,output        tfl,output        wr_ss);// Net declarationswire [15:0] c;wire [15:0] omemalu;wire [ 3:0] addr_a;wire [ 3:0] addr_c;wire [ 3:0] addr_d;wire [ 8:0] flags;wire [15:0] a, b, s, alu_iflags, bus_b;wire [31:0] aluout;wire [3:0]  addr_b;wire [2:0]  t, func;wire [1:0]  addr_s;wire        wrfl, high, memalu, r_byte, c_byte;wire        wr, wr_reg;wire        wr_cnd;wire        jmp;wire        b_imm;wire  [8:0] iflags, oflags;wire  [4:0] logic_flags;wire        alu_word;wire        a_byte;wire        b_byte;wire        wr_high;wire        dive;// Module instances
  zet_alu alu( {c, a }, bus_b, aluout, t, func, alu_iflags, oflags,alu_word, s, off, clk, dive);zet_regfile regfile (a, b, c, cs, ip, {aluout[31:16], omemalu}, s, flags, wr_reg, wrfl,wr_high, clk, rst, addr_a, addr_b, addr_c, addr_d, addr_s, iflags,~byteop, a_byte, b_byte, c_byte, cx_zero, wrip0);zet_jmp_cond jmp_cond (logic_flags, addr_b, addr_c[0], c, jmp);// Assignmentsassign addr_s = ir[1:0];assign addr_a = ir[5:2];assign addr_b = ir[9:6];assign addr_c = ir[13:10];assign addr_d = ir[17:14];assign wrfl   = ir[18];assign we     = ir[19];assign wr     = ir[20];assign wr_cnd = ir[21];assign high   = ir[22];assign t      = ir[25:23];assign func   = ir[28:26];assign byteop = ir[29];assign memalu = ir[30];assign m_io   = ir[32];assign b_imm  = ir[33];assign r_byte = ir[34];assign c_byte = ir[35];assign omemalu = memalu ? aluout[15:0] : memout;assign bus_b   = b_imm ? imm : b;assign addr = aluout[19:0];assign wr_data = c;assign wr_reg  = (wr | (jmp & wr_cnd)) && !block && !div_exc;assign wr_high = high && !block && !div_exc;assign of  = flags[8];assign ifl = flags[6];assign tfl = flags[5];assign zf  = flags[3];assign iflags = oflags;assign alu_iflags = { 4'b1111, flags[8:3], 1'b0, flags[2], 1'b0, flags[1],1'b1, flags[0] };assign logic_flags = { flags[8], flags[4], flags[3], flags[1], flags[0] };assign alu_word = (t==3'b011) ? ~r_byte : ~byteop;assign a_byte = (t==3'b011 && func[1]) ? 1'b0 : r_byte;assign b_byte = r_byte;assign div_exc = dive && wr;assign wr_ss = (addr_d == 4'b1010) && wr;endmodule

module altor32_lite
(// Generalinput               clk_i /*verilator public*/,input               rst_i /*verilator public*/,// Maskable interrupt    input               intr_i /*verilator public*/,// Unmaskable interruptinput               nmi_i /*verilator public*/,// Memory interfaceoutput reg [31:0]   mem_addr_o /*verilator public*/,input [31:0]        mem_dat_i /*verilator public*/,output reg [31:0]   mem_dat_o /*verilator public*/,output reg          mem_cyc_o /*verilator public*/,output reg          mem_stb_o /*verilator public*/,output reg          mem_we_o /*verilator public*/,output reg [3:0]    mem_sel_o /*verilator public*/,input               mem_ack_i/*verilator public*/
);
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//-----------------------------------------------------------------
// Next State Logic
//-----------------------------------------------------------------
reg [3:0] next_state_r;
always @ *
beginnext_state_r = state_q;case (state_q)    //-----------------------------------------// IDLE - //-----------------------------------------
    STATE_IDLE :beginif (enable_i)next_state_r    = STATE_FETCH;end    //-----------------------------------------// FETCH - Fetch line from memory//-----------------------------------------
    STATE_FETCH :beginnext_state_r    = STATE_FETCH_WAIT;end//-----------------------------------------// FETCH_WAIT - Wait for read responses//-----------------------------------------
    STATE_FETCH_WAIT:begin// Read from memory completeif (mem_ack_i)next_state_r = STATE_EXEC;end  //-----------------------------------------// EXEC//-----------------------------------------
    STATE_EXEC :beginif (load_inst_r || store_inst_r)next_state_r    = STATE_MEM;elsenext_state_r    = STATE_WRITE_BACK;end//-----------------------------------------// MEM//-----------------------------------------
    STATE_MEM :begin// Read from memory completeif (mem_ack_i)next_state_r = STATE_FETCH;end    //-----------------------------------------// WRITE_BACK//-----------------------------------------
    STATE_WRITE_BACK :beginif (enable_i)next_state_r    = STATE_FETCH;end    default:;endcase
end
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//-----------------------------------------------------------------
// Memory Access / Instruction Fetch
//-----------------------------------------------------------------
always @ (posedge rst_i or posedge clk_i )
beginif (rst_i == 1'b1)beginmem_addr_o      <= 32'h00000000;        mem_dat_o       <= 32'h00000000;mem_sel_o       <= 4'b0;mem_we_o        <= 1'b0;mem_stb_o       <= 1'b0;mem_cyc_o       <= 1'b0;
opcode_q        <= 32'h00000000;mem_offset_q    <= 2'b0;endelsebegincase (state_q)//-----------------------------------------// FETCH - Issue instruction fetch//-----------------------------------------
            STATE_FETCH :begin// Start fetch from memorymem_addr_o  <= pc_q;mem_stb_o   <= 1'b1;mem_we_o    <= 1'b0;mem_cyc_o   <= 1'b1;end//-----------------------------------------// FETCH_WAIT - Wait for response//-----------------------------------------
            STATE_FETCH_WAIT :begin// Data ready from memory?if (mem_ack_i)beginopcode_q    <= mem_dat_i;mem_cyc_o   <= 1'b0;                            endend//-----------------------------------------// EXEC - Issue read / write//-----------------------------------------
            STATE_EXEC :begin`ifdef CONF_CORE_TRACE$display("%08x: Execute 0x%08x", pc_q, opcode_q);$display(" rA[%d] = 0x%08x", ra_w, reg_ra_r);$display(" rB[%d] = 0x%08x", rb_w, reg_rb_r);`endifcase (1'b1)// l.lbs l.lhs l.lws l.lbz l.lhz l.lwz
                 load_inst_r:beginmem_addr_o      <= {mem_addr_r[31:2], 2'b0};mem_offset_q    <= mem_addr_r[1:0];mem_dat_o       <= 32'h00000000;mem_sel_o       <= 4'b1111;mem_we_o        <= 1'b0;mem_stb_o       <= 1'b1;mem_cyc_o       <= 1'b1;
`ifdef CONF_CORE_DEBUG$display(" Load from 0x%08x to R%d", mem_addr_r, rd_w);`endifendinst_sb_w: // l.sbbeginmem_addr_o      <= {mem_addr_r[31:2], 2'b0};mem_offset_q    <= mem_addr_r[1:0];case (mem_addr_r[1:0])2'b00 :beginmem_dat_o       <= {reg_rb_r[7:0],24'h000000};mem_sel_o       <= 4'b1000;mem_we_o        <= 1'b1;mem_stb_o       <= 1'b1;mem_cyc_o       <= 1'b1;end2'b01 :beginmem_dat_o       <= {{8'h00,reg_rb_r[7:0]},16'h0000};mem_sel_o       <= 4'b0100;mem_we_o        <= 1'b1;mem_stb_o       <= 1'b1;mem_cyc_o       <= 1'b1;end2'b10 :beginmem_dat_o       <= {{16'h0000,reg_rb_r[7:0]},8'h00};mem_sel_o       <= 4'b0010;mem_we_o        <= 1'b1;mem_stb_o       <= 1'b1;mem_cyc_o       <= 1'b1;end2'b11 :beginmem_dat_o       <= {24'h000000,reg_rb_r[7:0]};mem_sel_o       <= 4'b0001;mem_we_o        <= 1'b1;mem_stb_o       <= 1'b1;mem_cyc_o       <= 1'b1;enddefault :;endcaseendinst_sh_w: // l.shbeginmem_addr_o      <= {mem_addr_r[31:2], 2'b0};mem_offset_q    <= mem_addr_r[1:0];case (mem_addr_r[1:0])2'b00 :beginmem_dat_o       <= {reg_rb_r[15:0],16'h0000};mem_sel_o       <= 4'b1100;mem_we_o        <= 1'b1;mem_stb_o       <= 1'b1;mem_cyc_o       <= 1'b1;end2'b10 :beginmem_dat_o       <= {16'h0000,reg_rb_r[15:0]};mem_sel_o       <= 4'b0011;mem_we_o        <= 1'b1;mem_stb_o       <= 1'b1;mem_cyc_o       <= 1'b1;enddefault :;endcaseendinst_sw_w: // l.swbeginmem_addr_o      <= {mem_addr_r[31:2], 2'b0};mem_offset_q    <= mem_addr_r[1:0];mem_dat_o       <= reg_rb_r;mem_sel_o       <= 4'b1111;mem_we_o        <= 1'b1;mem_stb_o       <= 1'b1;mem_cyc_o       <= 1'b1;
`ifdef CONF_CORE_DEBUG$display(" Store R%d to 0x%08x = 0x%08x", rb_w, {mem_addr_r[31:2],2'b00}, reg_rb_r);
      `endifenddefault:;endcaseend//-----------------------------------------// MEM - Wait for response//-----------------------------------------
            STATE_MEM :begin// Data ready from memory?if (mem_ack_i)beginmem_cyc_o   <= 1'b0;endend            default:;endcaseend
end

//-----------------------------------------------------------------
// Module - AltOR32 CPU (Pipelined Wishbone Interfaces)
//-----------------------------------------------------------------
module altor32
(// Generalinput               clk_i,input               rst_i,input               intr_i,input               nmi_i,output              fault_o,output              break_o,// Instruction memoryoutput [31:0]       imem_addr_o,input [31:0]        imem_dat_i,output [2:0]        imem_cti_o,output              imem_cyc_o,output              imem_stb_o,input               imem_ack_i,  // Data memoryoutput [31:0]       dmem_addr_o,output [31:0]       dmem_dat_o,input [31:0]        dmem_dat_i,output [3:0]        dmem_sel_o,output [2:0]        dmem_cti_o,output              dmem_cyc_o,output              dmem_we_o,output              dmem_stb_o,input               dmem_ack_i
);
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//-----------------------------------------------------------------
// Module - Wishbone fetch unit
//-----------------------------------------------------------------
always @ (posedge rst_i or posedge clk_i )
beginif (rst_i == 1'b1)beginwbm_addr_o      <= 32'h00000000;wbm_cti_o       <= 3'b0;wbm_stb_o       <= 1'b0;wbm_cyc_o       <= 1'b0;
fetch_word_q    <= {FETCH_WORDS_W{1'b0}};resp_word_q     <= {FETCH_WORDS_W{1'b0}};endelsebegin// Idleif (!wbm_cyc_o)beginif (fetch_i)beginif (burst_i)beginwbm_addr_o      <= {address_i[31:FETCH_BYTES_W], {FETCH_BYTES_W{1'b0}}};fetch_word_q    <= {FETCH_WORDS_W{1'b0}};resp_word_q     <= {FETCH_WORDS_W{1'b0}};// Incrementing linear burstwbm_cti_o       <= WB_CTI_BURST;endelsebegin                    wbm_addr_o      <= address_i;resp_word_q     <= address_i[FETCH_BYTES_W-1:2];// Single fetchwbm_cti_o       <= WB_CTI_FINAL;                    end// Start fetch from memorywbm_stb_o           <= 1'b1;wbm_cyc_o           <= 1'b1;                        endend// Access in-progresselsebegin// Command acceptedif (~wbm_stall_i)begin// Fetch next word for lineif (wbm_cti_o != WB_CTI_FINAL)beginwbm_addr_o      <= {wbm_addr_o[31:FETCH_BYTES_W], next_word_w, 2'b0};fetch_word_q    <= next_word_w;// Final word to read?if (penultimate_word_w)wbm_cti_o   <= WB_CTI_FINAL;end// Fetch completeelsewbm_stb_o       <= 1'b0;end// Responseif (wbm_ack_i)resp_word_q         <= resp_word_q + 1'b1;// Last response?if (final_o)wbm_cyc_o           <= 1'b0;endend
end
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//-----------------------------------------------------------------
// Module - Data Cache Memory Interface
//-----------------------------------------------------------------
always @ *
beginnext_state_r = state;case (state)//-----------------------------------------// IDLE//-----------------------------------------
    STATE_IDLE :begin// Perform cache evict (write)     if (evict_i)next_state_r    = STATE_WRITE_SETUP;// Perform cache fill (read)else if (fill_i)next_state_r    = STATE_FETCH;// Read/Write singleelse if (rd_single_i | (|wr_single_i))next_state_r    = STATE_MEM_SINGLE;end//-----------------------------------------// FETCH - Fetch line from memory//-----------------------------------------
    STATE_FETCH :begin// Line fetch complete?if (~mem_stall_i && request_idx == {CACHE_LINE_WORDS_IDX_MAX{1'b1}})next_state_r    = STATE_FETCH_WAIT;end//-----------------------------------------// FETCH_WAIT - Wait for read responses//-----------------------------------------
    STATE_FETCH_WAIT:begin// Read from memory completeif (mem_ack_i && response_idx == {CACHE_LINE_WORDS_IDX_MAX{1'b1}})next_state_r = STATE_IDLE;end  //-----------------------------------------// WRITE_SETUP - Wait for data from cache//-----------------------------------------
    STATE_WRITE_SETUP :next_state_r    = STATE_WRITE;//-----------------------------------------// WRITE - Write word to memory//-----------------------------------------
    STATE_WRITE :begin// Line write complete?if (~mem_stall_i && request_idx == {CACHE_LINE_WORDS_IDX_MAX{1'b1}})next_state_r = STATE_WRITE_WAIT;// Fetch next word for lineelse if (~mem_stall_i | ~mem_stb_o)next_state_r = STATE_WRITE_SETUP;end//-----------------------------------------// WRITE_WAIT - Wait for write to complete//-----------------------------------------
    STATE_WRITE_WAIT:begin// Write to memory completeif (mem_ack_i && response_idx == {CACHE_LINE_WORDS_IDX_MAX{1'b1}})next_state_r = STATE_IDLE;end            //-----------------------------------------// MEM_SINGLE - Single access to memory//-----------------------------------------
    STATE_MEM_SINGLE:begin// Data ready from memory?if (mem_ack_i)next_state_r  = STATE_IDLE;end  default:;endcase
end