1 module SEG7_Controller (
2 // Avalon clock interface siganals
3   input csi_clockreset_clk,
4 input csi_clockreset_reset_n,
5 // Signals for Avalon-MM slave port
6   input [ADDR_WIDTH-1:0] avs_s1_address,
7 input avs_s1_write,
8 input [DATA_WIDTH-1:0] avs_s1_writedata,
9 // user logic inputs and outputs
10   output [SEG7_NUM*8-1:0] avs_s1_export_oHEX
11 );
12
13 parameter DATA_WIDTH = 32; // data bus width
14  parameter SEG7_NUM = 8; // specify the number of seg7 unit
15  parameter ADDR_WIDTH = 3; // log2(SEG7_NUM)
16  
17 reg [SEG7_NUM-1:0] base_index;
18 reg [DATA_WIDTH-1:0] write_data;
19 reg [(SEG7_NUM*8-1):0] reg_file;
20
21 assign avs_s1_export_oHEX = ~reg_file;
22
23 always@(posedge csi_clockreset_clk, negedge csi_clockreset_reset_n) begin
24 if (!csi_clockreset_reset_n) begin
25 integer i;
26 base_index <= 8'h00;
27 write_data <= 8'h00;
28
29 for(i = 0; i < SEG7_NUM * 8; i = i + 1)
30 reg_file[i] <= 1'b1;
31 end
32 else begin
33 if (avs_s1_write) begin
34 integer j;
35 write_data <= avs_s1_writedata;
36 base_index <= (avs_s1_address << 3);
37
38 for(j = 0; j < 8; j = j + 1)
39 reg_file[base_index+j] <= write_data[j];
40 end
41 end
42 end
43
44 endmodule

SEG7_NUM = 2；

ADDR_WIDTH = 1；

1 module SEG7_Controller (
2 // Avalon clock interface siganals
3 input csi_clockreset_clk,
4 input csi_clockreset_reset_n,
5 // Signals for Avalon-MM slave port
6 input [ADDR_WIDTH-1:0] avs_s1_address,
7 input avs_s1_write,
8 input [31:0] avs_s1_writedata,
9 // user logic inputs and outputs
10 output [SEG7_NUM*8-1:0] avs_s1_export_oHEX
11 );
12
13 parameter SEG7_NUM = 8; // specify the number of seg7 unit
14 parameter ADDR_WIDTH = 3; // log2(SEG7_NUM)
15 parameter DEFAULT_ACTIVE = 1;
16 parameter LOW_ACTIVE = 1;
17
18 reg [(SEG7_NUM*8-1):0] reg_file;
19
20 assign avs_s1_export_oHEX = (LOW_ACTIVE)?~reg_file:reg_file;
21
22 always@(posedge csi_clockreset_clk, negedge csi_clockreset_reset_n) begin
23 if (!csi_clockreset_reset_n) begin
24 reg_file[(SEG7_NUM*8-1):0] <= (DEFAULT_ACTIVE)?8'hFF:8'h00; // trun on or off
25 end
26 else begin
27 if (avs_s1_write) begin
28 integer j;
29 for(j = 0; j < 8; j = j + 1)
30 reg_file[(avs_s1_address << 3) + j] <= avs_s1_writedata[j];
31 // reg_file[((avs_s1_address << 3) + 7 ):(avs_s1_address << 3)] <= avs_s1_writedata[7:0];
32 end
33 end
34 end
35
36 endmodule