iTop-4412精英版的u-boot-2017.11移植教程（三）

（一）修改clock.c

经过上面两节的修改，我们发现还是有些问题，就是u-boot启动后会停留在MMC: ，其实这是由于在clock.c文件中关于mmc和lcd部分的结构体用错了

exynos4_get_mmc_clk()

exynos4_set_mmc_clk()

exynos4_get_lcd_clk()

exynos4_set_lcd_clk()

根据文档资料，exynos4412芯片属于4x12系列，而不是4系列，所以要改一下

（二）修改lowlevel_init.c

由于itop-4412开发板用的串口是串口2，所以改一下；还有就是tzpc的初始化，u-boot-2017.11默认的tzpc是exynos5系列芯片的，其实exynos4412已经有tzpc了，关于exynos的tzpc相关的知识，大家可以去网上学习，由于我移植的u-boot又不是用于高大上的商业机密啥的，就把它注释了，如果自己想加上tzpc的话，自己参考讯为提供的三星原厂exynos4412芯片文档，在第14章。

讯为提供的三星原厂exynos4412芯片文档第14章

（三）修改power.c

（1）为power.h文件增加exynos4x12_power
这是由于exynos4412芯片属于exynos4x12类型

这个结构体来源与讯为提供的三星原厂exynos4412芯片资料的8.8 Register Description

代码

struct exynos4x12_power {unsigned int    om_stat;unsigned char   res1[0xc];unsigned int    rtc_clko_sel;unsigned int    gnss_rtc_out_ctrl;unsigned int    lpi_denial_mask0;unsigned int    lpi_denial_mask1;unsigned int    lpi_denial_mask2;unsigned int    c2c_ctrl;unsigned char   res2[0x1d8];unsigned int    central_seq_config;unsigned int    res3;unsigned int    central_seq_option;unsigned char   res4[0x1f4];unsigned int    swreset;unsigned int    rst_stat;unsigned int    auto_wdt_reset_disable;unsigned int    mask_wdt_reset_request;unsigned char   res5[0x1f0];unsigned int    wakeup_stat;unsigned int    eint_wakeup_mask;unsigned int    wakeup_mask;unsigned char   res6[0xf4];unsigned int    hdmi_phy_control;unsigned int    usbdevice_phy_control;unsigned int    hsic_1_phy_control;unsigned int    hsic_2_phy_control;unsigned int    mipi_phy0_control;unsigned int    mipi_phy1_control;unsigned int    adc_phy_control;unsigned char   res7[0x64];unsigned int    body_bias_con0;unsigned int    body_bias_con1;unsigned int    body_bias_con2;unsigned int    body_bias_con3;unsigned char   res8[0x70];unsigned int    inform0;unsigned int    inform1;unsigned int    inform2;unsigned int    inform3;unsigned int    inform4;unsigned int    inform5;unsigned int    inform6;unsigned int    inform7;unsigned char   res9[0x1e0];unsigned int    pmu_debug;unsigned char   res10[0x5fc];unsigned int    arm_core0_sys_pwr_reg;unsigned char   res11[0xc];unsigned int    arm_core1_sys_pwr_reg;unsigned char   res12[0x6c];unsigned int    arm_common_sys_pwr_reg;unsigned char   res13[0x3c];unsigned int    arm_cpu_l2_0_sys_pwr_reg;unsigned int    arm_cpu_l2_1_sys_pwr_reg;unsigned char   res14[0x38];unsigned int    cmu_aclkstop_sys_pwr_reg;unsigned int    cmu_sclkstop_sys_pwr_reg;unsigned char   res15[0x4];unsigned int    cmu_reset_sys_pwr_reg;unsigned char   res16[0x10];unsigned int    apll_sysclk_sys_pwr_reg;unsigned int    mpll_sysclk_sys_pwr_reg;unsigned int    vpll_sysclk_sys_pwr_reg;unsigned int    epll_sysclk_sys_pwr_reg;unsigned char   res17[0x8];unsigned int    cmu_clkstop_gps_alive_sys_pwr_reg;unsigned int    cmu_reset_gps_alive_sys_pwr_reg;unsigned int    cmu_clkstop_cam_sys_pwr_reg;unsigned int    cmu_clkstop_tv_sys_pwr_reg; unsigned int    cmu_clkstop_mfc_sys_pwr_reg;unsigned int    cmu_clkstop_g3d_sys_pwr_reg;unsigned int    cmu_clkstop_lcd0_sys_pwr_reg;unsigned int    cmu_clkstop_isp_sys_pwr_reg;unsigned int    cmu_clkstop_maudio_sys_pwr_reg;unsigned int    cmu_clkstop_gps_sys_pwr_reg;unsigned int    cmu_reset_cam_sys_pwr_reg;unsigned int    cmu_reset_tv_sys_pwr_reg;unsigned int    cmu_reset_mfc_sys_pwr_reg;unsigned int    cmu_reset_g3d_sys_pwr_reg;unsigned int    cmu_reset_lcd0_sys_pwr_reg;unsigned int    cmu_reset_isp_sys_pwr_reg;unsigned int    cmu_reset_maudio_sys_pwr_reg;unsigned int    cmu_reset_gps_sys_pwr_reg;unsigned int    top_bus_sys_pwr_reg;unsigned int    top_retention_sys_pwr_reg;unsigned int    top_pwr_sys_pwr_reg;unsigned char   res18[0x14];unsigned int    logic_reset_sys_pwr_reg;unsigned char   res19[0x1c];unsigned int    onenandxl_mem_sys_pwr_reg;unsigned int    hsi_mem_sys_pwr_reg;unsigned char   res20[0x4]; unsigned int    usbotg_mem_sys_pwr_reg;unsigned int    sdmmc_mem_sys_pwr_reg;unsigned int    cssys_mem_sys_pwr_reg;unsigned int    secss_mem_sys_pwr_reg;unsigned int    potator_mem_sys_pwr_reg;unsigned char   res21[0x20];unsigned int    pad_retention_dram_sys_pwr_reg;unsigned int    pad_retention_maudio_sys_pwr_reg;unsigned char   res22[0x18];unsigned int    pad_retention_gpio_sys_pwr_reg;unsigned int    pad_retention_uart_sys_pwr_reg;unsigned int    pad_retention_mmca_sys_pwr_reg;unsigned int    pad_retention_mmcb_sys_pwr_reg;unsigned int    pad_retention_ebia_sys_pwr_reg;unsigned int    pad_retention_ebib_sys_pwr_reg;unsigned char   res23[0x8];unsigned int    pad_isolation_sys_pwr_reg;unsigned char   res24[0x1c];unsigned int    pad_alv_sel_sys_pwr_reg;unsigned char   res25[0x1c];unsigned int    xusbxti_sys_pwr_reg;unsigned int    xxti_sys_pwr_reg;unsigned char   res26[0x38];unsigned int    ext_regulator_sys_pwr_reg;unsigned char   res27[0x3c];unsigned int    gpio_mode_sys_pwr_reg;unsigned char   res28[0x3c];unsigned int    gpio_mode_maudio_sys_pwr_reg;unsigned char   res29[0x3c];unsigned int    cam_sys_pwr_reg;unsigned int    tv_sys_pwr_reg;unsigned int    mfc_sys_pwr_reg;unsigned int    g3d_sys_pwr_reg;unsigned int    lcd0_sys_pwr_reg;unsigned int    isp_sys_pwr_reg;unsigned int    maudio_sys_pwr_reg;unsigned int    gps_sys_pwr_reg;unsigned int    gps_alive_sys_pwr_reg;unsigned char   res30[0xc5c];unsigned int    arm_core0_configuration;unsigned int    arm_core0_status;unsigned int    arm_core0_option;unsigned char   res31[0x74];unsigned int    arm_core1_configuration;unsigned int    arm_core1_status;unsigned int    arm_core1_option;unsigned char   res32[0x37c];unsigned int    arm_common_option;unsigned char   res33[0x1f4];unsigned int    arm_cpu_l2_0_configuration;unsigned int    arm_cpu_l2_0_status;unsigned char   res34[0x18];unsigned int    arm_cpu_l2_1_configuration;unsigned int    arm_cpu_l2_1_status;unsigned char   res35[0xa00];unsigned int    pad_retention_maudio_option;unsigned char   res36[0xdc];unsigned int    pad_retention_gpio_option;unsigned char   res37[0x1c];unsigned int    pad_retention_uart_option;unsigned char   res38[0x1c];unsigned int    pad_retention_mmca_option;unsigned char   res39[0x1c];unsigned int    pad_retention_mmcb_option;unsigned char   res40[0x1c];unsigned int    pad_retention_ebia_option;unsigned char   res41[0x1c];unsigned int    pad_retention_ebib_option;unsigned char   res42[0x160];unsigned int    ps_hold_control;unsigned char   res43[0xf0];unsigned int    xusbxti_configuration;unsigned int    xusbxti_status;unsigned char   res44[0x14];unsigned int    xusbxti_duration;unsigned int    xxti_configuration;unsigned int    xxti_status;unsigned char   res45[0x14];unsigned int    xxti_duration;unsigned char   res46[0x1dc];unsigned int    ext_regulator_duration;unsigned char   res47[0x5e0];unsigned int    cam_configuration;unsigned int    cam_status;unsigned int    cam_option;unsigned char   res48[0x14];unsigned int    tv_configuration;unsigned int    tv_status;unsigned int    tv_option;unsigned char   res49[0x14];unsigned int    mfc_configuration;unsigned int    mfc_status;unsigned int    mfc_option;unsigned char   res50[0x14];unsigned int    g3d_configuration;unsigned int    g3d_status;unsigned int    g3d_option;unsigned char   res51[0x14];unsigned int    lcd0_configuration;unsigned int    lcd0_status;unsigned int    lcd0_option;unsigned char   res52[0x14];unsigned int    isp_configuration;unsigned int    isp_status;unsigned int    isp_option;unsigned char   res53[0x34];unsigned int    gps_configuration;unsigned int    gps_status;unsigned int    gps_option;unsigned char   res54[0x14];unsigned int    gps_alive_configuration;unsigned int    gps_alive_status;unsigned int    gps_alive_option;
};

（2）添加exynos4x12_set_ps_hold_ctrl函数，并修改set_ps_hold_ctrl

static void exynos4x12_set_ps_hold_ctrl(void)
{struct exynos4x12_power *power = (struct exynos4x12_power *)samsung_get_base_power();/* value: 1000000000B */setbits_le32(&power->ps_hold_control, EXYNOS_PS_HOLD_CONTROL_DATA_HIGH);/*** GPX0PUD register** 0x0 = Disables Pull-up/Pull-down* 0x1 = Enables Pull-down* 0x2 = Reserved* 0x3 = Enables Pull-up*/writel(0x3, (unsigned int *)0x11000c08);
}

注：为啥要修改GPX0PUD寄存器呢？因为exynos4412 scp 核心板的电源管理是通过gpio来控制电源管理的，所以要将gpio设置为上拉

void set_ps_hold_ctrl(void)
{if (cpu_is_exynos5())exynos5_set_ps_hold_ctrl();
#ifdef CONFIG_ITOP4412else if (cpu_is_exynos4())exynos4x12_set_ps_hold_ctrl();
#endif
}

（四）配置itop4412.h文件了

/** Copyright (C) 2011 Samsung Electronics** Configuration settings for the SAMSUNG ITOP4412 (EXYNOS4412) board.** SPDX-License-Identifier: GPL-2.0+*/#ifndef __CONFIG_ITOP4412_H
#define __CONFIG_ITOP4412_H#include <configs/exynos4-common.h>#define CONFIG_SUPPORT_EMMC_BOOT 1/* High Level Configuration Options */
#define CONFIG_EXYNOS4210       1   /* which is a EXYNOS4210 SoC */
#define CONFIG_ITOP4412         1   /* working with ITOP4412*/#define CONFIG_SYS_DCACHE_OFF       1/* itop-4412 has 4 bank of DRAM */
#define CONFIG_NR_DRAM_BANKS        4
#define CONFIG_SYS_SDRAM_BASE       0x40000000
#define PHYS_SDRAM_1            CONFIG_SYS_SDRAM_BASE
#define SDRAM_BANK_SIZE         (256 << 20) /* 256 MB *//* memtest works on */
#define CONFIG_SYS_MEMTEST_START    CONFIG_SYS_SDRAM_BASE
#define CONFIG_SYS_MEMTEST_END      (CONFIG_SYS_SDRAM_BASE + 0x6000000)
#define CONFIG_SYS_LOAD_ADDR        (CONFIG_SYS_SDRAM_BASE + 0x00100000)#define CONFIG_SYS_TEXT_BASE        0x43E00000/* #define MACH_TYPE_ITOP4412       0xffffffff */
#define CONFIG_MACH_TYPE        MACH_TYPE_ITOP4412/* select serial console configuration */
#define CONFIG_SERIAL2/* Console configuration */
#define CONFIG_DEFAULT_CONSOLE      "console=ttySAC1,115200n8\0"#define CONFIG_SYS_MEM_TOP_HIDE (1 << 20)   /* ram console */#define CONFIG_SYS_MONITOR_BASE 0x00000000/* Power Down Modes */
#define S5P_CHECK_SLEEP         0x00000BAD
#define S5P_CHECK_DIDLE         0xBAD00000
#define S5P_CHECK_LPA           0xABAD0000#define CONFIG_SUPPORT_RAW_INITRD/* MMC SPL */
#define COPY_BL2_FNPTR_ADDR     0x02020030
#define CONFIG_SPL_TEXT_BASE    0x02023400 /* 0x02021410 */#define CONFIG_EXTRA_ENV_SETTINGS \"loadaddr=0x40007000\0" \"rdaddr=0x48000000\0" \"kerneladdr=0x40007000\0" \"ramdiskaddr=0x48000000\0" \"console=ttySAC2,115200n8\0" \"mmcdev=0\0" \"bootenv=uEnv.txt\0" \"dtb_addr=0x41000000\0" \"dtb_name=exynos4412-itop-4412.dtb\0" \"loadbootenv=load mmc ${mmcdev} ${loadaddr} ${bootenv}\0" \"bootargs=console=ttySAC2,115200n8 earlyprintk\0" \"importbootenv=echo Importing environment from mmc ...; " \"env import -t $loadaddr $filesize\0" \"loadbootscript=load mmc ${mmcdev} ${loadaddr} boot.scr\0" \"bootscript=echo Running bootscript from mmc${mmcdev} ...; " \"source ${loadaddr}\0"
#define CONFIG_BOOTCOMMAND \"if mmc rescan; then " \"echo SD/MMC found on device ${mmcdev};" \"if run loadbootenv; then " \"echo Loaded environment from ${bootenv};" \"run importbootenv;" \"fi;" \"if test -n $uenvcmd; then " \"echo Running uenvcmd ...;" \"run uenvcmd;" \"fi;" \"if run loadbootscript; then " \"run bootscript; " \"fi; " \"fi;" \"mmc read ${loadaddr} 0x1000 0x4000; mmc read ${dtb_addr} 0x800 0xa0; bootm ${loadaddr} - ${dtb_addr}" \"load mmc ${mmcdev} ${loadaddr} uImage; load mmc ${mmcdev} ${dtb_addr} ${dtb_name}; bootm ${loadaddr} - ${dtb_addr}"#define CONFIG_CLK_1000_400_200/* MIU (Memory Interleaving Unit) */
#define CONFIG_MIU_2BIT_21_7_INTERLEAVED#define CONFIG_SYS_MMC_ENV_DEV      0
#define CONFIG_ENV_SIZE         (8 << 10)   /* 16 KB */
#define RESERVE_BLOCK_SIZE      (512)
#define BL1_SIZE            (8 << 10) /*8 K reserved for BL1*/
#define BL2_SIZE            (16 << 10) /*16 K reserved for BL2 */
#define CONFIG_ENV_OFFSET       (RESERVE_BLOCK_SIZE + BL1_SIZE + BL2_SIZE)#define CONFIG_SPL_MAX_FOOTPRINT    (14 * 1024)#define CONFIG_SPL_STACK            0x02040000
#define UBOOT_SIZE                  (2 << 20)
#define CONFIG_SYS_INIT_SP_ADDR     (CONFIG_SYS_TEXT_BASE+UBOOT_SIZE-0x1000)/* U-Boot copy size from boot Media to DRAM. */
#define COPY_BL2_SIZE       0x80000
#define BL2_START_OFFSET    ((CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)/512)
#define BL2_SIZE_BLOC_COUNT (COPY_BL2_SIZE/512)#endif  /* __CONFIG_H */

（五）最后就是设备树文件的编写了

关于设备树文件的编写，网上也有很多资料可以查，我也就不详细说明了(其实我也不太懂，只是弄个大概，反正u-boot的能正常运行就ok了)，废话不多说，直接上代码，位置在arch/arm/dts/exynos4412-itop4412.dts

exynos4412-itop4412.dts

/** Odroid-U3/X2 board device tree source** Copyright (c) 2014 Samsung Electronics Co., Ltd.*      http://www.samsung.com** SPDX-License-Identifier: GPL-2.0+*//dts-v1/;
#include "exynos4412.dtsi"/ {model = "itop-4412 based on Exynos4412";compatible = "samsung,itop-4412", "samsung,exynos4412";aliases {i2c0 = "/i2c@13860000";i2c1 = "/i2c@13870000";i2c2 = "/i2c@13880000";i2c3 = "/i2c@13890000";i2c4 = "/i2c@138a0000";i2c5 = "/i2c@138b0000";i2c6 = "/i2c@138c0000";i2c7 = "/i2c@138d0000";serial0 = "/serial@13820000";console = "/serial@13820000";mmc2 = "sdhci@12530000";mmc4 = "dwmmc@12550000";};fimd@11c00000 {compatible = "samsung,exynos-fimd";reg = <0x11c00000 0xa4>;samsung,vl-freq = <60>;samsung,vl-col = <480>;samsung,vl-row = <272>;samsung,vl-width = <480>;samsung,vl-height = <272>;samsung,vl-clkp = <0>;samsung,vl-oep = <0>;samsung,vl-hsp = <1>;samsung,vl-vsp = <0>;samsung,vl-dp = <1>;samsung,vl-bpix = <4>;samsung,vl-hspw = <32>;samsung,vl-hbpd = <80>;samsung,vl-hfpd = <48>;samsung,vl-vspw = <2>;samsung,vl-vbpd = <1>;samsung,vl-vfpd = <13>;samsung,vl-cmd-allow-len = <0xf>;samsung,winid = <0>;samsung,power-on-delay = <30>;samsung,interface-mode = <1>;samsung,mipi-enabled = <0>;//samsung,dp-enabled;//samsung,dual-lcd-enabled;samsung,logo-on = <1>;samsung,resolution = <0>;samsung,rgb-mode = <1>;samsung,pwm-out-gpio  = <&gpd0 1 1>;samsung,bl-en-gpio = <&gpd0 0 1>;};mipidsi@11c80000 {compatible = "samsung,exynos-mipi-dsi";reg = <0x11c80000 0x5c>;samsung,dsim-config-e-interface = <1>;samsung,dsim-config-e-virtual-ch = <0>;samsung,dsim-config-e-pixel-format = <7>;samsung,dsim-config-e-burst-mode = <1>;samsung,dsim-config-e-no-data-lane = <3>;samsung,dsim-config-e-byte-clk = <0>;samsung,dsim-config-hfp = <1>;samsung,dsim-config-p = <3>;samsung,dsim-config-m = <120>;samsung,dsim-config-s = <1>;samsung,dsim-config-pll-stable-time = <500>;samsung,dsim-config-esc-clk = <20000000>;samsung,dsim-config-stop-holding-cnt = <0x7ff>;samsung,dsim-config-bta-timeout = <0xff>;samsung,dsim-config-rx-timeout = <0xffff>;samsung,dsim-device-id = <0xffffffff>;samsung,dsim-device-bus-id = <0>;samsung,dsim-device-reverse-panel = <1>;};i2c@13860000 {samsung,i2c-sda-delay = <100>;samsung,i2c-slave-addr = <0x10>;samsung,i2c-max-bus-freq = <100000>;status = "okay";max77686_pmic@09 {compatible = "maxim,max77686_pmic";interrupts = <7 0>;reg = <0x09 0 0>;#clock-cells = <1>;};};serial@13820000 {status = "okay";};sdhci@12510000 {status = "disabled";};sdhci@12520000 {status = "disabled";};sdhci@12530000 {samsung,bus-width = <4>;/*samsung,timing = <1 2 3>;*//*cd-gpios = <&gpk2 2 0>;*/status = "okay";};sdhci@12540000 {status = "disabled";};dwmmc@12550000 {samsung,bus-width = <4>;samsung,timing = <2 1 0>;samsung,removable = <0>;fifoth_val = <0x203f0040>;bus_hz = <400000000>;div = <0x3>;index = <4>;};ehci@12580000 {compatible = "samsung,exynos-ehci";reg = <0x12580000 0x100>;#address-cells = <1>;#size-cells = <1>;phy {compatible = "samsung,exynos-usb-phy";reg = <0x125B0000 0x100>;};};emmc-reset {compatible = "samsung,emmc-reset";reset-gpio = <&gpk1 2 0>;};
};

关于u-boot-2017.11版本在iTop-4412精英版的移植就大功告成了，（因为移植了好一段时间了，可能有些地方没写到，一切以源代码为准）

移植后的源代码
iTop-4412 精英版 u-boot-2017.11

以后有时间我会把linux-4.14.12在iTop-4412精英版的移植写出教程的
先大家看看移植后的截图