实验前准备：CPU学习实验的头文件.vh

代码来源：《CPU自制入门》

1.bus.vh

/*-- ============================================================================-- FILE NAME    : bus.h-- DESCRIPTION : Bus header-- ------------------------------------------------------------------------------ Revision  Date        Coding_by  Comment-- 1.0.0      2011/06/27  suito      Created-- ============================================================================
*/`ifndef __BUS_HEADER__`define __BUS_HEADER__             // Include gauard/********** Master *********/`define BUS_MASTER_CH      4     // The number of bus master channels`define BUS_MASTER_INDEX_W 2   // The width of bus master index/********** Bus owner *********/`define BusOwnerBus          1:0   // Status of bus owner`define BUS_OWNER_MASTER_0 2'h0     // Bus owner: Bus master 0`define BUS_OWNER_MASTER_1 2'h1     // Bus owner: Bus master 1`define BUS_OWNER_MASTER_2 2'h2     // Bus owner: Bus master 2`define BUS_OWNER_MASTER_3 2'h3     // Bus owner: Bus master 3/********** Bus slave *********/`define BUS_SLAVE_CH       8     // The number of bus slave channels`define BUS_SLAVE_INDEX_W  3    // The width of bus slave index`define BusSlaveIndexBus   2:0  // Status of bus slave`define BusSlaveIndexLoc   29:27 // Index of bus slave location`define BUS_SLAVE_0        0     // Bus slave 0`define BUS_SLAVE_1        1     // Bus slave 1`define BUS_SLAVE_2        2     // Bus slave 2`define BUS_SLAVE_3        3     // Bus slave 3`define BUS_SLAVE_4        4     // Bus slave 4`define BUS_SLAVE_5        5     // Bus slave 5`define BUS_SLAVE_6        6     // Bus slave 6`define BUS_SLAVE_7        7     // Bus slave 7`endif

2.cpu.vh

/* -- ============================================================================-- FILE NAME   : cpu.h-- DESCRIPTION : CPU header-- ------------------------------------------------------------------------------ Revision  Date        Coding_by  Comment-- 1.0.0      2011/06/27  suito      Created-- ============================================================================
*/`ifndef __CPU_HEADER__`define __CPU_HEADER__    // Include guard//------------------------------------------------------------------------------
// Operation
//------------------------------------------------------------------------------/********** Register **********/`define REG_NUM                 32   // Number of registers`define REG_ADDR_W          5    // Register address width`define RegAddrBus           4:0  // Register address bus/********** Interrupt request signal **********/`define CPU_IRQ_CH             8    // IRQ width/********** ALU opcode **********/// Bus`define ALU_OP_W          4    // ALU opcode width`define AluOpBus           3:0  // ALU opcode bus// Opcode`define ALU_OP_NOP          4'h0 // No Operation`define ALU_OP_AND            4'h1 // AND`define ALU_OP_OR          4'h2 // OR`define ALU_OP_XOR          4'h3 // XOR`define ALU_OP_ADDS            4'h4 // Signed ADD`define ALU_OP_ADDU             4'h5 // Unsigned ADD`define ALU_OP_SUBS           4'h6 // Signed SUB`define ALU_OP_SUBU             4'h7 // Unsigned SUB`define ALU_OP_SHRL           4'h8 // Shift right`define ALU_OP_SHLL            4'h9 // Shift left/********** MEM opcode **********/// Bus`define MEM_OP_W            2    // Memory opcode width`define MemOpBus            1:0  // Memory opcode bus// Opcode`define MEM_OP_NOP           2'h0 // No Operation`define MEM_OP_LDW            2'h1 // Read word`define MEM_OP_STW           2'h2 // Write word/********** Control opcode **********/// Bus`define CTRL_OP_W           2    // Control opcode width`define CtrlOpBus          1:0  // Control opcode bus// Opcode`define CTRL_OP_NOP             2'h0 // No Operation`define CTRL_OP_WRCR      2'h1 // Write to control register`define CTRL_OP_EXRT         2'h2 // Restore from exception/********** Execution mode **********/// Bus`define CPU_EXE_MODE_W      1    // Execution mode width`define CpuExeModeBus      0:0  // Execution mode bus// Opcode`define CPU_KERNEL_MODE         1'b0 // Kernel mode`define CPU_USER_MODE      1'b1 // User mode//------------------------------------------------------------------------------
// Control register
//------------------------------------------------------------------------------/********** Address map **********/`define CREG_ADDR_STATUS     5'h0  // Status`define CREG_ADDR_PRE_STATUS 5'h1  // Previous status`define CREG_ADDR_PC        5'h2  // Program counter`define CREG_ADDR_EPC         5'h3  // Exception program counter`define CREG_ADDR_EXP_VECTOR 5'h4  // Exception header`define CREG_ADDR_CAUSE         5'h5  // Exception cause register`define CREG_ADDR_INT_MASK   5'h6  // Interrupt mask`define CREG_ADDR_IRQ      5'h7  // Interrupt request// Read only region`define CREG_ADDR_ROM_SIZE   5'h1d // ROM size`define CREG_ADDR_SPM_SIZE   5'h1e // SPM size`define CREG_ADDR_CPU_INFO   5'h1f // CPU information/********** Bit map **********/`define CregExeModeLoc         0     // Execution mode location`define CregIntEnableLoc   1     // Interrupt enable location`define CregExpCodeLoc       2:0   // Exception code location`define CregDlyFlagLoc         3     // Delay slot flag location//------------------------------------------------------------------------------
// Bus interface
//------------------------------------------------------------------------------/********** Status of bus interface **********/// Bus`define BusIfStateBus      1:0   // Bus status// Status`define BUS_IF_STATE_IDLE  2'h0  // Idle`define BUS_IF_STATE_REQ     2'h1  // Bus request`define BUS_IF_STATE_ACCESS   2'h2  // Bus access`define BUS_IF_STATE_STALL     2'h3  // Stall//------------------------------------------------------------------------------
// MISC
//------------------------------------------------------------------------------/********** Header **********/`define RESET_VECTOR      30'h0 // Reset header/********** Shift amount **********/`define ShAmountBus          4:0   // Shift amount bus`define ShAmountLoc           4:0   // Shift amount location/********** CPU information *********/`define RELEASE_YEAR       8'd41 // YEAR (YYYY - 1970)`define RELEASE_MONTH      8'd7  // MONTH`define RELEASE_VERSION         8'd1  // VERSION`define RELEASE_REVISION  8'd0  // REVISION`endif

3.isa.vh

/* -- ============================================================================-- FILE NAME   : isa.h-- DESCRIPTION : Instruction set architecture-- ------------------------------------------------------------------------------ Revision  Date          Coding_by  Comment-- 1.0.0      2011/06/27  suito      Created-- ============================================================================
*/`ifndef __ISA_HEADER__`define __ISA_HEADER__             // Include Guard//------------------------------------------------------------------------------
// Instruction
//------------------------------------------------------------------------------/********** Instruction **********/`define ISA_NOP            32'h0 // No Operation/********** Opcode **********/// Bus`define ISA_OP_W         6     // Opcode width`define IsaOpBus          5:0   // Opcode bus`define IsaOpLoc        31:26 // Opcode location// Opcode`define ISA_OP_ANDR           6'h00`define ISA_OP_ANDI          6'h01`define ISA_OP_ORR           6'h02`define ISA_OP_ORI           6'h03`define ISA_OP_XORR          6'h04`define ISA_OP_XORI          6'h05`define ISA_OP_ADDSR     6'h06`define ISA_OP_ADDSI     6'h07`define ISA_OP_ADDUR     6'h08`define ISA_OP_ADDUI     6'h09`define ISA_OP_SUBSR     6'h0a`define ISA_OP_SUBUR     6'h0b`define ISA_OP_SHRLR     6'h0c`define ISA_OP_SHRLI     6'h0d `define ISA_OP_SHLLR    6'h0e`define ISA_OP_SHLLI     6'h0f`define ISA_OP_BE        6'h10`define ISA_OP_BNE           6'h11`define ISA_OP_BSGT          6'h12`define ISA_OP_BUGT          6'h13`define ISA_OP_JMP           6'h14`define ISA_OP_CALL          6'h15`define ISA_OP_LDW           6'h16`define ISA_OP_STW           6'h17`define ISA_OP_TRAP          6'h18`define ISA_OP_RDCR          6'h19`define ISA_OP_WRCR          6'h1a`define ISA_OP_EXRT          6'h1b/********** Register address **********/// Bus`define ISA_REG_ADDR_W     5     // Register address width`define IsaRegAddrBus       4:0   // Register address bus`define IsaRaAddrLoc      25:21 // Register Ra location`define IsaRbAddrLoc      20:16 // Register Rb location`define IsaRcAddrLoc      15:11 // Register Rc location/********** Immediate **********/// Bus`define ISA_IMM_W          16    // Immediate width`define ISA_EXT_W          16    // Immediate sign extension width`define ISA_IMM_MSB         15    // Immediate MSB`define IsaImmBus        15:0  // Immediate bus`define IsaImmLoc        15:0  // Immediate location//------------------------------------------------------------------------------
// Exception
//------------------------------------------------------------------------------/********** Exception code **********/// Bus`define ISA_EXP_W         3     // Exception width`define IsaExpBus          2:0   // Exception code bus// Exception`define ISA_EXP_NO_EXP      3'h0     // No exception`define ISA_EXP_EXT_INT       3'h1     // External interrupt`define ISA_EXP_UNDEF_INSN 3'h2  // Undefined instruction`define ISA_EXP_OVERFLOW   3'h3   // Arithmetic overflow`define ISA_EXP_MISS_ALIGN 3'h4     // Address misalign`define ISA_EXP_TRAP      3'h5     // Trap`define ISA_EXP_PRV_VIO       3'h6     // Permission violate`endif

4.spm.vh

/*-- ============================================================================-- FILE NAME    : spm.h-- DESCRIPTION : Scratchpad memory header-- ------------------------------------------------------------------------------ Revision  Date          Coding_by  Comment-- 1.0.0      2011/06/27  suito      Created-- ============================================================================
*/`ifndef __SPM_HEADER__`define __SPM_HEADER__              // Include guard/**  PM size calculation example:* If SPM's size is 16384Byte = 16KB,*   SPM_DEPTH is 16384 / 4 = 4096,*    SPM_ADDR_W is log2(4096) = 12.*/`define SPM_SIZE   16384 // SPM's size`define SPM_DEPTH  4096   // SPM's depth`define SPM_ADDR_W 12   // address width`define SpmAddrBus 11:0    // Address bus`define SpmAddrLoc 11:0  // Address location`endif

5.rom.vh

/*-- ============================================================================-- FILE NAME    : rom.h-- DESCRIPTION : ROM header-- ------------------------------------------------------------------------------ Revision  Date        Coding_by  Comment-- 1.0.0      2011/06/27  suito      Created-- ============================================================================
*/`ifndef __ROM_HEADER__`define __ROM_HEADER__              // Include guard/**  ROM's size calculation example:*   If ROM is 8192Byte = 4KB, then*  ROM_DEPTH is 8192 / 4 = 2048, *    ROM_ADDR_W is log2(2048) = 11.*/`define ROM_SIZE   8192  // ROM's size`define ROM_DEPTH  2048  // ROM's depth`define ROM_ADDR_W 11   // Address width`define RomAddrBus 10:0 // Address bus`define RomAddrLoc 10:0 // Address location`endif

6.global_config.vh

/*-- ============================================================================-- FILE NAME    : global_config.h-- DESCRIPTION : Global configuration-- ------------------------------------------------------------------------------ Revision  Date        Coding_by  Comment-- 1.0.0      2011/06/27  suito      Created-- ============================================================================
*/`ifndef __GLOBAL_CONFIG_HEADER__`define __GLOBAL_CONFIG_HEADER__    // Include guard//------------------------------------------------------------------------------
// Setup
//------------------------------------------------------------------------------/********** Target device (choose one) **********/
//  `define TARGET_DEV_MFPGA_SPAR3E        // Marutsu evaluation board`define TARGET_DEV_AZPR_EV_BOARD    // AZPR original board/********** Polarity of reset (choose one) **********/
//  `define POSITIVE_RESET             // Active High`define NEGATIVE_RESET               // Active Low/********** Polarity of memory ctrl signal (choose one) **********/`define POSITIVE_MEMORY                // Active High
//  `define NEGATIVE_MEMORY                // Active Low/********** I/O setup : setup I/O for implementation**********/`define IMPLEMENT_TIMER                // Timer//`define IMPLEMENT_UART               // UART`define IMPLEMENT_GPIO              // General Purpose I/O//------------------------------------------------------------------------------
// Generate parameters according to setup
//------------------------------------------------------------------------------/********** Polarity of reset *********/// Active Low`ifdef POSITIVE_RESET`define RESET_EDGE    posedge   // Reset edge`define RESET_ENABLE  1'b1       // Reset enable`define RESET_DISABLE 1'b0     // Reset disable`endif// Active High`ifdef NEGATIVE_RESET`define RESET_EDGE    negedge   // Reset edge`define RESET_ENABLE  1'b0       // Reset enable`define RESET_DISABLE 1'b1     // Reset disable`endif/********** Polarity of memory ctrl signal *********/// Actoive High`ifdef POSITIVE_MEMORY`define MEM_ENABLE     1'b1     // Memory enable`define MEM_DISABLE      1'b0     // Memory disable`endif// Active Low`ifdef NEGATIVE_MEMORY`define MEM_ENABLE   1'b0     // Memory enable`define MEM_DISABLE      1'b1     // Memory disable`endif`endif

7.nettype.vh

/*-- ============================================================================-- FILE NAME    : nettype.h-- DESCRIPTION : Default net type-- ------------------------------------------------------------------------------ Revision  Date          Coding_by  Comment-- 1.0.0      2011/04/26  suito      Created-- ============================================================================
*/`ifndef __NETTYPE_HEADER__      // Include guard`define __NETTYPE_HEADER__/********** Default net type: choose one **********/`default_nettype none       // none (Recommend)
//  `default_nettype wire     // wire (Verilog standard)`endif

8.stddef.vh

/*-- ============================================================================-- FILE NAME    : stddef.h-- DESCRIPTION : Global macro-- ------------------------------------------------------------------------------ Revision  Date       Coding_by  Comment-- 1.0.0      2011/04/01  suito      Created-- ============================================================================
*/`ifndef __STDDEF_HEADER__                 // Include guard`define __STDDEF_HEADER__// -----------------------------------------------------------------------------
// Value of signal
// -----------------------------------------------------------------------------/********** Signal level *********/`define HIGH                1'b1    // High level`define LOW                  1'b0    // Low level/********** Enable/Disable *********/// Positive logic `define DISABLE                1'b0`define ENABLE                1'b1// Negative logic`define DISABLE_         1'b1`define ENABLE_               1'b0/********** Read/Write *********/`define READ             1'b1`define WRITE             1'b0// -----------------------------------------------------------------------------
// Data bus
// -----------------------------------------------------------------------------/********** Least significant bit *********/`define LSB                    0/********** Byte (8 bit) *********/`define BYTE_DATA_W            8        // Data width`define BYTE_MSB         7        // Most significant bit`define ByteDataBus            7:0      // Data bus/********** Word (32 bit) *********/`define WORD_DATA_W            32       // Data width`define WORD_MSB         31       // Most significant bit`define WordDataBus            31:0         // Data bus// -----------------------------------------------------------------------------
// Address bus
// -----------------------------------------------------------------------------/********** Word address *********/`define WORD_ADDR_W         30       // Address width`define WORD_ADDR_MSB     29       // Most significant bit`define WordAddrBus            29:0     // Address bus/********** Byte offset *********/`define BYTE_OFFSET_W     2        // Offset width`define ByteOffsetBus      1:0      // Offset bus/********** Address location *********/`define WordAddrLoc           31:2     // Word address location`define ByteOffsetLoc     1:0      // Byte offset location/********** Value of byte offset *********/`define BYTE_OFFSET_WORD    2'b00   // Word boundary`endif

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实验前准备：CPU学习实验的头文件.vh

代码来源：《CPU自制入门》

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