基于小梅哥所提的线性序列机思想设计读写该芯片的SPI协议，线性序列机简单来说就是用一个计数器对时钟计数，对于每一个计数值，按照时序要求对信号做出相应操作。简单写了一下 Read Manufacturer / Device ID (90h) 指令，需要先发送0x90（一字节），接着发送地址0x000000（三字节），再接收Manufacturer ID 和Device ID 两字节，接收正确的话分别是0xEF和0x14。芯片手册的指令说明及时序图如下。

按照时序图一步一步写即可，程序如下，已经验证。

module spi_dri(input wire sys_clk,input wire rst_n,input wire start,input wire [7:0] instruct,input wire [23:0] addr,output reg spi_clk,output reg spi_cs_n,output reg spi_mosi,input wire spi_miso,output reg work_done,output reg [7:0] manu_id,output reg [7:0] device_id
);reg [7:0] r_manu_id;
reg [7:0] r_device_id;reg work_ing;
reg [9:0] cnt_sysclk;always@(posedge sys_clk or negedge rst_n)if(!rst_n)work_ing <= 1'b0;else if(start)work_ing <= 1'b1;else if(work_done)work_ing <= 1'b0;elsework_ing <= work_ing;always@(posedge sys_clk or negedge rst_n)if(!rst_n)cnt_sysclk <= 10'b0;else if(work_ing)cnt_sysclk <= cnt_sysclk + 1'b1;else if(cnt_sysclk == 10'd97)cnt_sysclk <= 10'b0;elsecnt_sysclk <= cnt_sysclk;always@(posedge sys_clk or negedge rst_n)if(!rst_n)beginspi_cs_n <= 1'b1;spi_clk <= 1'b0;spi_mosi <= 1'b1;r_device_id <= 8'd0;r_manu_id <= 8'd0;device_id <= 8'd0;manu_id <= 8'd0;work_done <= 1'b0;endelse begincase(cnt_sysclk)0:begin spi_cs_n <= 1'b0; spi_clk <= 1'b0; spi_mosi <= instruct[7]; end1:begin spi_clk <= 1'b1; end2:begin spi_clk <= 1'b0; spi_mosi <= instruct[6]; end3:begin spi_clk <= 1'b1; end4:begin spi_clk <= 1'b0; spi_mosi <= instruct[5]; end5:begin spi_clk <= 1'b1; end6:begin spi_clk <= 1'b0; spi_mosi <= instruct[4];end7:begin spi_clk <= 1'b1; end8:begin spi_clk <= 1'b0; spi_mosi <= instruct[3];end9:begin spi_clk <= 1'b1; end10:begin spi_clk <= 1'b0; spi_mosi <= instruct[2];end11:begin spi_clk <= 1'b1; end12:begin spi_clk <= 1'b0; spi_mosi <= instruct[1];end13:begin spi_clk <= 1'b1; end14:begin spi_clk <= 1'b0; spi_mosi <= instruct[0];end15:begin spi_clk <= 1'b1; end16:begin spi_clk <= 1'b0; spi_mosi <= addr[23]; end17:begin spi_clk <= 1'b1; end18:begin spi_clk <= 1'b0; spi_mosi <= addr[22]; end19:begin spi_clk <= 1'b1; end20:begin spi_clk <= 1'b0; spi_mosi <= addr[21]; end21:begin spi_clk <= 1'b1; end22:begin spi_clk <= 1'b0; spi_mosi <= addr[20];end23:begin spi_clk <= 1'b1; end24:begin spi_clk <= 1'b0; spi_mosi <= addr[19];end25:begin spi_clk <= 1'b1; end26:begin spi_clk <= 1'b0; spi_mosi <= addr[18];end27:begin spi_clk <= 1'b1; end28:begin spi_clk <= 1'b0; spi_mosi <= addr[17];end29:begin spi_clk <= 1'b1; end30:begin spi_clk <= 1'b0; spi_mosi <= addr[16]; end31:begin spi_clk <= 1'b1; end32:begin spi_clk <= 1'b0; spi_mosi <= addr[15]; end33:begin spi_clk <= 1'b1; end34:begin spi_clk <= 1'b0; spi_mosi <= addr[14]; end35:begin spi_clk <= 1'b1; end36:begin spi_clk <= 1'b0; spi_mosi <= addr[13];end37:begin spi_clk <= 1'b1; end38:begin spi_clk <= 1'b0; spi_mosi <= addr[12];end39:begin spi_clk <= 1'b1; end40:begin spi_clk <= 1'b0; spi_mosi <= addr[11];end41:begin spi_clk <= 1'b1; end42:begin spi_clk <= 1'b0; spi_mosi <= addr[10];end43:begin spi_clk <= 1'b1; end44:begin spi_clk <= 1'b0; spi_mosi <= addr[9]; end45:begin spi_clk <= 1'b1; end46:begin spi_clk <= 1'b0; spi_mosi <= addr[8]; end47:begin spi_clk <= 1'b1; end48:begin spi_clk <= 1'b0; spi_mosi <= addr[7]; end49:begin spi_clk <= 1'b1; end50:begin spi_clk <= 1'b0; spi_mosi <= addr[6];end51:begin spi_clk <= 1'b1; end52:begin spi_clk <= 1'b0; spi_mosi <= addr[5];end53:begin spi_clk <= 1'b1; end54:begin spi_clk <= 1'b0; spi_mosi <= addr[4];end55:begin spi_clk <= 1'b1; end56:begin spi_clk <= 1'b0; spi_mosi <= addr[3];end57:begin spi_clk <= 1'b1; end58:begin spi_clk <= 1'b0; spi_mosi <= addr[2]; end59:begin spi_clk <= 1'b1; end60:begin spi_clk <= 1'b0; spi_mosi <= addr[1]; end61:begin spi_clk <= 1'b1; end62:begin spi_clk <= 1'b0; spi_mosi <= addr[0]; end63:begin spi_clk <= 1'b1; end64:begin spi_clk <= 1'b0; end65:begin spi_clk <= 1'b1; r_manu_id[7] <= spi_miso; end66:begin spi_clk <= 1'b0; end67:begin spi_clk <= 1'b1; r_manu_id[6] <= spi_miso; end68:begin spi_clk <= 1'b0; end69:begin spi_clk <= 1'b1; r_manu_id[5] <= spi_miso; end70:begin spi_clk <= 1'b0; end71:begin spi_clk <= 1'b1; r_manu_id[4] <= spi_miso; end72:begin spi_clk <= 1'b0; end73:begin spi_clk <= 1'b1; r_manu_id[3] <= spi_miso; end74:begin spi_clk <= 1'b0; end75:begin spi_clk <= 1'b1; r_manu_id[2] <= spi_miso; end76:begin spi_clk <= 1'b0; end77:begin spi_clk <= 1'b1; r_manu_id[1] <= spi_miso; end78:begin spi_clk <= 1'b0; end79:begin spi_clk <= 1'b1; r_manu_id[0] <= spi_miso; manu_id <= r_manu_id; end80:begin spi_clk <= 1'b0; end81:begin spi_clk <= 1'b1; r_device_id[7] <= spi_miso;end82:begin spi_clk <= 1'b0;  end83:begin spi_clk <= 1'b1; r_device_id[6] <= spi_miso;end84:begin spi_clk <= 1'b0; end85:begin spi_clk <= 1'b1; r_device_id[5] <= spi_miso; end86:begin spi_clk <= 1'b0; end87:begin spi_clk <= 1'b1; r_device_id[4] <= spi_miso; end88:begin spi_clk <= 1'b0; end89:begin spi_clk <= 1'b1; r_device_id[3] <= spi_miso; end90:begin spi_clk <= 1'b0;end91:begin spi_clk <= 1'b1; r_device_id[2] <= spi_miso;  end92:begin spi_clk <= 1'b0;  end93:begin spi_clk <= 1'b1;r_device_id[1] <= spi_miso; end94:begin spi_clk <= 1'b0;   end95:begin spi_clk <= 1'b1; r_device_id[0] <= spi_miso;device_id <= r_device_id;end96:begin spi_cs_n <= 1'b1; work_done <= 1'b1; enddefault:;endcaseendendmodule