DM6437定时器的使用

    64bit模式：

    1、芯片复用引脚设置

    2、设置VDD3P3V_PWDN寄存器

    3、在TCR寄存器中设置CLKSRC位选择时钟来源于外部时钟还是内部时钟（27MHZ）

    4、设置TCR寄存器中的CP位，选择输出模式（脉冲还是clock）

    5、设置TCR寄存器中的PWID位，设置脉冲宽度

    6、设置TINP0SEL bit in TIMERCTL，选择外部输入时钟是否需要6分频

    7、Consider inverter requirements (INVINP and INVOUTP bits in TCR)

    8、选择 64-bit 模式 (TIMMODE bit in TGCR)

    9、Remove the timer from reset (TIM12RS and TIM34RS bits in TGCR)

    10、选择所需要的定时周期 (PRD12 and PRD34).

    11、使能定时器 (ENAMODE12 bit field in TCR).

    32bit链模式：（设置 TIMMODE bit to 3h in TGCR）

    使用TIM12，TIM34，PRD34，PRD12寄存器。

    TIM34计数，一旦达到PRD34设置的值得时候，产生一个信号同时TIM34清零从新开始，并且TIM12加1，当达到PRD12设置的值得时候产生一个TINTLn中断信号，以及一个定时器EDMA事件信号TEVTLn，产生一个输出信号TOUT。此时当定时器设置为连续模式的时候计数器值复位从新开始又一次循环。定时器可以使用 TIM12RS and TIM34RS bits in TGCR来停止，重启，复位，禁用。在链模式下定时器控制寄存器（TCR）的高16位不使用。

配置如下：

1.设置引脚复用功能
2. Program the VDD3P3V_PWDN register to power up the IO pins for Timer 0 and Timer 1
3. 设置时钟源 (CLKSRC bit in TCR).
4. 设置输出模式 (CP bit in TCR).
5. 选择输出脉冲宽度(PWID bit in TCR).
6. 外部时钟输入时选择是否需要6分频 (TINP0SEL bit in TIMERCTL in system module).
7. 是否需要反向(INVINP and INVOUTP bits in TCR).
8. Select 32-bit chained mode (TIMMODE bit in TCR).
9. Remove the timer from reset (TIM12RS and TIM34RS bits in TGCR).
10. 设置周期 (PRD12).
11. Select the desired timer prescaler value (PRD34).
12. 使能定时器(ENAMODE12 bit field in TCR).

32位非链模式：（setting the TIMMODE bit to 1 in TGCR）

在此模式下会产生两个32bit独立的定时器，(Timer 3:4) operates as a 32-bit timer being clocked by a 4-bit prescaler. The other 32-bit timer (Timer 1:2) operates as a 32-bit timer with no prescaler.

配置如下：

1. 设置引脚复用
2. 设置 VDD3P3V_PWDN 寄存器
3. 选择输出模式 (CP bit in TCR).
4. 选择脉冲宽度(PWID bit in TCR).
5. 外部时钟输入是否6分频 (TINP0SEL bit in TIMERCTL in system module).
6. 输出反向 (INVINP and INVOUTP bits in TCR).
7. 设置32bit非链模式 (TIMMODE bit in TGCR).
8. Remove the Timer 1:2 from reset (TIM12RS bit in TGCR).
9. 选择时钟周期Timer 1:2 (PRD12).
10. 选择时钟源 Timer 1:2 (CLKSRC12 bit in TCR).
11. 时能 Timer 1:2 (ENAMODE12 bit field in TCR).
配置Timer 3:4, 如下:
1. 选择32bit非链模式 (TIMMODE bit in TGCR).

2. Remove the Timer 3:4 from reset (TIM34RS bit in TGCR).
3. 选择时钟周期Timer 3:4 (PRD34).
4. Select the desired prescaler value for Timer 3:4 (PSC34 bit in TGCR).
5. 使能Timer 3:4 (ENAMODE34 bit field in TCR).

代码功能：

使用TIMER0产生cpu中断INT4.  TIMER0 配置成32bit非链一次执行模式，事件映射到CPU 中断 4.程序验证定时器到达周期时中断服务程序执行，在非bios的模式下。

/*  ============================================================================*   Copyright (c) Texas Instruments Inc 2002, 2003, 2004, 2005, 2006, 2007**   Use of this software is controlled by the terms and conditions found*   in the license agreement under which this software has been supplied.*  ============================================================================*//** ============================================================================*  @brief  A simple example to demonstrate CSL 3.x register layer *   usage and interrupts.  **  @file  interrupt_example.c**  <b> Example description </b> *  @verbatimThe interrupt example is a non-bios example that uses TIMER0 to generate cpu INT4.  TIMER0 is configured in 32bit unchained once mode and its event is mapped CPU interrupt 4.  The test enables TIMER0 and verifies that the interrupt service routine is executed when the period value is reached.  A pass/fail status is returned to main.@endverbatim*   *   *  @n <b> Procedure to run the example </b>*  @verbatim1. Configure the CCS setup to work with the emulator being used.2. Please refer CCS manual for setup configuration and loading proper GEL file.3. Launch CCS.4. Open project Intc_example.pjt.5. Build the project and load the .out file for the project.@endverbatim**  ============================================================================**/#include <stdio.h>
#include <soc.h>
#include <c6x.h>
#include <cslr_intc.h>
#include <cslr_tmr.h>
#include <cslr_psc.h>
#include <cslr_sys.h>static void setup(void);
static int test_interrupt(void);
extern void intcVectorTable(void);
static void device_init(void);const unsigned int TIMER_PERIOD = 0x00006978;  // timer period setting
int intFlag=1;                                 // interrupt flag CSL_TmrRegsOvly tmr0Regs = (CSL_TmrRegsOvly)CSL_TMR_0_REGS;
CSL_IntcRegsOvly intcRegs = (CSL_IntcRegsOvly)CSL_INTC_0_REGS;int main (void)
{// enable TIMER0 in MUX and PSCdevice_init();     // setup TIMER0 and interrupt  setup();// test interrupt, returns 0 for pass and 1 for fail return(test_interrupt());
}void setup(void)
{// clear TIM12 register                 CSL_FINST(tmr0Regs->TIM12,TMR_TIM12_TIM12,RESETVAL);// select 32 bit unchained mode and take the timer out of resettmr0Regs->TGCR = CSL_FMKT(TMR_TGCR_TIMMODE,32BIT_UNCHAIN)| CSL_FMKT(TMR_TGCR_TIM12RS,NO_RESET);// set TIMER0 PRD1:2CSL_FINS(tmr0Regs->PRD12,TMR_PRD12_PRD12,TIMER_PERIOD);// map TIMER0 event to cpu int4CSL_FINS(intcRegs->INTMUX1, INTC_INTMUX1_INTSEL4,TIMER0_EVENT); // set ISTP to point to the vector table addressISTP = (unsigned int)intcVectorTable;// clear all interrupts, bits 4 thru 15ICR = 0xFFF0; // enable the bits for non maskable interrupt and CPUINT4 */IER |= 0x12; // enable interrupts, set GIE bit _enable_interrupts();
}int test_interrupt(void)
{printf("\nTesting CPU Interrupt 4 using TIMER0\n");// enable TIMER0 1:2 side, once modeCSL_FINST(tmr0Regs->TCR,TMR_TCR_ENAMODE12,EN_ONCE);printf("\nStarting TIMER0\n");// wait for TIMER0 to run to the period value and reset countwhile(CSL_FEXT(tmr0Regs->TIM12,TMR_TIM12_TIM12)!=0x0);if(intFlag!=0){printf("Error\n");printf("\nInterrupt test:  FAILED\n");} elseprintf("\nInterrupt test:  PASSED\n"); return(intFlag);
}interrupt void interrupt4(void)
{// disable TIMER0 1:2 sideCSL_FINST(tmr0Regs->TCR,TMR_TCR_ENAMODE12,DISABLE); // set the interrupt flag  intFlag=0;
}void device_init(void)
{CSL_PscRegsOvly pscRegs = (CSL_PscRegsOvly)CSL_PSC_0_REGS;CSL_SysRegsOvly sysRegs = (CSL_SysRegsOvly)CSL_SYS_0_REGS;// enable TIMER0 in the PINMUX1 register

//使能time0sysRegs->PINMUX1 |= CSL_FMK(SYS_PINMUX1_TIM0BK,1);  // ensure TIMER0 is powered

//io口电源设置sysRegs->VDD3P3V_PWDN |= CSL_FMKT(SYS_VDD3P3V_PWDN_TIMER0,POWERUP);// deassert TIMER0 local PSC reset and set NEXT state to ENABLEpscRegs->MDCTL[CSL_PSC_TIMER0] = CSL_FMKT( PSC_MDCTL_NEXT, ENABLE ) | CSL_FMKT( PSC_MDCTL_LRST, DEASSERT );// move TIMER0 PSC to Next statepscRegs->PTCMD = CSL_FMKT(  PSC_PTCMD_GO0, SET );// wait for transitionwhile ( CSL_FEXT( pscRegs->MDSTAT[CSL_PSC_TIMER0], PSC_MDSTAT_STATE )!= CSL_PSC_MDSTAT_STATE_ENABLE );
}

说明：以上代码是在非bios模式下，使用TI的CSLR来完成的