一直不清楚FPGA中Speed Grade的可选值的大小于FPGA速率是成正比还是反比关系,我对其不解如下文中的提问者,所以今天GOOGLE了一下,找到答案,如下英文。简单的说FPGA的speed grade是一个相对标准,在现代版的(XILINX) FPGA 中,Speed Grade的值越大其速率越高,具体说详解下文(回答问题的2人均为Xilinx的员工):

ASK:

Can anyone please explain what a speed grade is?
If i tell you my bicycle has a speed grade of 29, you'll probably say something like: "Good for you.", but you wouldn't have a clue about what i just said.
So, can you explain to me how i should see the speed grades.
What do they stand for?
Who defines the speed grades?
Can i compare the speed grades between manufacturers?

I can't seem to be able to find anything about the subject anywhere...

ANSWER 1:

There is no consistent definition of a speed grade for all devices. Even for Xilinx, speed grades mean different things depending on if you are referring to a FPGA or a CPLD. For CPLDs, speed grades represent the time it takes for logic to go through the device (eg. in <= out). So a -10 device means that the device is guaranteed to send a signal from an input pin thru to an output pin in under 10 nS. So for CPLDs, the lower the number, the faster the part is. This is standard for CPLDs across all vendors so this can be used for device comparison purposes.

However for FPGAs, they don't use the same definition for speed grade. Originally speed grades for FPGAs represented the time through a look up table but now the speed grade doesn't actually repesent a timing path. I am not sure if it is the same for other vendors, but for Xilinx FPGAs higher numbers are faster. Each speed grade increment is ~15% faster than the one before it. So a -5 is 10% faster than a -4 speed grade.

Arthur

ANSWER 2:

As Arthur indicated, it is a relative term that is really dependent on the specific family:
-for CPLDs, it is generally pin-to-pin delays in nanoseconds (lower # = faster)
-for old Xilinx FPGAs (pre-Virtex), lower # was faster
-for modern (Virtex and later) FPGAs, the higher # is faster.
The speed grade influences a variety of timing paramters in the FPGA, including fabric (slice), multiplier/DSP48x, BlockRAM, I/O, and other resources parameters.
You really need to consult the specific datasheet to see specific details for timing based on associated speed grades.
For example, Virtex-4 speed grades are -10 (slowest), -11, and -12 (fatest)
Virtex-5 spede grades are -1 (slowest), -2, and -3 (fastest)
There is no correlation between these numbers. It is really a relative metric of performance within a specific family.
Cheers,
原文地址http://blog.csdn.net/code_robot/article/details/6980961

关于FPGA中Speed Grade的说明相关推荐

  1. FPGA速度等级问题(Speed Grade)

    =============================== FPGA的速度等级(speed grade)(1) XILINX公司FPGASpartan 3E系列XC3S500E速度等级为4.但一直 ...

  2. (转)FPGA的速度等级(speed grade)

    2008-06-06 17:04 XILINX公司FPGASpartan 3E系列XC3S500E速度等级为4.但一直不知道是什么意思. 通过学习知道, (1)CPLD与FPGA的速度等级定义的区别 ...

  3. fpga 速度等级(speed grade)

    xilinx fpga 速度等级(speed grade): 数值越大,芯片性能越好,能支持的代码处理速度越高,且能更好的处理复杂代码实现过程,不用太多的时序约束干预.反之,数值越小,芯片性能越差,能 ...

  4. FPGA的速度等级(speed grade)

    1.  对于Xilinx的 CPLDs来说,值越小,速度越高: 2.  对于Xilinx FPGAs 来说,值越大,速度越高. Each speed grade increment is ~15% f ...

  5. Speed Grade——芯片的“速度等级”初探(转)

    最初接触speed grade这个概念时,很是为Altera的-6.-7.-8速度等级逆向排序的方法困惑过一段时间.不很严密地说,"序号越低,速度等级越高"这是Altera FPG ...

  6. speed grade的选择

    定制pll时,要选择"which device speed grade will you be using",这是芯片速度等级的选择,依据是芯片型号最后一位数.如EP4CE15F1 ...

  7. FPGA中LVDS差分高速传输的实现

    低压差分传送技术是基于低压差分信号(Low Volt-agc Differential signaling)的传送技术,从一个电路板系统内的高速信号传送到不同电路系统之间的快速数据传送都可以应用低压差 ...

  8. FPGA中的Logic Cells, Logic Slices, Configurable Logic Blocks and Gates 的定义

    一个逻辑单元(logic cell) 包含了一个查找表,一个触发器和与附近单元的连接电路.查找表使用组合逻辑实现了一个4输入的逻辑表达式(与,或,与非,加等). 一个逻辑片(logic slice)  ...

  9. FPGA中实现对数运算

    FPGA中实现对数运算主要有三种方法: (1)在外部直接算好对数值,按照数值范围做个表,存在ram里,到时候查表.为了减少表深度,提高资源利用率,可以考虑去掉部分低位数值,损失一定的精度. (2)使用 ...

最新文章

  1. R3模擬器版本預覽一下。。暫時沒帶QQ....
  2. 奇小葩讲设备树(3/5)-- Linux设备树详解(三)u-boot设备树的传递
  3. ai背景合成_智能合成AI主播很危险,应立即取消!
  4. Angular使用Console.log()打印出来的数据没问题,点击详情后数据变了
  5. LeetCode 1837. K 进制表示下的各位数字总和
  6. MYSQL返回指定时间间隔函数DATE_SUB和TO_DAYS详解
  7. 基于mysql搭建框架环境搭建_Maven+Spring+Spring MVC+MyBatis+MySQL,搭建SSM框架环境
  8. Pentium II Pentium III架构/微架构/流水线 (1) - 架构概述
  9. [C/C++] String Reverse 字符串 反转
  10. 拓端tecdat|使用OpenCV在Python中进行图像处理
  11. VS2015安装VBpowerpacks工具箱教程
  12. matlab及机器学习
  13. Mac 利用 Chrome 下载所有网页上的视频
  14. 【C进阶】之动态内存分配及内存操作函数
  15. Picture of my baby when 2 monthes old_拔剑-浆糊的传说_新浪博客
  16. 推流式搅拌器选型功率计算方法_不同池形中推流搅拌器功率消耗的数值模拟
  17. LSTM长短期记忆人工神经网络简述
  18. 洛谷 P2015 二叉苹果树 题解
  19. openxml操作word的基本应用
  20. 分枝定界法求哈密尔登回路问题的由表及里

热门文章

  1. 使用Git进行代码版本管理
  2. matlab 滤波器设计 coe_现代雷达系统分析与设计
  3. 中国科学院大学 张云华老师 现代雷达系统课件
  4. 架构:多源异构数据。
  5. CTA-861标准解析EDID的VSDB与VDB
  6. 0欧姆电阻的一些用处
  7. 老蜗牛写采集:网络爬虫(二)
  8. 小程序运行报错:“pages/xxx/xxx.js 出现脚本错误或者未正确调用 Page()
  9. 特别记事本这款文字编辑器怎么样
  10. UTC时间与当地时间