-- textio.vhdllibrary std; use std.standard.all;    -- needed for bootstrap modepackage TEXTIO is-- Type Definitions for Text I/Otype LINE is access STRING;    -- a line is a pointer to a STRING valuetype TEXT is file of STRING;    -- a file of variable-length ASCII recordstype SIDE is (RIGHT, LEFT);    -- for justifying output data within fieldssubtype WIDTH is NATURAL;    -- for specifying widths of output fields-- Standard Text Filesfile INPUT: TEXT open READ_MODE is "STD_INPUT";file OUTPUT: TEXT open WRITE_MODE is "STD_OUTPUT";-- Input Routines for Standard Typesprocedure READLINE (file F: TEXT; L: inout LINE);procedure READ (L: inout LINE; VALUE: out BIT; GOOD: out BOOLEAN);procedure READ (L: inout LINE; VALUE: out BIT);procedure READ (L: inout LINE; VALUE: out BIT_VECTOR; GOOD: out BOOLEAN);procedure READ (L: inout LINE; VALUE: out BIT_VECTOR);procedure READ (L: inout LINE; VALUE: out BOOLEAN; GOOD: out BOOLEAN);procedure READ (L: inout LINE; VALUE: out BOOLEAN);procedure READ (L: inout LINE; VALUE: out CHARACTER; GOOD: out BOOLEAN);procedure READ (L: inout LINE; VALUE: out CHARACTER);procedure READ (L: inout LINE; VALUE: out INTEGER; GOOD: out BOOLEAN);procedure READ (L: inout LINE; VALUE: out INTEGER);procedure READ (L: inout LINE; VALUE: out REAL; GOOD: out BOOLEAN);procedure READ (L: inout LINE; VALUE: out REAL);procedure READ (L: inout LINE; VALUE: out STRING; GOOD: out BOOLEAN);procedure READ (L: inout LINE; VALUE: out STRING);procedure READ (L: inout LINE; VALUE: out TIME; GOOD: out BOOLEAN);procedure READ (L: inout LINE; VALUE: out TIME);-- Output Routines for Standard Typesprocedure WRITELINE (file F: TEXT; L: inout LINE);procedure WRITE (L: inout LINE; VALUE: in BIT;JUSTIFIED: in SIDE := RIGHT; FIELD: in WIDTH := 0);procedure WRITE (L: inout LINE; VALUE: in BIT_VECTOR;JUSTIFIED: in SIDE := RIGHT; FIELD: in WIDTH := 0);procedure WRITE (L: inout LINE; VALUE: in BOOLEAN;JUSTIFIED: in SIDE := RIGHT; FIELD: in WIDTH := 0);procedure WRITE (L: inout LINE; VALUE: in CHARACTER;JUSTIFIED: in SIDE := RIGHT; FIELD: in WIDTH := 0);procedure WRITE (L: inout LINE; VALUE: in INTEGER;JUSTIFIED: in SIDE := RIGHT; FIELD: in WIDTH := 0);procedure WRITE (L: inout LINE; VALUE: in REAL;JUSTIFIED: in SIDE := RIGHT; FIELD: in WIDTH := 0;DIGITS: in NATURAL := 0);procedure WRITE (L: inout LINE; VALUE: in STRING;JUSTIFIED: in SIDE := RIGHT; FIELD: in WIDTH := 0);procedure WRITE (L: inout LINE; VALUE: in TIME;JUSTIFIED: in SIDE := RIGHT; FIELD: in WIDTH := 0;UNIT: in TIME := ns);-- File Position Predicatesfunction ENDLINE (L: in LINE) return BOOLEAN;end TEXTIO;

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_signed.all;entity Add2In isport( D1        : in std_logic_vector(7 downto 0);D2        : in std_logic_vector(7 downto 0);Q         : out std_logic_vector(8 downto 0);Clk    : in std_logic);
end entity;architecture beha of Add2In is
begin process(Clk)beginif Clk'event and Clk = '1' thenQ <= ('0' & D1) + D2;end if;    end process;
end beha;

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_signed.all;
USE std.textio.all;ENTITY Add2In_vhd_tst IS
END Add2In_vhd_tst;
ARCHITECTURE Add2In_arch OF Add2In_vhd_tst ISSIGNAL Clk : STD_LOGIC := '0';
SIGNAL D1 : STD_LOGIC_VECTOR(7 DOWNTO 0):=(others => '0');
SIGNAL D2 : STD_LOGIC_VECTOR(7 DOWNTO 0):=(others => '0');
SIGNAL Q : STD_LOGIC_VECTOR(8 DOWNTO 0);
SIGNAL SResult    :    INTEGER;
SIGNAL OutData :     INTEGER;
SIGNAL Dlatch    :    boolean := false;COMPONENT Add2InPORT (Clk : IN STD_LOGIC;D1 : IN STD_LOGIC_VECTOR(7 DOWNTO 0);D2 : IN STD_LOGIC_VECTOR(7 DOWNTO 0);Q : OUT STD_LOGIC_VECTOR(8 DOWNTO 0));
END COMPONENT;
BEGINi1 : Add2InPORT MAP (Clk => Clk,D1 => D1,D2 => D2,Q => Q);init : PROCESS(Clk)
BEGIN            Clk <= not Clk after 10ns;
END PROCESS init;always : PROCESS FILE InputD    :    text open read_mode is "TestData.dat";FILE OutputD    :    text open write_mode is "OutData.txt";VARIABLE Dline    :    LINE;VARIABLE Rline    :    LINE;VARIABLE    Data1    :    INTEGER;VARIABLE Data2    :    INTEGER;VARIABLE    OutData    :    INTEGER;
BEGIN                                                         WAIT UNTIL Clk'event and CLk = '1';readline(InputD, Dline);read(Dline, Data1);read(Dline, Data2);D1 <= conv_std_logic_vector(Data1, 8);D2 <= conv_std_logic_vector(Data2, 8);OutData <= conv_integer(Q);writeline(OutputD, Rline);write(Rline, OutData);
END PROCESS always;                                          PROCESS
FILE InputR    :    text open read_mode is "Result.dat";
VARIABLE    Rline    :    LINE;
VARIABLE    Result    :    INTEGER;
BEGINWAIT UNTIL Clk'event and Clk = '1';Dlatch <= true;if Dlatch thenreadline(InputR, Rline);read(Rline, Result);SResult <= Result;if(SResult /= Q) thenassert false report "Two values are different"severity warning;end if;end if;
END PROCESS;END Add2In_arch;