The e200z4 MMU 学习笔记

The e200z4 MMU Functional description

10.1 Overview
The memory management unit is a 32-bit Power ISA embedded category-compliant implementation, with
the following feature set:
• Virtual memory support
• 32-bit virtual and physical addresses
• 8-bit process identifier
• 16-entry fully associative TLB
• Hardware assist for TLB miss exceptions
• Per-entry multiple page size support from 1 Kbyte to 4 Gbyte
• Entry flush protection
• Software managed by tlbre, tlbwe, tlbsx, tlbsync, and tlbivax instructions
• Freescale EIS MMU architecture compliant
• Support for external control of entry matching for a subset of TID values to support non-intrusive
runtime mapping modifications

Figure 10-1.Virtual Address and TLB-Entry Compare Process

a . EA–Effective Addresses 虚拟地址
The MMU translates this effective address to a 32-bit real address which is then used for memory accesses.
The Power ISA embedded category architecture divides the effective (virtual) and real (physical) address space into pages. The page represents the granularity of effective address translation, permission control,and memory/cache attributes.
In order for an effective to real address translation to exist, a valid entry for the page containing the effective address must be in a ***translation lookaside buffer (TLB)***. Addresses for which no TLB entry exists (a TLB miss) cause instruction or data TLB errors.

Instruction accesses are generated by sequential instruction fetches or due to a change in program flow(branches and interrupts).
Data accesses are generated by load, store, and cache management instructions.
The e200 instruction fetch, branch, and load/store units generate 32-bit effective addresses.

b. EPN–Effective Page Number

Table 10-1. Page Size and EPN Field Comparison
On a TLB hit, the corresponding bits of the real page number (RPN) field are used to form the real address.
The e200z4 MMU supports twenty-three page sizes.

Figure 10-2. Effective to Real Address Translation Flow

a. RPN–real Page Number

10.3 Translation Lookaside Buffer

The Freescale EIS architecture defines support for zero or more TLBs in an implementation（执行）, each with its own characteristics, and provides configuration information for software to query the existence and structure of the TLB(s) through a set of special purpose registers: MMUCFG, TLB0CFG, TLB1CFG, and so on.
By convention, (按规范)
TLB0 is used for a set associative（组合） TLB with fixed page sizes;
TLB1 is used for a fully associative TLB with variable page sizes;
and TLB2 is arbitrarily（专用于） defined by an implementation.
The e200z4 MMU supports a TLB that is fully associative and supports variable page sizes; thus it corresponds（与一致） to TLB1.
TLB1 consists of a 16-entry, fully associative CAM array with support for 23 page sizes. To perform a lookup, the CAM is searched in parallel for a matching TLB entry. The contents of this TLB entry are then concatenated（串级） with the page offset of the original effective address. The result constitutes（构成） the real (physical) address of the access. A hit to multiple TLB entries is considered to be a programming error. If this occurs, the TLB generates an invalid address but an exception will not be reported.

VLE – Variable-length encoding

10.7.3 MMU Assist Registers (MAS)

The e200z4 uses six special purpose registers (MAS0, MAS1, MAS2, MAS3, MAS4, and MAS6) to facilitate（促进） reading, writing, and searching the TLBs. The MAS registers can be read or written using the mfspr and mtspr instructions. The e200z4 does not implement the MAS5 register, present in other Freescale EIS designs, because the tlbsx instruction only searches based on a single SPID value.

Figure 10-9. MMU Assist Register 0 (MAS0)：SPR - 624; Read/ Write; Reset - Unaffected

Figure 10-10. MMU Assist Register 1 (MAS1)

Table 10-10. MAS1—Descriptor Context and Configuration Control

Figure 10-11. MMU Assist Register 2 (MAS2)

Table 10-11. MAS2—EPN and Page Attributes

Figure 10-12. MMU Assist Register 3 (MAS3)

Table 10-12. MAS3—RPN and Access Control

应用

_tlballoc:
/*
* TLB1 allocated to internal RAM (0x40000000).
/
e_lis %r3, HI(TLB1_MAS0) /e_lis 幅值/
mtspr 624, %r3 / MAS0 / /mtspr 读取地址624到R3上/
e_lis %r3, HI(TLB1_MAS1)
e_or2i %r3, LO(TLB1_MAS1) /e_or2i 逻辑或–加上/
mtspr 625, %r3 / MAS1 /
e_lis %r3, HI(TLB1_MAS2)
e_or2i %r3, LO(TLB1_MAS2)
mtspr 626, %r3 / MAS2 /
e_lis %r3, HI(TLB1_MAS3)
e_or2i %r3, LO(TLB1_MAS3)
mtspr 627, %r3 / MAS3 */
tlbwe /*tlbwe */

TLB default settings.
*/
#define TLB0_MAS0 (MAS0_TBLMAS_TBL | MAS0_ESEL(0))
#define TLB0_MAS1 (MAS1_VALID | MAS1_IPROT | MAS1_TSISE_2M)
#define TLB0_MAS2 (MAS2_EPN(0x00000000) | MAS2_VLE)
#define TLB0_MAS3 (MAS3_RPN(0x00000000) |
MAS3_UX | MAS3_SX | MAS3_UW | MAS3_SW |
MAS3_UR | MAS3_SR)

    e_lis                                               mtspr       624, %r3       读取地址624到R3上e_lis       %r3, HI(TLB1_MAS1)e_or2i      %r3, LO(TLB1_MAS1)  mtspr       625, %r3        /* MAS1 */e_lis       %r3, HI(TLB1_MAS2)e_or2i      %r3, LO(TLB1_MAS2)mtspr       626, %r3        /* MAS2 */e_lis       %r3, HI(TLB1_MAS3)e_or2i      %r3, LO(TLB1_MAS3)mtspr       627, %r3        /* MAS3 */tlbwe

a. tlbwe
The TLB1 array can be written by first writing the necessary information into MAS0–MAS3 using mtspr and then executing the tlbwe instruction. To write an entry into the TLB, the TLBSEL field in MAS0 must be set to ‘01’ and the ESEL bits in MAS0 must be set to point to the desired entry. When the tlbweinstruction is executed, the TLB entry information stored in MAS1–MAS3 will be written into the selected TLB entry.

3.18 Instruction Summary powerpc汇编指令集

3.18.1 Instruction Index Sorted by Mnemonic

Table 3-5. Instructions Sorted by Mnemonic

b 实现程序的跳转
bl 带返回地址的程序跳转

参考：
Memory Management Unit of e200z4RM in Chapter 10
Chapter 3 Instruction Model
MPC5643LRM

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