第二课 MC9S08DZ60之多功能时钟发生器S08MCGV1

1.MC9S08DZ60系统时钟分配（System Clock Distribution）

在使用多用能时钟发生器（MCG）之前，先来了解下这款单片机的系统时钟。

单片机的各个功能器件对命令的执行都是一步一步的进行的，每个步骤的执行都需要一个激励，这个激励就是时钟，在一定的时钟内完成给定的指令，这既是MCU工作的基本原理。可以打个不恰当的比方，MCU的时钟就如人的心脏，心脏的每一跳动，都在给全身各个功能器官输送血液养分和能量。MCU的时钟也是如此，每一个时钟跳动（震荡周期）片上资源（如ALG、SPI、IIC等）都会得到一个指令去执行。也即心脏如时钟发生器，人体器官如MCU上的片上资源，血液养分和能量就如单片机的指令和数据。

大家可以到我的百度盘下载该芯片的中英文的资料https://pan.baidu.com/s/1dgVbkE https://pan.baidu.com/s/1o9qFU5c，进入1.3 System Clock Distribution章节，建议读者先阅读一遍该章节，可以说确实不难，很快就可以知道这个芯片的时钟从产生到送到各个片上资源的路径，以及有几种时钟可以选择。这里我把芯片资料中的系统时钟图Figure 1-2. MC9S08DZ60 System Clock Distribution Diagram 粘贴上来做一个简单的说明，重点是如何为这款单片机配置系统时钟，那就是写代码！其他的多看看。

A.首先从图Figure 1-2 中要能知道这款单片机的片上资源有哪些，它们分别是RTC、COP、TPM1、TPM2、IIC、SCI1、SCI2、SPI、CPU、BDC、ADC、MSCAN、FLASH、EEPROM、LPO、MCG、XOSC。

B.这么多的片上资源咱们如果是一头蒙，不知道他们是干什么的话，那就不要管它们是什么。这课主题是MCG，也就是比拟的心脏，其他的，如CPU就理解为人的大脑，MSCAN就理解为人的嘴巴用来沟通的，FLASH/EEPROM就理解为人的记忆器官，反正总之这些片上资源它们是能各自完成各自的功能的，如果读者是位初学者且之前没有接触过单片机，那么也没关系，这些器件都会慢慢讲解。

C.看图的左边，MCG这个心脏为MCU片上资源提供了MCGERCLK、MCGIRCLK、MCGFFCLK、MCGOUT、MCGLCLK,并且知道MCG还控制一个（XOSC）外部振荡器以便把晶体或共鸣器用作外部参考时钟。除了MCG外这款单片机内部还有一个LPO 1KHZ的频率发生器只用来给RTC、COP这两个器件工作用。

D.另外右下角有一段英文：The fixed frequency clock(FFCLK) is internally synchronized to the bus clock and must not exceed one half of the bus clock frequency 就是FFCLK这个时钟频率不要大于总线的2倍就可以，其实也不用担心，因为从时钟系统图，看到硬件已经做了÷2的设定.

2.接下来就是看芯片资料的Chapter8 Multi-Purpose Clock Generator（S08MCGV1)来了解这个MCG和怎样去用这个MCG来真正是的单片机工作起来。

很显然，如果读者是第一次接触单片机，你肯定很头痛看这个芯片资料，或许看完之后也不知道怎么去操作这个MCG。即使真是这样，也没关系。不过建议多看看芯片资料，真的会有进步，个人经验，多看几遍就懂了。因为这里面涉及到很多理论概念加之读者的学识以及时间的限制，不啰嗦介绍这个MCG，读者自己看看咯。

3.现在来驱动这个MCG，让它工作起来。

看芯片资料的‘8.3 Register Definition'，一共看到5个寄存器（register），分别是MCGC1、MCGC2、MCGTRM、MCGSC、MCGC3。这里给这些寄存器分类为：MCGC1、MCGC2、MCGC3为控制类，MCGTRM为功能类、MCGSC为状态类。好那就建立三个函数，分别来操作这个三类寄存器吧。这三个函数名就分别取MCG_Control,MCG_Function和MCG_Status。

另外看到每个寄存器中有多个设置项，看下图

每个设置项又有多个选择项，看下图

作者在这里采用没个设置项“位与”“异或非”：的方式来最终组成8字节的寄存器内容和判断寄存器中的值，也就是需要为每一个设置项定义多个define宏，如：#define CLKS_FLL_PLL 00 ;其实code warrior 工程文件加入芯片头文件后有类似的定义，也无需自己定义的，但是为了自己使用，还是自己写了，俗话说看十遍，不如写一遍--不要笑话哈。

另外还要理解芯片资料的介绍的“8.4.1 Operational Mode”。其中FEI（FLL Engaged Internal）是复位芯片的默认模式，如果要用其他模式，比如FBE(FLL Bypassed External)，直接设置到FBE模式，一步即可，但是要想用PBE(PLL Bypassed External)，那么就要根据（双向）箭头的指示，找最短路线，先设置为FBE，然后在设置为PBE。怎么去切换时钟模式，在8.4.1节下面小节的每个模式说明中都有介绍，这个读者自己去看了，我只把模式切换（Clock Switch Modes）图贴过来：

最后，读者要了解下，MCG内部的机制，建议读者通过一边浏览代码一边看MCG block diagram。通过这种方式，深入了解MCG提供的寄存器中各个设置项所做的事情，具体到MCG内部的详细情况。不同模式对输入的频率都有限制，这在芯片资料中8.5.2 MCG Mode Switching及相关对CLOCK mode说明章节中都有说明，设置的时钟分频一定要符合要求。

4.不善言表，废话也也多，上代码。

变量的重定义

#ifndef _DATA_TYPE_H_H
#define _DATA_TYPE_H_Htypedef char            INT8;
typedef unsigned char   UINT8;
typedef unsigned short  USHORT16;
typedef unsigned int    UNIT16;
typedef unsigned long   ULONG32;
typedef short           SHORT16;
typedef long            LONG32;
typedef unsigned char   BOOL;
#endif

头文件MCG.h

#ifndef _MCG_H_H
#define _MCG_H_H#ifdef CRYSTAL2M
#define RDIV_PARAM 0x00  //2Mhz的外部时钟频率除16
#else
#ifdef CRYSTAL4M
#define RDIV_PARAM 0x08  //4Mhz的外部时钟频率除32
#else
#ifdef CRYSTAL8M
#define RDIV_PARAM 0x10  //8Mhz的外部时钟频率除64
#else
#define RDIV_PARAM 0x18  //其他频率除128
#endif
#endif
#endif
//MCGC1
/*7     6   5 4 3      2       1           0R  |---------------------------------------------| CLKS    |RDIV   | IREFS | IRCLKEN | IREFSTENW  |---------|-----------------------------------
Reset:  0      0   0 0 0     1        0           0
*/
#define CLKS_SHIFT   6
#define RDIV_SHIFT   3
#define IREFS_SHIFT  2
#define IRCLKEN_SHIFT 1
#define IREFSTEN_SHIFT 0/*
只设置目标项，不影响其他项目的设置值，如设置CLKS为0b11那么CLKS为0b11，其他的，如
RDIV不会改变，维持原来的值。
value:为目标设定的值，如设RDIV 0b011,那么value=0x03,
shift:为目标设置项在寄存器中的起点，从0开始
具体方式是：先清零设置项，再给已经清零的设置项赋值。
*/
void MCGC1_Target_Set(UINT8 value,UINT8 shift);
/*
Notice!　Put a brandnew value to MCGC1,the pre-Value in MCGC1 will erased.
new value will replace it.
参数setMCGC1可以使用 表1中所有宏定义，如要设置多项，可以用位"与"，来选择多个不同
设置选项。
*/
void MCGC1_Set(UINT8 setMCGC1);
//表1
//Selects the system clock source-----------------------------------------------#define MCGC1_RESET 0x04   //芯片重启\复位后寄存器初始值#define CLKS_SEL_FLL_PLL     0x00//(0x00<<6)    //Output of FLL or PLL is selected.    #define CLKS_SEL_INT_REF_CLK 0x01//(0x01<<6)    //Internal reference clock is selected.#define CLKS_SEL_EXT_REF_CLK 0x02//(0x02<<6)    //External reference clock is selected.#define CLKS_SEL_RESERVED    0x03//(0x03<<6)    //Reserved, defaults to 00.//Selects the amount to divide down the reference clock selected by the IREFS bit. //If the FLL is selected, the resulting frequency must be in the range 31.25kHz to //39.0625kHz. If the PLL is selected, the resulting frequency must be in the range//1 MHz to 2 MHz.#define RDIV_1   0x00//(0x00<<3)    //Divides reference clock by 1(reset default)#define RDIV_2   0x01//(0x01<<3)   //Divides reference clock by 2#define RDIV_4   0x02//(0x02<<3)  //Divides reference clock by 4#define RDIV_8   0x03//(0x03<<3)  //Divides reference clock by 8#define RDIV_16  0x04//(0x04<<3)  //Divides reference clock by 16#define RDIV_32  0x05//(0x05<<3)  //Divides reference clock by 32#define RDIV_64  0x06//(0x06<<3)  //Divides reference clock by 64#define RDIV_128 0x07//(0x07<<3)  //Divides reference clock by 128     //Selects the reference clock source.#define IREFS_SEL_INT_REF_CLK 0x01//0x01//(0x01<<2)    //Internal reference clock selected#define IREFS_SEL_EXT_REF_CLK 0x00//(0x00<<2)    //External reference clock selected//Enables the internal reference clock for use as MCGIRCLK.#define MCGIRCLK_ACTIVE   0x01//(0x01<<1)  //MCGIRCLK active#define MCGIRCLK_INACTIVE 0x00//(0x00<<1)  //MCGIRCLK inactive//Controls whether or not the internal reference clock remains enabled when//the MCG enters stop mode.#define INT_CLK_ENABLE_IN_STOP  0x01    //Internal reference clock stays enabled// in stop if IRCLKEN is set or if MCG is in //FEI, FBI, or BLPI mode before entering stop#define INT_CLK_DISABLE_IN_STOP 0x00  //Internal reference clock is disabled in stop//MCGC2/*7 6   5      4    3    2       1        0
R     ----------------------------------------------|BDIV |RANGE| HGO |LP |EREFS |ERCLKEN |EREFSTEN
W     ----------------------------------------------
Reset: 0 1     0     0    0    0      0         0*/
#define BDIV_SHIFT    6
#define RANGE_SHIFT   5
#define HGO_SHIFT     4
#define LP_SHIFT      3
#define EREFS_SHIFT   2
#define ERCLKEN_SHIFT  1
#define EREFSTEN_SHIFT  0
/*
只设置目标项，不影响其他项目的设置值，如设置BDIV为0b11那么BDIV为0b11，其他的，如
RANGE不会改变，维持原来的值。
value:为目标设定的值，如设BDIV 0b11,那么value=0x03,
shift:为目标设置项在寄存器中的起点，从0开始
具体方式是：先清零设置项，再给已经清零的设置项赋值。
*/
void MCGC2_Target_Set(UINT8 value,UINT8 shift);
/*
Notice!  Put a brandnew value to MCGC2,the pre-Value in MCGC2 will erased.
new value will replace it.
参数setMCGC2可以使用 表2 中所有宏定义，如要设置多项，可以用位"与"，来选择多个不同
设置选项。
*/
void MCGC2_Set(UINT8 setMCGC2);
//表2
//Selects the amount to divide down the clock source selected by the CLKS bits in the//MCGC2 register. This controls the bus frequency.#define MCGC2_RESET 0x40     //MCGC2复位值#define BDIV_1 0x00//(0x00<<6)    //Divides selected clock by 1#define BDIV_2 0x01//(0x01<<6)    //Divides selected clock by 2 (reset default)#define BDIV_4 0x02//(0x02<<6)    //Divides selected clock by 4#define BDIV_8 0x03//(0x03<<6)    //Divides selected clock by 8//Selects the frequency range for the external oscillator or external clock source.#define RANGE_1_16_MHZ  0x01//(0x01<<5)   //High frequency range selected for the external //oscillator of 1 MHz to 16 MHz#define RANGE_1_40_MHZ  0x01//(0x01<<5)    //1 MHz to 40 MHz for external clock source#define RANGE_32_100_KHZ  0x00//(0x00<<5)    //Low frequency range selected for the external// oscillator of 32 kHz to 100 kHz#define RANGE_32K_1M_HZ  0x00//(0x00<<5)    //32 kHz to 1 MHz for external clock source.//Controls the external oscillator mode of operation#define HGO_HI_GAIN  0x01//(0x01<<4)    //Configure external oscillator for high gain operation#define HGO_LO_POW   0x00//(0x00<<4)    //Configure external oscillator for low power operation//Controls whether the FLL (or PLL) is disabled in bypassed modes.#define LP_DISABLE  0x01//(0x01<<3)      //FLL (or PLL) is disabled in bypass modes (lower power).#define LP_ENABLE   0x00//(0x00<<3)      //FLL (or PLL) is not disabled in bypass modes.//Selects the source for the external reference clock.#define EREFS_SEL_OSC    0x01//(0x01<<2)    //Oscillator requested#define EREFS_SEL_EXT_CLK  0x00//(0x00<<2)  //External Clock Source requested//Enables the external reference clock for use as MCGERCLK.#define MCGERCLK_ACTIVE    0x01//(0x01<<1)    //MCGERCLK active#define MCGERCLK_INACTIVE  0x00//(0x00<<1)    //MCGERCLK inactive//Controls whether or not the external reference clock remains enabled when//the MCG enters stop mode.#define EXT_CLK_ENABLE_IN_STOP  0x01    //External reference clock stays enabled in stop// if ERCLKEN is set or if MCG is in FEE, FBE, PEE, PBE, //or BLPE mode before entering stop#define INT_CLK_DISABLE_IN_STOP 0x00    //IExternal reference clock is disabled in stop//MCGC3/*7      6      5    4   3 2 1 0
R      ---------------------------------|LOLIE | PLLS | CME |0  |VDIV
W      ---------------------------------
Reset:    0       0     0    0   0 0 0 1*/
#define LOLIE_SHIFT  7
#define PLLS_SHIFT   6
#define CME_SHIFT    5
#define VDIV_SHIFT   0
/*
只设置目标项，不影响其他项目的设置值，如设置LOLIE为0b1那么LOLIE为0b1，其他的，如
PLLS不会改变，维持原来的值。
value:为目标设定的值，如设PLLS 0b1,那么value=0x01,
shift:为目标设置项在寄存器中的起点，从0开始
具体方式是：先清零设置项，再给已经清零的设置项赋值。
*/
void MCGC3_Target_Set(UINT8 value,UINT8 shift);
/*
Put a brandnew value to MCGC3,the pre-Value in MCGC3 will erased.
new value will replace it.
参数setMCGC3可以使用 表3 中所有宏定义，如要设置多项，可以用位"与"，来选择多个不同
设置选项。
*/
void MCGC3_Set(UINT8 setMCGC3);
//表3
//Determines if an interrupt request is made following a loss of lock indication.//The LOLIE bit only has an effect when LOLS is set.#define MCGC3_RESET 0x10#define    LOLIE_INTR_DEN  0x00//(0x0<<7)    //No request on loss of lock.#define    LOLIE_INTR_REQ  0x01//(0x01<<7)    //Generate an interrupt request on loss of lock.//Controls whether the PLL or FLL is selected. If the PLLS bit is clear, the PLL is disabled in all//modes. If the PLLS is set, the FLL is disabled in all modes.#define PLL_SELECTED    0x01//(0x01<<6)    //PLL is selected#define FLL_SELECTED    0x00//(0x00<<6)    //FLL is selected//Determines if a reset request is made following a loss of external clock indication. The
//CME bit should only be set to a logic 1 when either the MCG is in an operational mode that uses the external
//clock (FEE, FBE, PEE, PBE, or BLPE) or the external reference is enabled (ERCLKEN=1 in the MCGC2
//register). Whenever the CME bit is set to a logic 1, the value of the RANGE bit in the MCGC2 register should not//be changed.#define MONITOR_DISABLED   0x00//(0x00<<5)    //Clock monitor is disabled#define LOSS_EXT_CLK_RESET 0x01//(0x01<<5)    //Generate a reset request on loss of external clock.
//Selects the amount to divide down the VCO output of PLL. The VDIV bits establish the//multiplication factor (M) applied to the reference clock frequency.#define VDIV_0      0x00    //reselved#define VDIV_4      0x01   //Multiply by 4.#define VDIV_8      0x02   //Multiply by 8.#define VDIV_12      0x03   //Multiply by 12.#define VDIV_16      0x04   //Multiply by 16.#define VDIV_20      0x05   //Multiply by 20#define VDIV_24      0x06   //Multiply by 24.#define VDIV_28      0x07   //Multiply by 28.#define VDIV_32      0x08   //Multiply by 32.#define VDIV_36     0x09  //Multiply by 36.#define VDIV_40      0x0A   //Multiply by 40.#define VDIV_1011      0x0B   //Reserved (default to M=40).#define VDIV_11XX      0x0C/*TO 0xFF*/   //Reserved (default to M=40).//MCGTRM
//MCG Trim Setting — Controls the internal reference clock frequency by controlling the internal reference clock
//period. The TRIM bits are binary weighted (i.e., bit 1 will adjust twice as much as bit 0). Increasing the binary
//value in TRIM will increase the period, and decreasing the value will decrease the period.
//An additional fine trim bit is available in MCGSC as the FTRIM bit.
//If a TRIM[7:0] value stored in nonvolatile memory is to be used, it’s the user’s responsibility to copy that value
//from the nonvolatile memory location to this register.
/*
TRIM
RW
POR:   1 0 0 0 0 0 0 0
Reset: U U U U U U U U
*/
/*
Controls the internal reference clock frequency by controlling the internal reference clock
period. The TRIM bits are binary weighted (i.e., bit 1 will adjust twice as much as bit 0).
Increasing the binary value in TRIM will increase the period, and decreasing the value will
decrease the period.An additional fine trim bit is available in MCGSC as the FTRIM bit.
If a TRIM[7:0] value stored in nonvolatile memory is to be used, it’s the user’s responsibility
to copy that value from the nonvolatile memory location to this register.
*/
//extern uchar trm;
void MCG_Function(UINT8 mcgtrm);
//MCGSC/*7      6     5      4       3 2     1        0
R     LOLS |LOCK |PLLST |IREFST |CLKST |OSCINIT |FTRIM
W
POR:  0      0     0      1        00     0        0
Reset:0      0     0      1        00     0        U
*/
#define LOLS_SHIFT    7
#define LOCK_SHIFT    6
#define PLLST_SHIFT   5
#define IREFST_SHIFT  4
#define CLKST_SHIFT   2
#define OSCINIT_SHIFT 1
#define FTRIM_SHIFT   0
/*
Get MCG Status and Control Register
当需求的状态吻合时，返回真
*/
BOOL MCG_Status(UINT8 status,UINT8 shift);
//表4
//This bit is a sticky indication of lock status for the FLL or PLL. LOLS is set when lock
//detection is enabled and after acquiring lock, the FLL or PLL output frequency has fallen outside the lock exit
//frequency tolerance, Dunl. LOLIE determines whether an interrupt request is made when set. LOLS is cleared by
//reset or by writing a logic 1 to LOLS when LOLS is set. Writing a logic 0 to LOLS has no effect.#define MCGSC_RESET 0x10 //MCGSC复位值#define LOLS_FLL_PLL_LOCKED        0x00//(0x80^0x00)   //FLL or PLL has not lost lock since LOLS was last cleared#define LOLS_FLL_PLL_LOST_LOCK     0x80//(0x80^0x80)   //FLL or PLL has lost lock since LOLS was last cleared//Lock Status — Indicates whether the FLL or PLL has acquired lock. Lock detection is disabled when both the
//FLL and PLL are disabled. If the lock status bit is set then changing the value of any of the following bits IREFS,
//PLLS, RDIV[2:0], TRIM[7:0] (if in FEI or FBI modes), or VDIV[3:0] (if in PBE or PEE modes), will cause the lock
//status bit to clear and stay cleared until the FLL or PLL has reacquired lock. Stop mode entry will also cause the
//lock status bit to clear and stay cle#define LOCK_FLL_PLL_UNLOCKED   0x00//(0x40^0x00)  //FLL or PLL is currently unlocked#define LOCK_FLL_PLL_LOCKED     0x40//(0x40^0x40)  //FLL or PLL is currently locked.//PLL Select Status — The PLLST bit indicates the current source for the PLLS clock. The PLLST bit does not
//update immediately after a write to the PLLS bit due to internal synchronization between clock domains.#define PLLST_PLLS_IS_FLL                0x00//(0x20^0x00)   //Source of PLLS clock is FLL clock#define PLLST_PLLS_IS_PLL                0x20//(0x20^0x20)   //Source of PLLS clock is PLL clock.//Internal Reference Status — The IREFST bit indicates the current source for the reference clock. The IREFST
//bit does not update immediately after a write to the IREFS bit due to internal synchronization between clock
//domains.#define IREFST_EXT_CLOCK               0x00//(0x10^0x00)  //Source of reference clock is external reference clock //(oscillator or external clock source as determined by the//EREFS bit in the MCGC2 register).#define IREFST_INT_CLOCK               0x10//(0x10^0x10)  //Source of reference clock is internal reference clock// Clock Mode Status — The CLKST bits indicate the current clock mode. The CLKST bits do not update
//immediately after a write to the CLKS bits due to internal synchronization between clock domains.#define CLKST_FLL_IS_SELECTED          0x00//(0x0C^0x00)  //Output of FLL is selected.#define CLKST_INT_CLK_SELECTED         0x04//(0x0C^0x04)  //Internal reference clock is selected#define CLKST_EXT_CLK_SELECTED         0x08//(0x0C^0x08)  //External reference clock is selected.#define CLKST_PLL_IS_SELECTED          0x0C//(0x0C^0x0C)   //Output of PLL is selected//OSC Initialization — If the external reference clock is selected by ERCLKEN or by the MCG being in FEE, FBE,
//PEE, PBE, or BLPE mode, and if EREFS is set, then this bit is set after the initialization cycles of the external
//oscillator clock have completed. This bit is only cleared when either EREFS is cleared or when the MCG is in
//either FEI, FBI, or BLPI mode and ERCLKEN is cleared.#define OSCINIT_SET                    0x02//(0x02^0x00)#define OSCINT_CLEARD                  0x00//(0x02^0x02)//MCG Fine Trim — Controls the smallest adjustment of the internal reference clock frequency. Setting FTRIM
//will increase the period and clearing FTRIM will decrease the period by the smallest amount possible.
//If an FTRIM value stored in nonvolatile memory is to be used, it’s the user’s responsibility to copy that value from
//the nonvolatile memory location to this register’s FTRIM bit.#define FTRIM_PROLONG                  0x00//(0x01^0x00)#define FTRIM_SHORTEN                  0x01//(0x01^0x01)/*
Add new value to MCGC1 MCGC2 and MCGC3,previous bit-value will not be erased.
because here in the function use or('|') operator.
参数mcgc1、mcgc2、mcgc3分别可以使用表1、表2、表3中的宏定义，每个参数如需设置多项，可以用位"与"
，来选择多个不同设置选项。 如不想设置某个寄存器，直接给参数0即可。
*/
void MCG_Control(UINT8 mcgc1,UINT8 mcgc2,UINT8 mcgc3);/*
one example for setting the mcg From the initial FEI clock mode to PEE clock mode.
*/
//从FEI到FBE模式的寄存器设置
//#define MCGC2_FEI_FBE  (BDIV_1|RANGE_1_40_MHZ|HGO_HI_GAIN|EREFS_SEL_OSC|MCGERCLK_ACTIVE)
//#define MCGC1_FEI_FBE  (CLKS_SEL_EXT_REF_CLK|RDIV_64|IREFS_SEL_EXT_REF_CLK)
extern void SetBusClock(void);#endif

源文件.C

#include <hidef.h>
#include "derivative.h"
#include "MCG.h"//------VARIABLES PLACE HERE----------------------------------------------------
//uchar trm;//------LOCAL FUNC PLACE HERE---------------------------------------------------//------------------------------------------------------------------------------
void MCGC1_Target_Set(volatile UINT8 value,UINT8 shift) {switch(shift) {case  CLKS_SHIFT:if(0x03<value) value = 0x03;MCGC1 &=0x3F;MCGC1 |=0xC0 & (value<<shift);break;case  RDIV_SHIFT:if(0x07<value) value = 0x07;MCGC1 &= 0xC7;MCGC1 |=0x38 & (value<<shift);break;case  IREFS_SHIFT:if(0x01<value) value = 0x01;MCGC1 &= 0xFB;MCGC1 |= 0x04 & (value<<shift);break;case  IRCLKEN_SHIFT:if(0x01<value) value = 0x01;MCGC1 &= 0xFD;MCGC1 |= 0x02 & (value<<shift);break;case IREFSTEN_SHIFT:if(0x01<value) value = 0x01;MCGC1 &= 0xFE;MCGC1 |= 0x01 & (value<<shift);break;default:break;}
}
void MCGC1_Set(UINT8 setMCGC1)
{MCGC1 = setMCGC1;
}
//------------------------------------------------------------------------------
void MCGC2_Target_Set(UINT8 value,UINT8 shift) {switch(shift){case BDIV_SHIFT:if(0x03<value) value = 0x03;MCGC2 &= 0x3F;MCGC2 |= 0xC0 & (value<<shift);break;case RANGE_SHIFT:if(0x01<value) value = 0x01;MCGC2 &= 0xDF;MCGC2 |= 0x20 & (value<<shift);break;case HGO_SHIFT:if(0x01<value) value = 0x01;MCGC2 &= 0xEF;MCGC2 |= 0x10 & (value<<shift); break;case LP_SHIFT:if(0x01<value) value = 0x01;MCGC2 &= 0xF7;MCGC2 |= 0x08 & (value<<shift);break;case EREFS_SHIFT:if(0x01<value) value = 0x01;MCGC2 &= 0xFB;MCGC2 |= 0x04 & (value<<shift);break;case ERCLKEN_SHIFT:if(0x01<value) value = 0x01;MCGC2 &= 0xFD;MCGC2 |= 0x02 & (value<<shift);break;case EREFSTEN_SHIFT:if(0x01<value) value = 0x01;MCGC2 &= 0xFE;MCGC2 |= 0x01 & (value<<shift);break;default:break;}
}
void MCGC2_Set(UINT8 setMCGC2)
{MCGC2 = setMCGC2;
}
//------------------------------------------------------------------------------
void MCGC3_Target_Set(UINT8 value,UINT8 shift) {switch(shift) {case LOLIE_SHIFT:if(0x01<value) value = 0x01;MCGC3 &= 0x7F;MCGC3 |= 0x80 & (value<<shift); break;case PLLS_SHIFT:if(0x01<value) value = 0x01;MCGC3 &= 0xBF;MCGC3 |= 0x40 & (value<<shift);break;case CME_SHIFT:if(0x01<<value) value = 0x01;MCGC3 &= 0xDF;MCGC3 |= 0x20 & (value<<shift);      break;case VDIV_SHIFT:if(0x0F<value) value = 0x0F;MCGC3 &= 0xF0;MCGC3 |= 0x0F &(value<<shift);break;default:break;}}
void MCGC3_Set(UINT8 setMCGC3)
{MCGC3 = setMCGC3;
}void MCG_Control(UINT8 mcgc1,UINT8 mcgc2,UINT8 mcgc3)
{MCGC1 |= mcgc1;MCGC2 |= mcgc2;MCGC3 |= mcgc3;
}
void MCG_Function(UINT8 mcgtrm) {MCGTRM = mcgtrm;
}
BOOL MCG_Status(UINT8 status,UINT8 shift) {BOOL temp;switch(shift){case LOLS_SHIFT:temp = ((MCGSC & 0x80) == status );    break;case LOCK_SHIFT:temp = ((MCGSC & 0x40) == status );break;case PLLST_SHIFT:temp = ((MCGSC & 0x20) == status );break;case IREFST_SHIFT:temp = ((MCGSC & 0x10) == status );break;case CLKST_SHIFT:temp = ((MCGSC & 0x0C) == status );break;case OSCINIT_SHIFT:temp = ((MCGSC & 0x02) == status );break;case FTRIM_SHIFT:temp = ((MCGSC & 0x01) == status);break;default:break;}return temp;
}
void SetBusClock(void)
{//----------------------从初始化FEI时钟模式切换到FBE时钟模式 -------------------/* Set MCGC2 register */MCGC2_Target_Set(BDIV_1,BDIV_SHIFT);         //被MCGC1_CLKS选中的时钟源除1MCGC2_Target_Set(RANGE_1_16_MHZ,RANGE_SHIFT);//为外部振荡器选择1-16MHz的高频范//围，本实验板外部晶振8MhzMCGC2_Target_Set(HGO_HI_GAIN,HGO_SHIFT);      //外部振荡器的高增益运行MCGC2_Target_Set(LP_ENABLE,LP_SHIFT);         //旁路模式中激活旁路模式FLL或PLLMCGC2_Target_Set(EREFS_SEL_OSC,EREFS_SHIFT);  //选择振荡器MCGC2_Target_Set(MCGERCLK_ACTIVE,ERCLKEN_SHIFT);//外部参考时钟用作MCGERCLK/* Set MCGC1 register */MCGC1_Set(MCGC1_RESET);MCGC1_Target_Set(CLKS_SEL_EXT_REF_CLK,CLKS_SHIFT);//选择外部参考时钟MCGC1_Target_Set(RDIV_16,RDIV_SHIFT);             //外部参考时钟除16MCGC1_Target_Set(IREFS_SEL_EXT_REF_CLK,IREFS_SHIFT);//选择外部参考时钟MCGC1 |= RDIV_PARAM;//针对不同外部平率选择while(!MCG_Status(OSCINIT_SET,OSCINIT_SHIFT))       {           /* Wait until external reference is stable *///外部震荡时钟初始化周期之后退出}while(!MCG_Status(IREFST_EXT_CLOCK,IREFST_SHIFT))   {            /* Wait until external reference is selected *///参考时钟源是外部参考时钟退出}while(!MCG_Status(CLKST_EXT_CLK_SELECTED,CLKST_SHIFT)) {        /* Wait until external clock is selected as a bus clock reference *///选择外部参考时钟}
//----------------------从初始化FBE时钟模式切换到PBE时钟模式 -------------------   /* Set MCGC1 register */MCGC1_Target_Set(CLKS_SEL_EXT_REF_CLK,CLKS_SHIFT);MCGC1_Target_Set(RDIV_4,RDIV_SHIFT);/* Set MCGC3 register */MCGC3_Target_Set(PLL_SELECTED,PLLS_SHIFT);MCGC3_Target_Set(VDIV_20,VDIV_SHIFT);while(!MCG_Status(PLLST_PLLS_IS_PLL,PLLS_SHIFT)){          /* Wait until PLL is selected */}while(!MCG_Status(LOCK_FLL_PLL_LOCKED,LOCK_SHIFT)){            /* Wait until PLL is locked */}
//----------------------从初始化PBE时钟模式切换到PEE时钟模式 -------------------   MCGC1 = RDIV_PARAM;            /* Set MCGC1 register */while(!MCG_Status(CLKST_PLL_IS_SELECTED,CLKST_SHIFT)){      /* Wait until PLL clock is selected as a bus clock reference */}//---------------------最终PLL clock 作为BUS clock----------------------------
}

5、最终从MCG分配出来的几个时钟频率分别为MCGERCLK=8Mhz、MCGOUT=40Mhz、MCGFFCLK=2Mhz

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