Uboot SPL的Boot模式选择(从MMC切换到SPI启动)

目前主流的Uboot启动模式分为三级启动：

上电开机后，芯片Boot Rom的代码会被加载到内部的SRam运行，由于通常SRam的内存很小(几十K左右)，这就决定了Boot Rom中的代码是做不了太多的事情的，通常厂商会在这部分固化的代码中完成MMC,NAND,NOR等存储介质的初始化，并尝试从存储介质中读取SPL的代码；
SPL代码执行阶段会初始化串口，DRAM等外设，并从FLASH中读取完整的UBOOT代码到DRAM中；
UBOOT执行，SPL将UBOOT的完整代码加载到RAM后，会跳转到UBOOT的代码段中执行。

大致启动过程如下(32位ARM)：

arch\arm\lib\crt0.S

...
bl  board_init_f
...
ldr pc, =board_init_r  /* this is auto-relocated! */
...

board_init_f会完成串口以及DRAM的初始化，以及必要的板级设备初始化

arch\arm\mach-sunxi\board.c

void board_init_f(ulong dummy)
{spl_init();//串口初始化preloader_console_init();#ifdef CONFIG_SPL_I2C_SUPPORT/* Needed early by sunxi_board_init if PMU is enabled */i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
#endif//必要的板级设备以及DRAM初始化sunxi_board_init();//内存测试
#ifdef CONFIG_SPL_BUILDspl_mem_test();
#endif
}

common\spl\spl.c

void board_init_r(gd_t *dummy1, ulong dummy2)
{u32 spl_boot_list[] = {BOOT_DEVICE_NONE,BOOT_DEVICE_NONE,BOOT_DEVICE_NONE,BOOT_DEVICE_NONE,BOOT_DEVICE_NONE,};struct spl_image_info spl_image;debug(">>spl:board_init_r()\n");...//选择BOOT设备(MMC,NAND,NOR等)board_boot_order(spl_boot_list);//从FLASH介质中读取UBOOT完整代码段到DRAMif (boot_from_devices(&spl_image, spl_boot_list,ARRAY_SIZE(spl_boot_list))) {puts("SPL: failed to boot from all boot devices\n");hang();}spl_image.entry_point |= 0x1;//根据读取的代码段，确认代码段是UBOOT还是KERNELswitch (spl_image.os) {case IH_OS_U_BOOT:debug("Jumping to U-Boot\n");break;case IH_OS_LINUX:debug("Jumping to Linux\n");spl_fixup_fdt();spl_board_prepare_for_linux();jump_to_image_linux(&spl_image);default:debug("Unsupported OS image.. Jumping nevertheless..\n");}...//跳转到UBOOT执行debug("loaded - jumping to U-Boot...\n");spl_board_prepare_for_boot();jump_to_image_no_args(&spl_image);

这个章节再关注下board_boot_order这个函数

common\spl\spl.c

__weak void board_boot_order(u32 *spl_boot_list)
{spl_boot_list[0] = spl_boot_device();
}

arch\arm\mach-sunxi\board.c

uint32_t sunxi_get_boot_device(void)
{int boot_source;/** When booting from the SD card or NAND memory, the "eGON.BT0"* signature is expected to be found in memory at the address 0x0004* (see the "mksunxiboot" tool, which generates this header).** When booting in the FEL mode over USB, this signature is patched in* memory and replaced with something else by the 'fel' tool. This other* signature is selected in such a way, that it can't be present in a* valid bootable SD card image (because the BROM would refuse to* execute the SPL in this case).** This checks for the signature and if it is not found returns to* the FEL code in the BROM to wait and receive the main u-boot* binary over USB. If it is found, it determines where SPL was* read from.*/if (!is_boot0_magic(SPL_ADDR + 4)) /* eGON.BT0 */return BOOT_DEVICE_BOARD;boot_source = readb(SPL_ADDR + 0x28);printf("boot source %d\n", boot_source);    switch (boot_source) {case SUNXI_BOOTED_FROM_MMC0:return BOOT_DEVICE_MMC1;case SUNXI_BOOTED_FROM_NAND:return BOOT_DEVICE_NAND;case SUNXI_BOOTED_FROM_MMC2:return BOOT_DEVICE_MMC2;case SUNXI_BOOTED_FROM_SPI:return BOOT_DEVICE_SPI;}panic("Unknown boot source %d\n", boot_source);return -1;        /* Never reached */
}
u32 spl_boot_device(void)
{return sunxi_get_boot_device();
}

如上就是BOOT的FLASH设备选择过程。
需要注意的是要将sunxi_spi_spl.c编译进SPL中

common/spl/Makefile/

+obj-y += sunxi_spi_spl.o

代码如下：

/** Copyright (C) 2016 Siarhei Siamashka <siarhei.siamashka@gmail.com>** SPDX-License-Identifier: GPL-2.0+*/#include <common.h>
#include <spl.h>
#include <asm/gpio.h>
#include <asm/io.h>
#include <libfdt.h>#ifdef CONFIG_SPL_OS_BOOT
#error CONFIG_SPL_OS_BOOT is not supported yet
#endif/** This is a very simple U-Boot image loading implementation, trying to* replicate what the boot ROM is doing when loading the SPL. Because we* know the exact pins where the SPI Flash is connected and also know* that the Read Data Bytes (03h) command is supported, the hardware* configuration is very simple and we don't need the extra flexibility* of the SPI framework. Moreover, we rely on the default settings of* the SPI controler hardware registers and only adjust what needs to* be changed. This is good for the code size and this implementation* adds less than 400 bytes to the SPL.** There are two variants of the SPI controller in Allwinner SoCs:* A10/A13/A20 (sun4i variant) and everything else (sun6i variant).* Both of them are supported.** The pin mixing part is SoC specific and only A10/A13/A20/H3/A64 are* supported at the moment.*//*****************************************************************************/
/* SUN4I variant of the SPI controller                                       */
/*****************************************************************************/#define SUN4I_SPI0_CCTL             (0x01C05000 + 0x1C)
#define SUN4I_SPI0_CTL              (0x01C05000 + 0x08)
#define SUN4I_SPI0_RX               (0x01C05000 + 0x00)
#define SUN4I_SPI0_TX               (0x01C05000 + 0x04)
#define SUN4I_SPI0_FIFO_STA         (0x01C05000 + 0x28)
#define SUN4I_SPI0_BC               (0x01C05000 + 0x20)
#define SUN4I_SPI0_TC               (0x01C05000 + 0x24)#define SUN4I_CTL_ENABLE            BIT(0)
#define SUN4I_CTL_MASTER            BIT(1)
#define SUN4I_CTL_TF_RST            BIT(8)
#define SUN4I_CTL_RF_RST            BIT(9)
#define SUN4I_CTL_XCH               BIT(10)/*****************************************************************************/
/* SUN6I variant of the SPI controller                                       */
/*****************************************************************************/#define SUN6I_SPI0_CCTL             (0x01C68000 + 0x24)
#define SUN6I_SPI0_GCR              (0x01C68000 + 0x04)
#define SUN6I_SPI0_TCR              (0x01C68000 + 0x08)
#define SUN6I_SPI0_FIFO_STA         (0x01C68000 + 0x1C)
#define SUN6I_SPI0_MBC              (0x01C68000 + 0x30)
#define SUN6I_SPI0_MTC              (0x01C68000 + 0x34)
#define SUN6I_SPI0_BCC              (0x01C68000 + 0x38)
#define SUN6I_SPI0_TXD              (0x01C68000 + 0x200)
#define SUN6I_SPI0_RXD              (0x01C68000 + 0x300)#define SUN6I_CTL_ENABLE            BIT(0)
#define SUN6I_CTL_MASTER            BIT(1)
#define SUN6I_CTL_SRST              BIT(31)
#define SUN6I_TCR_XCH               BIT(31)/*****************************************************************************/#define CCM_AHB_GATING0             (0x01C20000 + 0x60)
#define CCM_SPI0_CLK                (0x01C20000 + 0xA0)
#define SUN6I_BUS_SOFT_RST_REG0     (0x01C20000 + 0x2C0)#define AHB_RESET_SPI0_SHIFT        20
#define AHB_GATE_OFFSET_SPI0        20#define SPI0_CLK_DIV_BY_2           0x1000
#define SPI0_CLK_DIV_BY_4           0x1001#define _DEBUG    1
#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x8000/*****************************************************************************//** Allwinner A10/A20 SoCs were using pins PC0,PC1,PC2,PC23 for booting* from SPI Flash, everything else is using pins PC0,PC1,PC2,PC3.*/
static void spi0_pinmux_setup(unsigned int pin_function)
{unsigned int pin;for (pin = SUNXI_GPC(0); pin <= SUNXI_GPC(2); pin++)sunxi_gpio_set_cfgpin(pin, pin_function);if (IS_ENABLED(CONFIG_MACH_SUN4I) || IS_ENABLED(CONFIG_MACH_SUN7I))sunxi_gpio_set_cfgpin(SUNXI_GPC(23), pin_function);elsesunxi_gpio_set_cfgpin(SUNXI_GPC(3), pin_function);
}/** Setup 6 MHz from OSC24M (because the BROM is doing the same).*/
static void spi0_enable_clock(void)
{/* Deassert SPI0 reset on SUN6I */if (IS_ENABLED(CONFIG_SUNXI_GEN_SUN6I))setbits_le32(SUN6I_BUS_SOFT_RST_REG0,(1 << AHB_RESET_SPI0_SHIFT));/* Open the SPI0 gate */setbits_le32(CCM_AHB_GATING0, (1 << AHB_GATE_OFFSET_SPI0));/* Divide by 4 */writel(SPI0_CLK_DIV_BY_4, IS_ENABLED(CONFIG_SUNXI_GEN_SUN6I) ?SUN6I_SPI0_CCTL : SUN4I_SPI0_CCTL);/* 24MHz from OSC24M */writel((1 << 31), CCM_SPI0_CLK);if (IS_ENABLED(CONFIG_SUNXI_GEN_SUN6I)) {/* Enable SPI in the master mode and do a soft reset */setbits_le32(SUN6I_SPI0_GCR, SUN6I_CTL_MASTER |SUN6I_CTL_ENABLE |SUN6I_CTL_SRST);/* Wait for completion */while (readl(SUN6I_SPI0_GCR) & SUN6I_CTL_SRST);} else {/* Enable SPI in the master mode and reset FIFO */setbits_le32(SUN4I_SPI0_CTL, SUN4I_CTL_MASTER |SUN4I_CTL_ENABLE |SUN4I_CTL_TF_RST |SUN4I_CTL_RF_RST);}
}static void spi0_disable_clock(void)
{/* Disable the SPI0 controller */if (IS_ENABLED(CONFIG_SUNXI_GEN_SUN6I))clrbits_le32(SUN6I_SPI0_GCR, SUN6I_CTL_MASTER |SUN6I_CTL_ENABLE);elseclrbits_le32(SUN4I_SPI0_CTL, SUN4I_CTL_MASTER |SUN4I_CTL_ENABLE);/* Disable the SPI0 clock */writel(0, CCM_SPI0_CLK);/* Close the SPI0 gate */clrbits_le32(CCM_AHB_GATING0, (1 << AHB_GATE_OFFSET_SPI0));/* Assert SPI0 reset on SUN6I */if (IS_ENABLED(CONFIG_SUNXI_GEN_SUN6I))clrbits_le32(SUN6I_BUS_SOFT_RST_REG0,(1 << AHB_RESET_SPI0_SHIFT));
}static void spi0_init(void)
{unsigned int pin_function = SUNXI_GPC_SPI0;if (IS_ENABLED(CONFIG_MACH_SUN50I))pin_function = SUN50I_GPC_SPI0;spi0_pinmux_setup(pin_function);spi0_enable_clock();
}static void spi0_deinit(void)
{/* New SoCs can disable pins, older could only set them as input */unsigned int pin_function = SUNXI_GPIO_INPUT;if (IS_ENABLED(CONFIG_SUNXI_GEN_SUN6I))pin_function = SUNXI_GPIO_DISABLE;spi0_disable_clock();spi0_pinmux_setup(pin_function);
}/*****************************************************************************/#define SPI_READ_MAX_SIZE 60 /* FIFO size, minus 4 bytes of the header */static void sunxi_spi0_read_data(u8 *buf, u32 addr, u32 bufsize,ulong spi_ctl_reg,ulong spi_ctl_xch_bitmask,ulong spi_fifo_reg,ulong spi_tx_reg,ulong spi_rx_reg,ulong spi_bc_reg,ulong spi_tc_reg,ulong spi_bcc_reg)
{writel(4 + bufsize, spi_bc_reg); /* Burst counter (total bytes) */writel(4, spi_tc_reg);           /* Transfer counter (bytes to send) */if (spi_bcc_reg)writel(4, spi_bcc_reg);  /* SUN6I also needs this *//* Send the Read Data Bytes (03h) command header */writeb(0x03, spi_tx_reg);writeb((u8)(addr >> 16), spi_tx_reg);writeb((u8)(addr >> 8), spi_tx_reg);writeb((u8)(addr), spi_tx_reg);/* Start the data transfer */setbits_le32(spi_ctl_reg, spi_ctl_xch_bitmask);/* Wait until everything is received in the RX FIFO */while ((readl(spi_fifo_reg) & 0x7F) < 4 + bufsize);/* Skip 4 bytes */readl(spi_rx_reg);/* Read the data */while (bufsize-- > 0)*buf++ = readb(spi_rx_reg);/* tSHSL time is up to 100 ns in various SPI flash datasheets */udelay(1);
}static void spi0_read_data(void *buf, u32 addr, u32 len)
{u8 *buf8 = buf;u32 chunk_len;while (len > 0) {chunk_len = len;if (chunk_len > SPI_READ_MAX_SIZE)chunk_len = SPI_READ_MAX_SIZE;if (IS_ENABLED(CONFIG_SUNXI_GEN_SUN6I)) {sunxi_spi0_read_data(buf8, addr, chunk_len,SUN6I_SPI0_TCR,SUN6I_TCR_XCH,SUN6I_SPI0_FIFO_STA,SUN6I_SPI0_TXD,SUN6I_SPI0_RXD,SUN6I_SPI0_MBC,SUN6I_SPI0_MTC,SUN6I_SPI0_BCC);} else {sunxi_spi0_read_data(buf8, addr, chunk_len,SUN4I_SPI0_CTL,SUN4I_CTL_XCH,SUN4I_SPI0_FIFO_STA,SUN4I_SPI0_TX,SUN4I_SPI0_RX,SUN4I_SPI0_BC,SUN4I_SPI0_TC,0);}len  -= chunk_len;buf8 += chunk_len;addr += chunk_len;}
}static ulong spi_load_read(struct spl_load_info *load, ulong sector,ulong count, void *buf)
{spi0_read_data(buf, sector, count);return count;
}/*****************************************************************************/static int spl_spi_load_image(struct spl_image_info *spl_image,struct spl_boot_device *bootdev)
{int ret = 0;struct image_header *header;header = (struct image_header *)(CONFIG_SYS_TEXT_BASE);spi0_init();spi0_read_data((void *)header, CONFIG_SYS_SPI_U_BOOT_OFFS, 0x40);if (IS_ENABLED(CONFIG_SPL_LOAD_FIT) &&image_get_magic(header) == FDT_MAGIC) {struct spl_load_info load;debug("Found FIT image\n");load.dev = NULL;load.priv = NULL;load.filename = NULL;load.bl_len = 1;load.read = spi_load_read;ret = spl_load_simple_fit(spl_image, &load,CONFIG_SYS_SPI_U_BOOT_OFFS, header);} else {ret = spl_parse_image_header(spl_image, header);if (ret)return ret;spi0_read_data((void *)spl_image->load_addr,CONFIG_SYS_SPI_U_BOOT_OFFS, spl_image->size);}spi0_deinit();return ret;
}
/* Use priorty 0 to override the default if it happens to be linked in */
SPL_LOAD_IMAGE_METHOD("Jon SPI", 0, BOOT_DEVICE_SPI, spl_spi_load_image);

SPL_LOAD_IMAGE_METHOD("Jon SPI", 0, BOOT_DEVICE_SPI, spl_spi_load_image);
如上是SPI BOOT的入口项；另外需要特别留意CONFIG_SYS_SPI_U_BOOT_OFFS，这个是配置的UBOOT代码的偏移地址，如何确定这个偏移是多少呢？这个需要看u-boot-spl.lds文件配置的是多大了,如下：

u-boot/arch/arm/cpu/armv7/sunxi/u-boot-spl.lds

MEMORY { .sram : ORIGIN = CONFIG_SPL_TEXT_BASE,\LENGTH = CONFIG_SPL_MAX_SIZE }
MEMORY { .sdram : ORIGIN = CONFIG_SPL_BSS_START_ADDR, \LENGTH = CONFIG_SPL_BSS_MAX_SIZE }

CONFIG_SYS_SPI_U_BOOT_OFFS=CONFIG_SPL_TEXT_BASE+CONFIG_SPL_MAX_SIZE
其实还可以直接看SPL目录的生成文件：

u-boot/spl/u-boot-spl.lds

MEMORY { .sram : ORIGIN = 0x60, LENGTH = 0x7fa0 }
MEMORY { .sdram : ORIGIN = 0x4ff80000, LENGTH = 0x00080000 }

拔出MMC后启动LOG如下：

U-Boot Jon SPL 2017.11 (Apr 30 2019 - 15:46:34)
DRAM: 256 MiB(408MHz)
CPU Freq: 408MHz
memory test: 1
Pattern 55aa  Writing...Reading...OK
>>spl:board_init_r()
boot source 3
flag : 0xffffffff
Trying to boot from Jon SPI
Boot device: untest, may occur error
Jon,spl_parse_image_header
0x27,
0x05,0x19,0x56,0x98,0x4a,0xd2,0x7b,0x5c,0xc7,0xfd,
0x77,0x00,0x04,0xf6,0x2c,0x4a,0x00,0x00,0x00,0x00,
0x00,0x00,0x00,0x34,0x15,0xab,0xdd,0x11,0x02,0x05,
0x00,0x55,0x2d,0x42,0x6f,0x6f,0x74,0x20,0x32,0x30,
0x31,0x37,0x2e,0x31,0x31,0x20,0x66,0x6f,0x72,0x20,
0x73,0x75,0x6e,0x78,0x69,0x20,0x62,0x6f,0x61,0x72,
0x64,0x00,0x00,
spl: payload image: *s load addr: 0x20 size: 1241514016
loader->name : Jon SPI
Jumping to U-Boot
SPL malloc() used lx bytes (0 KB)
loaded - jumping to U-Boot...
image entry point: 0xU-Boot 2017.11 (Apr 30 2019 - 15:46:34 +0800) Allwinner TechnologyCPU:   Allwinner H3 (SUN8I 1680)
Model: FriendlyElec NanoPi H3
DRAM:  256 MiB
Detecting eMMC...
No MMC device available
No MMC device available
eMMC not exist
CPU Freq: 1008MHz
MMC:   SUNXI SD/MMC: 0, SUNXI SD/MMC: 1
Card did not respond to voltage select!
mmc_init: -95, time 22
*** Warning - MMC init failed, using default environmentERROR: unsupported boot mmc 3
### ERROR ### Please RESET the board ###

很明显SPL已经能够正常从SPI中BOOT了

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