R11代表了Allwinner在智能硬件处理器上的最新成就，它集成了一个以1.2GHz的速度工作的单ARM

CortexTM-A7 CPU，并支持多个外围设备。

CPU

ARM CortexTM-A7 MP1 Processor Thumb-2 Technology Supports NEON Advanced SIMD(Single Instruction Multiple Data)

instruction for acceleration of media and

signal processing

functions Supports Large Physical Address

Extensions(LPAE) VFPv4 Floating Point Unit 32KB L1 Instruction cache and 32KB L1 Data

cache 128KB L2 cache

Memory Subsystem Boot ROM

Internal on-chip memory Supports system boot from the following

devices: - SPI Nor flash - SPI Nand flash - SD/TF card - eMMC Supports system code download through USB OTG

SDRAM

Internal on-chip memory Built-in DDR2 in the R11 Clock frequency up to 400MHz Supports Memory Dynamic Frequency Scale(MDFS)

SD/MMC

External off-chip memory and storage

device Two SD/MMC controllers 1/4-bit data bus Complies with eMMC standard specification V4.41, SD physical layer

specification V2.0, SDIO card specification

Supports hardware CRC generation and error

detection Block size from 1 to 65535 bytes

System Peripheral Timer

Three on-chip timers with interrupt-based

operation One watchdog to generate reset signal or

interrupt 33 bits Audio/Video Sync(AVS) Counter 24MHz or internal OSC clock input

High Speed Timer

Up to two high speed timers Counters up to 56 bits Clock source is synchronized with AHB1 clock, much more accurate

than other timers

GIC

Supports 16 Software Generated Interrupts(SGIs), 16 Private

Peripheral Interrupts(PPIs) and 125 Shared

Peripheral Interrupts(SPIs)

DMA

Up to 8-channel DMA Flexible data width of 8/16/32 bits Supports linear and IO address modes Supports data transfer types with memory-to-memory,

memory-to-peripheral, peripheral-to-memory

CCU

9 PLLs One on-chip RC oscillator One 24MHz external oscillator One 32.768kHz external oscillator Clock management: clock gating ,clock enabling to the device

modules, clock reset, clock generation, clock division

PWM

Two PWM channels Supports outputting two kinds of waveform: continuous waveform and

pulse waveform 0% to 100% adjustable duty cycle Up to 24MHz output frequency

RTC

Time,calendar Counters second,minutes,hours,day,week,month and year with leap

year generator Alarm:general alarm and weekly alarm

LRADC

6-bit resolution Supports hold key and continuous key Supports single key, normal key and continuous key

Crypto Engine

Supports AES 128/192/256-bit with ECB,CBC,CTS,CTR

mode Supports DES/TDES with ECB,CBC,CTR mode Supports SHA1 and MD5 160-bit hardware PRNG with 175-bit seed

Display Subsystem DE2.0

Output size up to 1024x1024 Supports three alpha blending channel for main

display Supports four overlay layers in each channel, and has a independent

scale Supports potter-duff compatible blending

operation Supports input format

YUV422/YUV420/YUV411/ARGB8888/XRGB8888/RGB888/ARGB4444/ARGB1555/RGB565

Display Output

Supports LVDS interface with single link, up to

1024x768@60fps Supports RGB interface with DE/SYNC mode, up to

1024x768@60fps Supports serial RGB/dummy RGB/CCIR656 interface, up to

800x480@60fps Supports i80 interface with 18/16/9/8 bit, support TE, up to

800x480@60fps Supports pixel format: RGB888, RGB666 and

RGB565 Dither function from RGB666/RGB565 to

RGB888 Gamma correction with R/G/B channel independence

Video Engine Video Decoding

Supports video decoder for H.264 and

JPEG/MJPEG Supports H.264 BP/MP/HP up to 1080p@30fps Supports H.264 output formats

:NV21,NV12,YU12,YV12 Supports JPEG/MJPEG up to 1080p@30fps

Video Encoding

Supports H.264 video encoding up to

720p@60fps JPEG baseline: picture size up to 8192x8192 Supports input picture size up to 4800x4800 Supports input format:

YU12/YV12/NV12/NV21/YUYV/YVYU/UYVY/VYUY Supports Alpha blending Supports thumb generation Supports 4x2 scaling ratio: from 1/16 to 64 arbitrary non-integer

ratio Supports rotated input

Image Subsystem Image Input

Supports 8/10-bit CMOS sensor parallel

interface Supports 8-bit CCIR656 protocol for NTSC and

PAL Supports ITU-R BT 1120 protocol for HD-CIF

system Supports 16-bit interface with separate

syncs MIPI-CSI2 interface compliant with MIPI-DPHY v1.0 and MIPI-CSI2

v1.0 Supports MIPI-CSI2 1/2 data lanes

configuration Supports Format:

- YUV422-8/10 bits - YUV420-8/10 bits(for MIPI-CSI2 only) - RAW-8/10 bits - RGB888/RGB565(for MIPI-CSI2 only)

Performance: - Still capture resolution up to 5M with parallel

interface - Video capture resolution up to 1080p@30fps with parallel

interface - Still capture resolution up to 5M with MIPI-CSI2

interface - Video capture resolution up to 1080p@30fps with MIPI-CSI2

interface - MIPI-DPHY maximum data rate up to 1Gbps per lane

ISP

Supports input formats:8/10-bit RAW RGB,8-bit

YCbCr Supports output formats: YCbCr420 semi-planar,YCrCb420 semi-planar,

YCbCr422 semi-planar,YCrCb422 semi-planar,YUV420

planar,YUV422 planar Supports image mirror flip and rotation Supports two output channels Speed up to 8MPixels@24fps Defect pixel correction Super lens shading correction Anisotropic non-linear Bayer interpolation with false color

suppression Programmable color correction Advanced contrast enhance and sharping Advanced saturation adjust Advanced spatial(2D) de-noise filter Advanced chrominance noise reduction Zone-based AE/AF/AWB statistics Anti-flick detection statistics Histogram statistics

Audio Subsystem Audio Codec

Two audio digital-to-analog(DAC)

channels Supports analog/digital volume control One low-noise analog microphone bias output Analog low-power loop from microphone to headphone

outputs Supports Dynamic Range Controller adjusting the DAC playback

output One Microphone input One Stereo Lineout output Two audio analog-to-digital(ADC) channels

- 92dB SNR@A-weight - Supports ADC Sample Rates from 8kHz to 48kHz

Supports Automatic Gain Control(AGC) and Dynamic Range Control(DRC)

adjusting the ADC recording input

External Peripherals USB

One USB 2.0 OTG controller with integrated

PHY Complies with USB2.0 Specification Supports High-Speed(HS,480 Mbit/s),Full-Speed(FS,12 Mbit/s),and

Low-Speed(LS,1.5 Mbit/s) in host mode Complies with Enhanced Host Controller Interface (EHCI)

Specification, Version 1.0,and the Open Host

Controller Interface(OHCI) Specification,Version 1.0a for host

mode Up to 8 User-Configurable Endpoints in device

mode Supports point-to-point and point-to-multipoint transfer in both

host and peripheral mode

I2S/PCM

Compliant with standard Inter-IC sound(I2S) bus

specification Compliant with left-justified, right-justified, PCM mode, and

TDM(Time Division Multiplexing) format Full-duplex synchronous work mode Master and slave mode configured Adjustable audio sample resolution from 8-bit to 32-bit

Sample rate from 8 kHz to 192 kHz

Supports 8-bit u-law and 8-bit A-law companded sample

EMAC

Supports 10/100/1000 Mbit/s data transfer

rate Supports RGMII/MII/RMII interface

Full-duplex and half-duplex operation Linked-list descriptor list structure Programmable frame length to support Standard or Jumbo Ethernet

frames with sizes up to 16 KB Supports a variety of flexible address filtering modes

UART

Up to three UART controllers 64-Bytes Transmit and receive data FIFOs for all

UART Compliant with industry-standard 16550 UARTs

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