1 library ieee;                        --第一个低层设计实体 xor_gate
 2 use ieee.std_logic_1164.all;
 3 entity xor_gate is
 4     port(op1 , op2 : in std_logic;
 5         xor_result: out std_logic);
 6 end xor_gate;
 7 architecture behave of xor_gate is
 8 begin
 9     xor_result <= op1 xor op2;
10 end behave;
11
12
13 library ieee;                        --第二个低层设计实体 and_gate
14 use ieee.std_logic_1164.all;
15 entity and_gate is
16     port(op1 , op2 : in std_logic;
17         and_result : out std_logic);
18 end and_gate;
19 architecture behave of and_gate is
20 begin
21     and_result <= op1 and op2;
22 end behave;
23
24
25 library ieee;                        --顶层设计实体 half_adder
26 use ieee.std_logic_1164.all;
27 entity half_adder is
28     port(a , b       : in std_logic;
29          sum , carry : out std_logic);
30 end half_adder;
31 architecture struct of half_adder is
32 component xor_gate                    --说明元件 “异或门” xor_gate
33     port(op1 , op2  : in std_logic;
34         xor_result : out std_logic);
35 end component;
36 component and_gate                    --说明元件“与门” and_gate
37     port(op1 , op2  : in std_logic;
38          and_result : out std_logic);
39 end component;
40 begin
41     G1 : xor_gate port map                --对“异或门”xor_gate的一次例化
42             (op1 => a , op2 => b , xor_result => sum);
43     G2 : and_gate port map                --对“与门”and_gate的一次例化
44             (op1 => a , op2 => b , and_result => carry);
45 end struct;