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Computer orga ni zati on and architecture

Midterm exam 2010/11

I. Multi-choice

〔.Erasure unit for flash memory is( B )

a. Chip levelword levelb. byte level

a. Chip level

word level

b. byte level

c. block leveld.

Cache usually adopts ( B )

b. ran dom accessd. read only methodDirect access method (semi seque ntial)

b. ran dom access

d. read only method

method

c. Seque ntial access method

3.lf memory cycle is 250ns and 16 bits are read each time, then the data

tran sfer rate of the memory is (

d )

a. 4x10 6 bytes/s

b. 4M bytes/s

c. 8x10 6 bytes/s

d. 8M bytes/s

4.假设某系统总线在一个总线周期中并行传输4字节信息，一个总线周期占用

2个时钟周期，总线时钟频率为10MHz,则总线带宽是(b )

10 MB/sb. 20 MB/sc. 40 MB/sd. 80 MB/s

浮点数加、减运算过程包括对阶、尾数运算、规格化、舍入和判溢出等步骤。 设浮点数的阶码和尾数均采用补码表示，且位数分别为5位和7位(均含2

位符号位)。若有两个数X=^x29/32，丫=2x5/8，则用浮点加法计算X+Y的最 终结果是(d )

00111 1100010b. 00111 0100010

c. 01000 0010001d.发生溢出

设某浮点数共12位，其中阶码含1位阶符共4位，以2为底，补码表示；尾

数含1位数符共8位，补码表示，规格化。则该浮点数所能表示的最大正数 是( )。

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2 7b. 2 8c. 2 8-1d. 2 7-1

不恢复余数除法(也称加减交替除法)C

a.不存在恢复余数的操作

当某一步运算不够减时，做恢复余数操作

仅当最后一步余数为负时，做恢复余数操作

当某一步余数为负时，做恢复余数操作

指令周期是指 (c )

CPU从主存取出一条指令的时间

CPU执行一条指令的时间

CPU从主存取出一条指令加上执行一条指令的时间

时钟周期时间

II. Questi ons

The followi ng figure shows the releva nt porti on of memorya nd processor

registers. Please show the program executi on for the in structio ns in

memory locations 1002, 1003, and 1004.

Note: in structio ns are two addresses one.

“Load $R1, 1006 ” register R1(1006)

“Add $R2, $R1” $R2($R1) + ($R2)

“ ISZ $R1” in creme nt $R1, if $R1 is zero the n jump to 1005 else

do 1004

“ BR 1002' bran ch 1002

CPUMemory

CPU

100010011002Load $R1, 1006Clear $R2

1000

1001

1002

Load $R1, 1006

Clear $R2

Add $R2, $R1

IR

PC1002

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1003 ISZ $R11004 BR 1002

1003 ISZ $R1

1004 BR 1002

R1 -5

Store $R2, 1007

—5

—5

R2 0

S

Con sider a hypothetical microprocessor gen erat ing a 16-bit address and hav ing a 16-bit data bus.

What is the maximummemoryaddress space that t