ADuC7026简单开发过程

新建keil_MDK工程

第一步就会让你选Device，如果用的是高版本的keil（比如v5）那这里一定要提前在keil官网下好老版本的芯片包 <Legacy Device Database>。毕竟ADuC作为ARMv4内核的产品，已经很老了。

然后搜索器件选择ADuC7026。创检成功。

工程树里现在除了自己生成的启动文件外啥也没有：

我们向工程中添加ADI官网下载的ADuC7026评估板例程里的DAC demo，这个程序用于在DAC1输出正弦波：

/********************************************************************Author        : ADI - Apps            www.analog.com/MicroConverterDate          : Sept. 2005File          : DACsine.cHardware      : Applicable to ADuC702x rev H or I siliconCurrently targetting ADuC7026.Description   : DAC outputs a sine wave on pin 10 (DAC1). S1.8 must be offDAC is updated with core clock frequency 45MHz.********************************************************************/#include<ADuC7026.h>int main (void)  {// Table is placed in Flash/EEconst static unsigned short TableS[64] = {0x07FF, 0x08C8, 0x098E, 0x0A51, 0x0B0F, 0x0BC4, 0x0C71, 0x0D12,0x0DA7, 0x0E2E, 0x0EA5, 0x0F0D, 0x0F63, 0x0FA6, 0x0FD7, 0x0FF5,0x0FFF, 0x0FF5, 0x0FD7, 0x0FA6, 0x0F63, 0x0F0D, 0x0EA5, 0x0E2E,0x0DA7, 0x0D12, 0x0C71, 0x0BC4, 0x0B0F, 0x0A51, 0x098E, 0x08C8,0x07FF, 0x0736, 0x0670, 0x05AD, 0x04EF, 0x043A, 0x038D, 0x02EC,0x0257, 0x01D0, 0x0159, 0x00F1, 0x009B, 0x0058, 0x0027, 0x0009,0x0000, 0x0009, 0x0027, 0x0058, 0x009B, 0x00F1, 0x0159, 0x01D0,0x0257, 0x02EC, 0x038D, 0x043A, 0x04EF, 0x05AD, 0x0670, 0x0736  };int   i = 0;// DAC configurationDAC1CON = 0x13;               // DAC configuration// range AVdd/AGND// DAC1 is updated with falling edge of core clockDAC1DAT = 0x08000000;       // start from midscalewhile(1){DAC1DAT = (TableS[i] << 16);  i++;i &= 0x03f;          }return (0);
}

Build遇到BUG

按理说keil会自动配置好相关环境，不需要我们再手动关联甚至修改库文件。但此时直接Build就是会报6个Error，很无语：

.\Objects\ADuC7026_DAC1SineWave_Demo.axf: Error: L6218E: Undefined symbol DAbt_Handler (referred from aduc702x.o).
.\Objects\ADuC7026_DAC1SineWave_Demo.axf: Error: L6218E: Undefined symbol FIQ_Handler (referred from aduc702x.o).
.\Objects\ADuC7026_DAC1SineWave_Demo.axf: Error: L6218E: Undefined symbol IRQ_Handler (referred from aduc702x.o).
.\Objects\ADuC7026_DAC1SineWave_Demo.axf: Error: L6218E: Undefined symbol PAbt_Handler (referred from aduc702x.o).
.\Objects\ADuC7026_DAC1SineWave_Demo.axf: Error: L6218E: Undefined symbol SWI_Handler (referred from aduc702x.o).
.\Objects\ADuC7026_DAC1SineWave_Demo.axf: Error: L6218E: Undefined symbol Undef_Handler (referred from aduc702x.o).

这些错源自启动文件里汇编程序extern了这6个xxx_Handler，但是这6个函数却没被定义。

ADI-keil官方在开发的时候准备了三个版本的irq.c文件，他们在你安装keil_MDK根目录的/ARM/INC\ADI路径下，例如

E:\Keil_MDK\ARM\INC\ADI

三个版本的文件名分别为：

irq.c

irq_keil.c

irq_arm.c

检查这三个文件的内容，发现那6个中断函数在irq_keil.c中被定义，因此反推错误产生的原因是keil在编译的时候没有编译irq_keil.c（要么就是编译了但被其他内容覆盖了），导致keil的汇编器在输出目标代码的时候找不到定义。

解决方法

手动添加 irq_keil.c 至工程。

烧录/调试

使用FT2232+OpenOCD给ADuc7026烧录程序。硬件启动并连接无误后，测试一下连接——使用命令：

openocd -f E:\OpenOCD\share\openocd\scripts\interface\ftdi\ft2232hq_jtag.cfg -f E:\OpenOCD\share\openocd\scripts\target\aduc702x.cfg

发现adapter已经可以和target通信。这里其实经过了漫长的摸索。。比如adapter speed太高会出一些玄学BUG，比如上图上半部分。（后来发现这个值不是说的FT2232的时钟频率——一块12MHz的晶振，adapter speed应该小于FT2232时钟频率和target即ADuC时钟频率的较小者）。

分享一下ft2232和aduc702x的配置文件吧：

#
# ADAFRUIT FTDI FT2232HQ as a JTAG/SWD interface
# Any FT2232Hx based board may work
#
# http://www.ftdichip.com/Products/ICs/FT2232HQ.htm
#
#adapter driver ftdi# The speed of the JTAG interface, in KHz. If you get DSR/DIR errors (and they
# do not relate to OpenOCD trying to read from a memory range without physical
# memory being present there), you can try lowering this.
adapter speed 200# specify the VID/PID, serial number, or the number of the channel you will use for FT2232H, since it has two channels.# FTDI Device                 FTDI Vendor ID          Default Product ID
# FT232BM/L/Q, FT245BM/L/Q        0x0403                  0x6001
# FT232RL/Q, FT245RL/Q            0x0403                  0x6001
# FT2232C/D/L                     0x0403                  0x6010
# FT2232HL/Q                      0x0403                  0x6010
# FT4232HL/Q                      0x0403                  0x6011
# FT232HL/Q                       0x0403                  0x6014
# VNC1L with VDPS Firmware        0x0403                  0x6001
# VNC2 with FT232Slave            0x0403                  0x6001ftdi_vid_pid 0x0403 0x6010ftdi_channel 1
# ftdi_serial "FTZ7O8O0"# tell OpenOCD the initial values of the FTDI GPIO data and direction registers through the ftdi_layout_init command.# You should first put the initial values of the channel’s 16 pins, and then the directions. Knowing that “1” is for selecting direction as output and “0” is for input, and each channel in ft2232H has 16 pins.# data MSB..LSB（高八位...低八位）
# 0000'0000'0001'1000
# direction (1:out) MSB..LSB（高八位...低八位）
# 0000'0101'1111'1011
ftdi_layout_init 0x0018 0x05fb
# 0xfff8 0xfffb
# Those signal are only required on some platforms or may required to be
# enabled explicitly (e.g. nrf5x chips).ftdi_layout_signal nSRST -data 0x0010
# ftdi_layout_signal nSRST -data 0x0010 -oe 0x0010
# ftdi_layout_signal nTRST -data 0x0020 -oe 0x0020# The FT2223 adapter can support more than one transport protocol, so OpenOCD allows you to select the transport protocol:
transport select jtag# re-configure TDO as tri-state
#ftdi_layout_signal TDO -data 0x0002 -oe 0x0002
#ftdi_layout_signal TDI -data 0x0004# With no variables set, openocd will configure JTAG for the two cores of the ESP32 and
# will do automatic RTOS detection. This can be adjusted by uncommenting any of the
# following lines:# Only configure the PRO CPU
#set ESP32_ONLYCPU 1
# Only configure the APP CPU
#set ESP32_ONLYCPU 2
# Disable RTOS support
# set ESP32_RTOS none
# Force RTOS to be FreeRTOS
#set ESP32_RTOS FreeRTOS#Source the ESP32 configuration file
#source [find target/esp32.cfg]# The TDI pin of ESP32 is also a bootstrap pin that selects the voltage the SPI flash
# chip runs at. When a hard reset happens (e.g. because someone switches the board off
# and on) the ESP32 will use the current TDI value as the bootstrap value because the
# JTAG adapter overrides the pull-up or pull-down resistor that is supposed to do the
# bootstrapping. These lines basically set the idle value of the TDO line to a
# specified value, therefore reducing the chance of a bad bootup due to a bad flash
# voltage greatly.# Enable this for 1.8V SPI flash
#esp108 flashbootstrap 1.8
# Enable this for 3.3V SPI flash
# esp108 flashbootstrap 3.3

然后是aduc702x.cfg，可能是因为写这个文件的时候OpenOCD版本还比较早，现在里面有些指令已经不能用了，自己魔改了一下：

if { [info exists CHIPNAME] } {set _CHIPNAME $CHIPNAME
} else {set _CHIPNAME aduc702x
}if { [info exists ENDIAN] } {set _ENDIAN $ENDIAN
} else {# This config file was defaulting to big endian..set _ENDIAN little
}if { [info exists CPUTAPID] } {set _CPUTAPID $CPUTAPID
} else {set _CPUTAPID 0x3f0f0f0f
}adapter srst delay 200
jtag_ntrst_delay 200## JTAG scan chain
#format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID##
## Target configuration
##
set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGETNAME# allocate the entire SRAM as working area
$_TARGETNAME configure -work-area-phys 0x10000 -work-area-size 0x2000## flash configuration
# only target number is needed
set _FLASHNAME $_CHIPNAME.flash
flash bank $_FLASHNAME aduc702x 0 0 0 0 $_TARGETNAME## If you use the watchdog, the following code makes sure that the board
## doesn't reboot when halted via JTAG.  Yes, on the older generation
## AdUC702x, timer3 continues running even when the CPU is halted.proc watchdog_service {} {global watchdog_hdlmww 0xffff036c 0
#    echo "watchdog!!"set watchdog_hdl [after 500 watchdog_service]
}# $_TARGETNAME configure -event reset-halt-post {  watchdog_service }
# 报错
# E:\OpenOCD\share\openocd\scripts\target\aduc702x.cfg:52: Error: -event: Unknown: reset-halt-post, try one of: gdb-halt, halted, resumed, resume-start, resume-end, step-start, step-end, gdb-start, gdb-end, reset-start, reset-assert-pre, reset-assert, reset-assert-post, reset-deassert-pre, reset-deassert-post, reset-init, reset-end, examine-start, examine-fail, examine-end, debug-halted, debug-resumed, gdb-attach, gdb-detach, gdb-flash-write-start, gdb-flash-write-end, gdb-flash-erase-start, gdb-flash-erase-end, or trace-config
# in procedure 'script'
# at file "embedded:startup.tcl", line 26
# at file "E:\OpenOCD\share\openocd\scripts\target\aduc702x.cfg", line 52
# Warn : Flash driver of aduc702x.flash does not support free_driver_priv()
$_TARGETNAME configure -event halted {  watchdog_service }
$_TARGETNAME configure -event resume-start { global watchdog_hdl; after cancel $watchdog_hdl }

然后尝试用program命令烧录bin/hex文件：命令

openocd -f E:\OpenOCD\share\openocd\scripts\interface\ftdi\ft2232hq_jtag.cfg -f E:\OpenOCD\share\openocd\scripts\target\aduc702x.cfg -c "program F:\STM32\202207\ADuC7026_DAC\Objects\ADuC7026_DAC1SineWave_Demo.bin verify reset exit"

Open On-Chip Debugger 0.11.0 (2021-06-25) [https://github.com/sysprogs/openocd]
Licensed under GNU GPL v2
libusb1 09e75e98b4d9ea7909e8837b7a3f00dda4589dc3
For bug reports, readhttp://openocd.org/doc/doxygen/bugs.html
jtag
Info : ftdi: if you experience problems at higher adapter clocks, try the command "ftdi_tdo_sample_edge falling"
Info : clock speed 12000 kHz
Info : JTAG tap: aduc702x.cpu tap/device found: 0x3f0f0f0f (mfg: 0x787 (<unknown>), part: 0xf0f0, ver: 0x3)
Info : Embedded ICE version 1
Info : aduc702x.cpu: hardware has 2 breakpoint/watchpoint units
Info : starting gdb server for aduc702x.cpu on 3333
Info : Listening on port 3333 for gdb connections
Info : JTAG tap: aduc702x.cpu tap/device found: 0x3f0f0f0f (mfg: 0x787 (<unknown>), part: 0xf0f0, ver: 0x3)
Error: aduc702x.cpu: how to reset?
** Unable to reset target **
shutdown command invokedWarn : Flash driver of aduc702x.flash does not support free_driver_priv()

他竟然跟我时候不知道怎么reset，我寻思我TRST不是连着好好的吗？

进cfg一看，发现里面居然没有定义reset_config。

尝试自己加了一行

reset_config trst_only

因为ADuC芯片上的软件复位确实只有TRST，官方的评估板也没有吧硬件复位~{RST}引出来与SRST相连。

然而测试一下发现只是加这一行并没有什么卵用，openocd还是不知道怎么给ADuC复位。

翻了翻ADuC的Datasheet在51页说明了软件强制复位的条件是往RSTSTA寄存器（地址0xFFFF0230）的bit3置1。RSTSTA是一个8位的寄存器，OpenOCD里可以用mdb和mwb来读和写值。因此软件复位就由这种手动写寄存器的方式进行吧！

先倒腾一下ADuC的Flash吧，看看能不能擦除/写入：

启动openocd

openocd -f E:\OpenOCD\share\openocd\scripts\interface\ftdi\ft2232hq_jtag.cfg -f E:\OpenOCD\share\openocd\scripts\target\aduc702x.cfg -c "init;targets"

一切正常的话会显示当前Target的信息和JTAG TAP的状态。

Info : JTAG tap: aduc702x.cpu tap/device found: 0x3f0f0f0f (mfg: 0x787 (<unknown>), part: 0xf0f0, ver: 0x3)
Info : Embedded ICE version 1

新开一个shell上telnet

telnet localhost 4444

擦除Flash前CPU（即ADuC7026，在OpenOCD里又称为Flash Driver）必须是halted（挂起）状态。因此在telnet中输入指令

halt

halt指令会让CPU进入debug mode的暂停状态。然后就可以尝试往Flash里写程序了。

在正式烧录之前你还可以尝试：

查看ADuC的Flash基本信息
```
> flash banks
#0 : aduc702x.flash (aduc702x) at 0x00080000, size 0x0000f800, buswidth 0, chipwidth 0
```
根据以上返回结果，证明 OpenOCD成功获取到了芯片上的Flash大小信息（因为在target的.cfg文件中只给出了Flash基地址是0x00080000，其size赋值为0）。除了 flash banks，也可以用 flash probe <bank_num>指令具体查看某个Flash bank的信息。
读取一下前20个word看看是啥
```
> flash mdw 0x00080000 20
0x00080000: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff
0x00080020: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff
0x00080040: ffffffff ffffffff ffffffff ffffffff
```
根据以上返回结果，ADuC的Flash似乎已经被擦除过了。另外，你能看到返回结果，至少证明你的ADuC没有被锁死。（Datasheet里说第三层保护机制可以永久锁死Flash。。。）
检查ADuC的Flash Driver当前是否busy
```
> mdb 0xFFFFF800
0xfffff800: 20
```
其中bit2是0，说明Flash Driver空闲，可以进行Flash操作。

烧录程序：flash write_image <Path_of_file.hex>指令

> flash write_image erase F:/STM32/202207/ADuC7026_DAC/Objects/ADuC7026_DAC1SineWave_Demo.hex
auto erase enabled
wrote 1536 bytes from file F:/STM32/202207/ADuC7026_DAC/Objects/ADuC7026_DAC1SineWave_Demo.hex in 0.397657s (3.772 KiB/s)

这里还加了一个可选参数 [erase] 表示先整片擦除再写。然后可以发现成功烧录了，但是板子上没有任何现象——因为还需要一次复位。

OpenOCD的 program 指令是可以自动完成 halt-> flash erase -> write -> reset 这一系列操作的，但也因此其中有一个环节出错，这个指令就用不了。就像前文说的OpenOCD不知道如何reset的问题。

所以这里手动往 RSTSTA 寄存器写 0x05 （置位bit3）来强制软件复位：

> mwb 0xFFFF0230 0x05
timeout waiting for SYSCOMP & DBGACK, last DBG_STATUS: 0>

以上返回结果说明成功复位了。

因为这里烧录的是官方的DAC demo，此时已经可以看到DAC1通道输出正弦波了。

本人刚接触OpenOCD，还对其原理不熟悉，以上内容仅供参考，有问题欢迎指出。