verilog 实现DES加密

1 总体思路

要实现DES加密其实只需要按照步骤，设计组合逻辑就能完成。为了每个步骤前后顺序相对可控，我将其粗略分为几个步骤

第一步：密钥PC-1置换，该步骤将64位的密钥按照表格置换成56位的新密钥。
第二步:将密钥分成左右两部分，分别按照要求左移。得到16组位移后的数值，再合并进行PC-2置换，得到最终的16组加密用密钥。
第三步：将明文进行初始置换。
第四步：完成加密运算。
第五步：对完成加密运算的64位数据进行最终置换。

根据分出来的几个步骤写完各个模块，然后使用一个简单的状态机对步骤的前后顺序进行控制以保证计算过程的稳定。关于DES算法的具体步骤，可以参考经典的DES算法详解这篇文章对DES算法的介绍非常细致，参考的时候注意文章里的S2置换表是写错了的。直接crt-c,crt-v得了

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SLEEP

PC_1

PC_2

CODING

DIP

2 生成密钥

2.1 PC-1置换模块

 module key_pc1(input                    clk,input                      rst_n,input         [1:64]   key,output reg  [1:56]  out,output reg              down_pc1,input                  en_pc1
);
always @(posedge clk or negedge rst_n) beginif(~rst_n)beginout <= 56'b0;down_pc1<=1'b0;endelse beginif(en_pc1)beginout <={key[57],key[49],key[41],key[33],key[25],key[17],key[9],key[1],key[58],key[50],key[42],key[34],key[26],key[18],key[10],key[2],key[59],key[51],key[43],key[35],key[27],key[19],key[11],key[3],key[60],key[52],key[44],key[36],key[63],key[55],key[47],key[39],key[31],key[23],key[15],key[7],key[62],key[54],key[46],key[38],key[30],key[22],key[14],key[6],key[61],key[53],key[45],key[37],key[29],key[21],key[13],key[5],key[28],key[20],key[12],key[4]};down_pc1<=1'b1;endelse beginout<= out;down_pc1<=down_pc1;endendend
endmodule

2.2 循环移位&PC-2置换模块

module key_pc2(input                 clk,input                   rst_n,input     [1:56]  key_1,output        [1:48*16]   out,output  reg                 down_pc2,input                          en_pc2
);
wire [0:27] C_T[16:0];
wire [0:27] D_T[16:0];
wire [1:56] T[16:0];//左右拼接reg [1:48] T_O[16:0];//PC-2置换后数值assign C_T[0] = key_1[1:28];
assign D_T[0] = key_1[29:56];
assign T[0]   = {C_T[0],D_T[0]};
assign out    = {T_O[1],T_O[2],T_O[3],T_O[4],T_O[5],T_O[6],T_O[7],T_O[8],T_O[9],T_O[10],T_O[11],T_O[12],T_O[13],T_O[14],T_O[15],T_O[16]};
genvar i;
generate for(i=1;i<=2;i=i+1)begin :shift1_2
assign C_T[i] = {C_T[i-1][1:27],C_T[i-1][0]};
assign D_T[i] = {D_T[i-1][1:27],D_T[i-1][0]};
assign T[i]   = {C_T[i],D_T[i]};
end
endgenerategenerate for(i=3;i<=8;i=i+1)begin :shift3_8
assign C_T[i] = {C_T[i-1][2:27],C_T[i-1][0:1]};
assign D_T[i] = {D_T[i-1][2:27],D_T[i-1][0:1]};
assign T[i]   = {C_T[i],D_T[i]};
end
endgenerategenerate for(i=9;i<=9;i=i+1)begin :shift9
assign C_T[i] = {C_T[i-1][1:27],C_T[i-1][0]};
assign D_T[i] = {D_T[i-1][1:27],D_T[i-1][0]};
assign T[i]   = {C_T[i],D_T[i]};
end
endgenerategenerate for(i=10;i<=15;i=i+1)begin :shift10_15
assign C_T[i] = {C_T[i-1][2:27],C_T[i-1][0:1]};
assign D_T[i] = {D_T[i-1][2:27],D_T[i-1][0:1]};
assign T[i]   = {C_T[i],D_T[i]};
end
endgenerate
generate for(i=16;i<=16;i=i+1)begin :shift16
assign C_T[i] = {C_T[i-1][1:27],C_T[i-1][0]};
assign D_T[i] = {D_T[i-1][1:27],D_T[i-1][0]};
assign T[i]   = {C_T[i],D_T[i]};
end
endgenerategenerate for(i=1;i<=16;i=i+1)begin :pc2
always @(posedge clk or negedge rst_n) beginif(~rst_n) beginT_O[i] <= 48'b0;endelse beginif(en_pc2)T_O[i] <= {T[i][14],T[i][17],T[i][11],T[i][24],T[i][1],T[i][5],T[i][2],T[i][28],T[i][15],T[i][6],T[i][21],T[i][10],T[i][23],T[i][19],T[i][12],T[i][3],T[i][26],T[i][8],T[i][16],T[i][7],T[i][27],T[i][20],T[i][13],T[i][4],T[i][41],T[i][52],T[i][31],T[i][37],T[i][47],T[i][55],T[i][30],T[i][40],T[i][51],T[i][45],T[i][33],T[i][48],T[i][44],T[i][49],T[i][39],T[i][56],T[i][34],T[i][53],T[i][46],T[i][42],T[i][50],T[i][36],T[i][29],T[i][32]};elseT_O[i] <= T_O[i];endendend
endgeneratealways @(posedge clk or negedge rst_n) beginif(~rst_n)  begindown_pc2 <= 1'b0;endelse beginif(en_pc2)down_pc2 <= 1'b1;else down_pc2<=down_pc2;endend
endmodule

3 生成密文

3.1 IP置换模块

module IP(input                  clk,input                       rst_n,input         [1:64]  data,output reg [0:63]  out,output  reg         down_IP,input                       en_IP
);always @(posedge clk or negedge rst_n) beginif(~rst_n)beginout <= 64'b0;down_IP<= 1'b0;endelse beginif(en_IP)beginout <={data[58],data[50],data[42],data[34],data[26],data[18],data[10],data[2],data[60],data[52],data[44],data[36],data[28],data[20],data[12],data[4],data[62],data[54],data[46],data[38],data[30],data[22],data[14],data[6],data[64],data[56],data[48],data[40],data[32],data[24],data[16],data[8],data[57],data[49],data[41],data[33],data[25],data[17],data[9],data[1],data[59],data[51],data[43],data[35],data[27],data[19],data[11],data[3],data[61],data[53],data[45],data[37],data[29],data[21],data[13],data[5],data[63],data[55],data[47],data[39],data[31],data[23],data[15],data[7]};down_IP<=1'b1;endelse beginout <= out;down_IP<=down_IP;endendendendmodule

3.2 轮运算模块

这里的轮运算模块只完成一次运算，数据的连接和异或操作等都在顶层文件中

 module f(input              clk,input                   rst_n,input     [1:32]  R,input     [1:48]  key,output  reg [1:32]  out,output                      down_f,input                            en_f
);
wire    [1:48] E;
assign E={R[32],R[1:5],R[4:9],R[8:13],R[12:17],R[16:21],R[20:25],R[24:29],R[28:32],R[1]};
reg [1:32] S;
reg down_s,down_p;
wire  [1:48] B;
assign B=E^key;
always @(posedge clk or negedge rst_n)beginif(!rst_n) beginS <= 32'b0;down_s<=1'b0;endelse beginif(en_f) begincase(B[1:6])//S16'b000000 :    S[1:4] <=  4'd14;6'b000001 :    S[1:4] <=  4'd0;6'b000010 :    S[1:4] <=  4'd4;6'b000011 :    S[1:4] <=  4'd15;6'b000100 :    S[1:4] <=  4'd13;6'b000101 :    S[1:4] <=  4'd7;6'b000110 :    S[1:4] <=  4'd1;6'b000111 :    S[1:4] <=  4'd4;6'b001000 :    S[1:4] <=  4'd2;6'b001001 :    S[1:4] <=  4'd14;6'b001010 :    S[1:4] <=  4'd15;6'b001011 :    S[1:4] <=  4'd2;6'b001100 :    S[1:4] <=  4'd11;6'b001101 :    S[1:4] <=  4'd13;6'b001110 :    S[1:4] <=  4'd8;6'b001111 :    S[1:4] <=  4'd1;6'b010000 :    S[1:4] <=  4'd3;6'b010001 :    S[1:4] <=  4'd10;6'b010010 :    S[1:4] <=  4'd10;6'b010011 :    S[1:4] <=  4'd6;6'b010100 :    S[1:4] <=  4'd6;6'b010101 :    S[1:4] <=  4'd12;6'b010110 :    S[1:4] <=  4'd12;6'b010111 :    S[1:4] <=  4'd11;6'b011000 :    S[1:4] <=  4'd5;6'b011001 :    S[1:4] <=  4'd9;6'b011010 :    S[1:4] <=  4'd9;6'b011011 :    S[1:4] <=  4'd5;6'b011100 :    S[1:4] <=  4'd0;6'b011101 :    S[1:4] <=  4'd3;6'b011110 :    S[1:4] <=  4'd7;6'b011111 :    S[1:4] <=  4'd8;6'b100000 :    S[1:4] <=  4'd4;6'b100001 :    S[1:4] <=  4'd15;6'b100010 :    S[1:4] <=  4'd1;6'b100011 :    S[1:4] <=  4'd12;6'b100100 :    S[1:4] <=  4'd14;6'b100101 :    S[1:4] <=  4'd8;6'b100110 :    S[1:4] <=  4'd8;6'b100111 :    S[1:4] <=  4'd2;6'b101000 :    S[1:4] <=  4'd13;6'b101001 :    S[1:4] <=  4'd4;6'b101010 :    S[1:4] <=  4'd6;6'b101011 :    S[1:4] <=  4'd9;6'b101100 :    S[1:4] <=  4'd2;6'b101101 :    S[1:4] <=  4'd1;6'b101110 :    S[1:4] <=  4'd11;6'b101111 :    S[1:4] <=  4'd7;6'b110000 :    S[1:4] <=  4'd15;6'b110001 :    S[1:4] <=  4'd5;6'b110010 :    S[1:4] <=  4'd12;6'b110011 :    S[1:4] <=  4'd11;6'b110100 :    S[1:4] <=  4'd9;6'b110101 :    S[1:4] <=  4'd3;6'b110110 :    S[1:4] <=  4'd7;6'b110111 :    S[1:4] <=  4'd14;6'b111000 :    S[1:4] <=  4'd3;6'b111001 :    S[1:4] <=  4'd10;6'b111010 :    S[1:4] <=  4'd10;6'b111011 :    S[1:4] <=  4'd0;6'b111100 :    S[1:4] <=  4'd5;6'b111101 :    S[1:4] <=  4'd6;6'b111110 :    S[1:4] <=  4'd0;6'b111111 :    S[1:4] <=  4'd13;endcasecase(B[7:12])//S26'b000000 :    S[5:8] <=  4'd15;6'b000001 :    S[5:8] <=  4'd3;6'b000010 :    S[5:8] <=  4'd1;6'b000011 :    S[5:8] <=  4'd13;6'b000100 :    S[5:8] <=  4'd8;6'b000101 :    S[5:8] <=  4'd4;6'b000110 :    S[5:8] <=  4'd14;6'b000111 :    S[5:8] <=  4'd7;6'b001000 :    S[5:8] <=  4'd6;6'b001001 :    S[5:8] <=  4'd15;6'b001010 :    S[5:8] <=  4'd11;6'b001011 :    S[5:8] <=  4'd2;6'b001100 :    S[5:8] <=  4'd3;6'b001101 :    S[5:8] <=  4'd8;6'b001110 :    S[5:8] <=  4'd4;6'b001111 :    S[5:8] <=  4'd14;6'b010000 :    S[5:8] <=  4'd9;6'b010001 :    S[5:8] <=  4'd12;6'b010010 :    S[5:8] <=  4'd7;6'b010011 :    S[5:8] <=  4'd0;6'b010100 :    S[5:8] <=  4'd2;6'b010101 :    S[5:8] <=  4'd1;6'b010110 :    S[5:8] <=  4'd13;6'b010111 :    S[5:8] <=  4'd10;6'b011000 :    S[5:8] <=  4'd12;6'b011001 :    S[5:8] <=  4'd6;6'b011010 :    S[5:8] <=  4'd0;6'b011011 :    S[5:8] <=  4'd9;6'b011100 :    S[5:8] <=  4'd5;6'b011101 :    S[5:8] <=  4'd11;6'b011110 :    S[5:8] <=  4'd10;6'b011111 :    S[5:8] <=  4'd5;6'b100000 :    S[5:8] <=  4'd0;6'b100001 :    S[5:8] <=  4'd13;6'b100010 :    S[5:8] <=  4'd14;6'b100011 :    S[5:8] <=  4'd8;6'b100100 :    S[5:8] <=  4'd7;6'b100101 :    S[5:8] <=  4'd10;6'b100110 :    S[5:8] <=  4'd11;6'b100111 :    S[5:8] <=  4'd1;6'b101000 :    S[5:8] <=  4'd10;6'b101001 :    S[5:8] <=  4'd3;6'b101010 :    S[5:8] <=  4'd4;6'b101011 :    S[5:8] <=  4'd15;6'b101100 :    S[5:8] <=  4'd13;6'b101101 :    S[5:8] <=  4'd4;6'b101110 :    S[5:8] <=  4'd1;6'b101111 :    S[5:8] <=  4'd2;6'b110000 :    S[5:8] <=  4'd5;6'b110001 :    S[5:8] <=  4'd11;6'b110010 :    S[5:8] <=  4'd8;6'b110011 :    S[5:8] <=  4'd6;6'b110100 :    S[5:8] <=  4'd12;6'b110101 :    S[5:8] <=  4'd7;6'b110110 :    S[5:8] <=  4'd6;6'b110111 :    S[5:8] <=  4'd12;6'b111000 :    S[5:8] <=  4'd9;6'b111001 :    S[5:8] <=  4'd0;6'b111010 :    S[5:8] <=  4'd3;6'b111011 :    S[5:8] <=  4'd5;6'b111100 :    S[5:8] <=  4'd2;6'b111101 :    S[5:8] <=  4'd14;6'b111110 :    S[5:8] <=  4'd15;6'b111111 :    S[5:8] <=  4'd9;endcasecase(B[13:18])//S36'b000000 :    S[9:12] <=  4'd10;6'b000001 :    S[9:12] <=  4'd13;6'b000010 :    S[9:12] <=  4'd0;6'b000011 :    S[9:12] <=  4'd7;6'b000100 :    S[9:12] <=  4'd9;6'b000101 :    S[9:12] <=  4'd0;6'b000110 :    S[9:12] <=  4'd14;6'b000111 :    S[9:12] <=  4'd9;6'b001000 :    S[9:12] <=  4'd6;6'b001001 :    S[9:12] <=  4'd3;6'b001010 :    S[9:12] <=  4'd3;6'b001011 :    S[9:12] <=  4'd4;6'b001100 :    S[9:12] <=  4'd15;6'b001101 :    S[9:12] <=  4'd6;6'b001110 :    S[9:12] <=  4'd5;6'b001111 :    S[9:12] <=  4'd10;6'b010000 :    S[9:12] <=  4'd1;6'b010001 :    S[9:12] <=  4'd2;6'b010010 :    S[9:12] <=  4'd13;6'b010011 :    S[9:12] <=  4'd8;6'b010100 :    S[9:12] <=  4'd12;6'b010101 :    S[9:12] <=  4'd5;6'b010110 :    S[9:12] <=  4'd7;6'b010111 :    S[9:12] <=  4'd14;6'b011000 :    S[9:12] <=  4'd11;6'b011001 :    S[9:12] <=  4'd12;6'b011010 :    S[9:12] <=  4'd4;6'b011011 :    S[9:12] <=  4'd11;6'b011100 :    S[9:12] <=  4'd2;6'b011101 :    S[9:12] <=  4'd15;6'b011110 :    S[9:12] <=  4'd8;6'b011111 :    S[9:12] <=  4'd1;6'b100000 :    S[9:12] <=  4'd13;6'b100001 :    S[9:12] <=  4'd1;6'b100010 :    S[9:12] <=  4'd6;6'b100011 :    S[9:12] <=  4'd10;6'b100100 :    S[9:12] <=  4'd4;6'b100101 :    S[9:12] <=  4'd13;6'b100110 :    S[9:12] <=  4'd9;6'b100111 :    S[9:12] <=  4'd0;6'b101000 :    S[9:12] <=  4'd8;6'b101001 :    S[9:12] <=  4'd6;6'b101010 :    S[9:12] <=  4'd15;6'b101011 :    S[9:12] <=  4'd9;6'b101100 :    S[9:12] <=  4'd3;6'b101101 :    S[9:12] <=  4'd8;6'b101110 :    S[9:12] <=  4'd0;6'b101111 :    S[9:12] <=  4'd7;6'b110000 :    S[9:12] <=  4'd11;6'b110001 :    S[9:12] <=  4'd4;6'b110010 :    S[9:12] <=  4'd1;6'b110011 :    S[9:12] <=  4'd15;6'b110100 :    S[9:12] <=  4'd2;6'b110101 :    S[9:12] <=  4'd14;6'b110110 :    S[9:12] <=  4'd12;6'b110111 :    S[9:12] <=  4'd3;6'b111000 :    S[9:12] <=  4'd5;6'b111001 :    S[9:12] <=  4'd11;6'b111010 :    S[9:12] <=  4'd10;6'b111011 :    S[9:12] <=  4'd5;6'b111100 :    S[9:12] <=  4'd14;6'b111101 :    S[9:12] <=  4'd2;6'b111110 :    S[9:12] <=  4'd7;6'b111111 :    S[9:12] <=  4'd12;endcasecase(B[19:24])//S46'b000000 :    S[13:16] <=  4'd7;6'b000001 :    S[13:16] <=  4'd13;6'b000010 :    S[13:16] <=  4'd13;6'b000011 :    S[13:16] <=  4'd8;6'b000100 :    S[13:16] <=  4'd14;6'b000101 :    S[13:16] <=  4'd11;6'b000110 :    S[13:16] <=  4'd3;6'b000111 :    S[13:16] <=  4'd5;6'b001000 :    S[13:16] <=  4'd0;6'b001001 :    S[13:16] <=  4'd6;6'b001010 :    S[13:16] <=  4'd6;6'b001011 :    S[13:16] <=  4'd15;6'b001100 :    S[13:16] <=  4'd9;6'b001101 :    S[13:16] <=  4'd0;6'b001110 :    S[13:16] <=  4'd10;6'b001111 :    S[13:16] <=  4'd3;6'b010000 :    S[13:16] <=  4'd1;6'b010001 :    S[13:16] <=  4'd4;6'b010010 :    S[13:16] <=  4'd2;6'b010011 :    S[13:16] <=  4'd7;6'b010100 :    S[13:16] <=  4'd8;6'b010101 :    S[13:16] <=  4'd2;6'b010110 :    S[13:16] <=  4'd5;6'b010111 :    S[13:16] <=  4'd12;6'b011000 :    S[13:16] <=  4'd11;6'b011001 :    S[13:16] <=  4'd1;6'b011010 :    S[13:16] <=  4'd12;6'b011011 :    S[13:16] <=  4'd10;6'b011100 :    S[13:16] <=  4'd4;6'b011101 :    S[13:16] <=  4'd14;6'b011110 :    S[13:16] <=  4'd15;6'b011111 :    S[13:16] <=  4'd9;6'b100000 :    S[13:16] <=  4'd10;6'b100001 :    S[13:16] <=  4'd3;6'b100010 :    S[13:16] <=  4'd6;6'b100011 :    S[13:16] <=  4'd15;6'b100100 :    S[13:16] <=  4'd9;6'b100101 :    S[13:16] <=  4'd0;6'b100110 :    S[13:16] <=  4'd0;6'b100111 :    S[13:16] <=  4'd6;6'b101000 :    S[13:16] <=  4'd12;6'b101001 :    S[13:16] <=  4'd10;6'b101010 :    S[13:16] <=  4'd11;6'b101011 :    S[13:16] <=  4'd1;6'b101100 :    S[13:16] <=  4'd7;6'b101101 :    S[13:16] <=  4'd13;6'b101110 :    S[13:16] <=  4'd13;6'b101111 :    S[13:16] <=  4'd8;6'b110000 :    S[13:16] <=  4'd15;6'b110001 :    S[13:16] <=  4'd9;6'b110010 :    S[13:16] <=  4'd1;6'b110011 :    S[13:16] <=  4'd4;6'b110100 :    S[13:16] <=  4'd3;6'b110101 :    S[13:16] <=  4'd5;6'b110110 :    S[13:16] <=  4'd14;6'b110111 :    S[13:16] <=  4'd11;6'b111000 :    S[13:16] <=  4'd5;6'b111001 :    S[13:16] <=  4'd12;6'b111010 :    S[13:16] <=  4'd2;6'b111011 :    S[13:16] <=  4'd7;6'b111100 :    S[13:16] <=  4'd8;6'b111101 :    S[13:16] <=  4'd2;6'b111110 :    S[13:16] <=  4'd4;6'b111111 :    S[13:16] <=  4'd14;endcasecase(B[25:30])//S56'b000000 :    S[17:20] <=  4'd2;6'b000001 :    S[17:20] <=  4'd14;6'b000010 :    S[17:20] <=  4'd12;6'b000011 :    S[17:20] <=  4'd11;6'b000100 :    S[17:20] <=  4'd4;6'b000101 :    S[17:20] <=  4'd2;6'b000110 :    S[17:20] <=  4'd1;6'b000111 :    S[17:20] <=  4'd12;6'b001000 :    S[17:20] <=  4'd7;6'b001001 :    S[17:20] <=  4'd4;6'b001010 :    S[17:20] <=  4'd10;6'b001011 :    S[17:20] <=  4'd7;6'b001100 :    S[17:20] <=  4'd11;6'b001101 :    S[17:20] <=  4'd13;6'b001110 :    S[17:20] <=  4'd6;6'b001111 :    S[17:20] <=  4'd1;6'b010000 :    S[17:20] <=  4'd8;6'b010001 :    S[17:20] <=  4'd5;6'b010010 :    S[17:20] <=  4'd5;6'b010011 :    S[17:20] <=  4'd0;6'b010100 :    S[17:20] <=  4'd3;6'b010101 :    S[17:20] <=  4'd15;6'b010110 :    S[17:20] <=  4'd15;6'b010111 :    S[17:20] <=  4'd10;6'b011000 :    S[17:20] <=  4'd13;6'b011001 :    S[17:20] <=  4'd3;6'b011010 :    S[17:20] <=  4'd0;6'b011011 :    S[17:20] <=  4'd9;6'b011100 :    S[17:20] <=  4'd14;6'b011101 :    S[17:20] <=  4'd8;6'b011110 :    S[17:20] <=  4'd9;6'b011111 :    S[17:20] <=  4'd6;6'b100000 :    S[17:20] <=  4'd4;6'b100001 :    S[17:20] <=  4'd11;6'b100010 :    S[17:20] <=  4'd2;6'b100011 :    S[17:20] <=  4'd8;6'b100100 :    S[17:20] <=  4'd1;6'b100101 :    S[17:20] <=  4'd12;6'b100110 :    S[17:20] <=  4'd11;6'b100111 :    S[17:20] <=  4'd7;6'b101000 :    S[17:20] <=  4'd10;6'b101001 :    S[17:20] <=  4'd1;6'b101010 :    S[17:20] <=  4'd13;6'b101011 :    S[17:20] <=  4'd14;6'b101100 :    S[17:20] <=  4'd7;6'b101101 :    S[17:20] <=  4'd2;6'b101110 :    S[17:20] <=  4'd8;6'b101111 :    S[17:20] <=  4'd13;6'b110000 :    S[17:20] <=  4'd15;6'b110001 :    S[17:20] <=  4'd6;6'b110010 :    S[17:20] <=  4'd9;6'b110011 :    S[17:20] <=  4'd15;6'b110100 :    S[17:20] <=  4'd12;6'b110101 :    S[17:20] <=  4'd0;6'b110110 :    S[17:20] <=  4'd5;6'b110111 :    S[17:20] <=  4'd9;6'b111000 :    S[17:20] <=  4'd6;6'b111001 :    S[17:20] <=  4'd10;6'b111010 :    S[17:20] <=  4'd3;6'b111011 :    S[17:20] <=  4'd4;6'b111100 :    S[17:20] <=  4'd0;6'b111101 :    S[17:20] <=  4'd5;6'b111110 :    S[17:20] <=  4'd14;6'b111111 :    S[17:20] <=  4'd3;endcasecase(B[31:36])//S66'b000000 :    S[21:24] <=  4'd12;6'b000001 :    S[21:24] <=  4'd10;6'b000010 :    S[21:24] <=  4'd1;6'b000011 :    S[21:24] <=  4'd15;6'b000100 :    S[21:24] <=  4'd10;6'b000101 :    S[21:24] <=  4'd4;6'b000110 :    S[21:24] <=  4'd15;6'b000111 :    S[21:24] <=  4'd2;6'b001000 :    S[21:24] <=  4'd9;6'b001001 :    S[21:24] <=  4'd7;6'b001010 :    S[21:24] <=  4'd2;6'b001011 :    S[21:24] <=  4'd12;6'b001100 :    S[21:24] <=  4'd6;6'b001101 :    S[21:24] <=  4'd9;6'b001110 :    S[21:24] <=  4'd8;6'b001111 :    S[21:24] <=  4'd5;6'b010000 :    S[21:24] <=  4'd0;6'b010001 :    S[21:24] <=  4'd6;6'b010010 :    S[21:24] <=  4'd13;6'b010011 :    S[21:24] <=  4'd1;6'b010100 :    S[21:24] <=  4'd3;6'b010101 :    S[21:24] <=  4'd13;6'b010110 :    S[21:24] <=  4'd4;6'b010111 :    S[21:24] <=  4'd14;6'b011000 :    S[21:24] <=  4'd14;6'b011001 :    S[21:24] <=  4'd0;6'b011010 :    S[21:24] <=  4'd7;6'b011011 :    S[21:24] <=  4'd11;6'b011100 :    S[21:24] <=  4'd5;6'b011101 :    S[21:24] <=  4'd3;6'b011110 :    S[21:24] <=  4'd11;6'b011111 :    S[21:24] <=  4'd8;6'b100000 :    S[21:24] <=  4'd9;6'b100001 :    S[21:24] <=  4'd4;6'b100010 :    S[21:24] <=  4'd14;6'b100011 :    S[21:24] <=  4'd3;6'b100100 :    S[21:24] <=  4'd15;6'b100101 :    S[21:24] <=  4'd2;6'b100110 :    S[21:24] <=  4'd5;6'b100111 :    S[21:24] <=  4'd12;6'b101000 :    S[21:24] <=  4'd2;6'b101001 :    S[21:24] <=  4'd9;6'b101010 :    S[21:24] <=  4'd8;6'b101011 :    S[21:24] <=  4'd5;6'b101100 :    S[21:24] <=  4'd12;6'b101101 :    S[21:24] <=  4'd15;6'b101110 :    S[21:24] <=  4'd3;6'b101111 :    S[21:24] <=  4'd10;6'b110000 :    S[21:24] <=  4'd7;6'b110001 :    S[21:24] <=  4'd11;6'b110010 :    S[21:24] <=  4'd0;6'b110011 :    S[21:24] <=  4'd14;6'b110100 :    S[21:24] <=  4'd4;6'b110101 :    S[21:24] <=  4'd1;6'b110110 :    S[21:24] <=  4'd10;6'b110111 :    S[21:24] <=  4'd7;6'b111000 :    S[21:24] <=  4'd1;6'b111001 :    S[21:24] <=  4'd6;6'b111010 :    S[21:24] <=  4'd13;6'b111011 :    S[21:24] <=  4'd0;6'b111100 :    S[21:24] <=  4'd11;6'b111101 :    S[21:24] <=  4'd8;6'b111110 :    S[21:24] <=  4'd6;6'b111111 :    S[21:24] <=  4'd13;endcasecase(B[37:42])//S76'b000000 :    S[25:28] <=  4'd4;6'b000001 :    S[25:28] <=  4'd13;6'b000010 :    S[25:28] <=  4'd11;6'b000011 :    S[25:28] <=  4'd0;6'b000100 :    S[25:28] <=  4'd2;6'b000101 :    S[25:28] <=  4'd11;6'b000110 :    S[25:28] <=  4'd14;6'b000111 :    S[25:28] <=  4'd7;6'b001000 :    S[25:28] <=  4'd15;6'b001001 :    S[25:28] <=  4'd4;6'b001010 :    S[25:28] <=  4'd0;6'b001011 :    S[25:28] <=  4'd9;6'b001100 :    S[25:28] <=  4'd8;6'b001101 :    S[25:28] <=  4'd1;6'b001110 :    S[25:28] <=  4'd13;6'b001111 :    S[25:28] <=  4'd10;6'b010000 :    S[25:28] <=  4'd3;6'b010001 :    S[25:28] <=  4'd14;6'b010010 :    S[25:28] <=  4'd12;6'b010011 :    S[25:28] <=  4'd3;6'b010100 :    S[25:28] <=  4'd9;6'b010101 :    S[25:28] <=  4'd5;6'b010110 :    S[25:28] <=  4'd7;6'b010111 :    S[25:28] <=  4'd12;6'b011000 :    S[25:28] <=  4'd5;6'b011001 :    S[25:28] <=  4'd2;6'b011010 :    S[25:28] <=  4'd10;6'b011011 :    S[25:28] <=  4'd15;6'b011100 :    S[25:28] <=  4'd6;6'b011101 :    S[25:28] <=  4'd8;6'b011110 :    S[25:28] <=  4'd1;6'b011111 :    S[25:28] <=  4'd6;6'b100000 :    S[25:28] <=  4'd1;6'b100001 :    S[25:28] <=  4'd6;6'b100010 :    S[25:28] <=  4'd4;6'b100011 :    S[25:28] <=  4'd11;6'b100100 :    S[25:28] <=  4'd11;6'b100101 :    S[25:28] <=  4'd13;6'b100110 :    S[25:28] <=  4'd13;6'b100111 :    S[25:28] <=  4'd8;6'b101000 :    S[25:28] <=  4'd12;6'b101001 :    S[25:28] <=  4'd1;6'b101010 :    S[25:28] <=  4'd3;6'b101011 :    S[25:28] <=  4'd4;6'b101100 :    S[25:28] <=  4'd7;6'b101101 :    S[25:28] <=  4'd10;6'b101110 :    S[25:28] <=  4'd14;6'b101111 :    S[25:28] <=  4'd7;6'b110000 :    S[25:28] <=  4'd10;6'b110001 :    S[25:28] <=  4'd9;6'b110010 :    S[25:28] <=  4'd15;6'b110011 :    S[25:28] <=  4'd5;6'b110100 :    S[25:28] <=  4'd6;6'b110101 :    S[25:28] <=  4'd0;6'b110110 :    S[25:28] <=  4'd8;6'b110111 :    S[25:28] <=  4'd15;6'b111000 :    S[25:28] <=  4'd0;6'b111001 :    S[25:28] <=  4'd14;6'b111010 :    S[25:28] <=  4'd5;6'b111011 :    S[25:28] <=  4'd2;6'b111100 :    S[25:28] <=  4'd9;6'b111101 :    S[25:28] <=  4'd3;6'b111110 :    S[25:28] <=  4'd2;6'b111111 :    S[25:28] <=  4'd12;endcasecase(B[43:48])//S86'b000000 :    S[29:32] <=  4'd13;6'b000001 :    S[29:32] <=  4'd1;6'b000010 :    S[29:32] <=  4'd2;6'b000011 :    S[29:32] <=  4'd15;6'b000100 :    S[29:32] <=  4'd8;6'b000101 :    S[29:32] <=  4'd13;6'b000110 :    S[29:32] <=  4'd4;6'b000111 :    S[29:32] <=  4'd8;6'b001000 :    S[29:32] <=  4'd6;6'b001001 :    S[29:32] <=  4'd10;6'b001010 :    S[29:32] <=  4'd15;6'b001011 :    S[29:32] <=  4'd3;6'b001100 :    S[29:32] <=  4'd11;6'b001101 :    S[29:32] <=  4'd7;6'b001110 :    S[29:32] <=  4'd1;6'b001111 :    S[29:32] <=  4'd4;6'b010000 :    S[29:32] <=  4'd10;6'b010001 :    S[29:32] <=  4'd12;6'b010010 :    S[29:32] <=  4'd9;6'b010011 :    S[29:32] <=  4'd5;6'b010100 :    S[29:32] <=  4'd3;6'b010101 :    S[29:32] <=  4'd6;6'b010110 :    S[29:32] <=  4'd14;6'b010111 :    S[29:32] <=  4'd11;6'b011000 :    S[29:32] <=  4'd5;6'b011001 :    S[29:32] <=  4'd0;6'b011010 :    S[29:32] <=  4'd0;6'b011011 :    S[29:32] <=  4'd14;6'b011100 :    S[29:32] <=  4'd12;6'b011101 :    S[29:32] <=  4'd9;6'b011110 :    S[29:32] <=  4'd7;6'b011111 :    S[29:32] <=  4'd2;6'b100000 :    S[29:32] <=  4'd7;6'b100001 :    S[29:32] <=  4'd2;6'b100010 :    S[29:32] <=  4'd11;6'b100011 :    S[29:32] <=  4'd1;6'b100100 :    S[29:32] <=  4'd4;6'b100101 :    S[29:32] <=  4'd14;6'b100110 :    S[29:32] <=  4'd1;6'b100111 :    S[29:32] <=  4'd7;6'b101000 :    S[29:32] <=  4'd9;6'b101001 :    S[29:32] <=  4'd4;6'b101010 :    S[29:32] <=  4'd12;6'b101011 :    S[29:32] <=  4'd10;6'b101100 :    S[29:32] <=  4'd14;6'b101101 :    S[29:32] <=  4'd8;6'b101110 :    S[29:32] <=  4'd2;6'b101111 :    S[29:32] <=  4'd13;6'b110000 :    S[29:32] <=  4'd0;6'b110001 :    S[29:32] <=  4'd15;6'b110010 :    S[29:32] <=  4'd6;6'b110011 :    S[29:32] <=  4'd12;6'b110100 :    S[29:32] <=  4'd10;6'b110101 :    S[29:32] <=  4'd9;6'b110110 :    S[29:32] <=  4'd13;6'b110111 :    S[29:32] <=  4'd0;6'b111000 :    S[29:32] <=  4'd15;6'b111001 :    S[29:32] <=  4'd3;6'b111010 :    S[29:32] <=  4'd3;6'b111011 :    S[29:32] <=  4'd5;6'b111100 :    S[29:32] <=  4'd5;6'b111101 :    S[29:32] <=  4'd6;6'b111110 :    S[29:32] <=  4'd8;6'b111111 :    S[29:32] <=  4'd11;endcasedown_s<=1'b1;endelsedown_s<=down_s;end
end
always @(posedge clk or negedge rst_n) beginif(~rst_n) beginout <= 32'b0;down_p<=1'b0;endelse beginif(down_s) beginout <={   S[16],S[7] ,S[20],S[21],S[29],S[12],S[28],S[17],S[1], S[15],S[23],S[26],S[5], S[18],S[31],S[10],S[2], S[8] ,S[24],S[14],S[32],S[27],S[3] ,S[9],S[19],S[13],S[30],S[6],S[22],S[11],S[4] ,S[25]};down_p<=1'b1;endelse beginout <= out;down_p<=down_p;endend
end
assign down_f = down_p&down_s;
endmodule

3.2 最终置换模块

module DIP(input                     clk,input                       rst_n,input         [1:64]  data,output reg [0:63]  out,output  reg         down_DIP,input                      en_DIP
);always @(posedge clk or negedge rst_n) beginif(~rst_n)beginout <= 64'b0;down_DIP<= 1'b0;endelse beginif(en_DIP)beginout <={data[40],data[8],data[48],data[16],data[56],data[24],data[64],data[32],data[39],data[7],data[47],data[15],data[55],data[23],data[63],data[31],data[38],data[6],data[46],data[14],data[54],data[22],data[62],data[30],data[37],data[5],data[45],data[13],data[53],data[21],data[61],data[29],data[36],data[4],data[44],data[12],data[52],data[20],data[60],data[28],data[35],data[3],data[43],data[11],data[51],data[19],data[59],data[27],data[34],data[2],data[42],data[10],data[50],data[18],data[58],data[26],data[33],data[1],data[41],data[9],data[49],data[17],data[57],data[25]};down_DIP<=1'b1;endelse beginout <= out;down_DIP<=down_DIP;endendendendmodule

顶层

module DES_TOP(input                 clk,input                   rst_n,output    [0:63]  result
);
//*********状态机部分***********//
wire        [0:63]  data;
wire        [0:63]  key;
assign  data = 64'b0000_0001_0010_0011_0100_0101_0110_0111_1000_1001_1010_1011_1100_1101_1110_1111;
assign   key  = 64'b0001_0011_0011_0100_0101_0111_0111_1001_1001_1011_1011_1100_1101_1111_1111_0001;parameter SLEEP   =  6'b000001;
parameter PC_1  =  6'b000010;
parameter PC_2      =  6'b000100;
parameter IP        =  6'b001000;
parameter CODING    =  6'b010000;
parameter DIP       =  6'b100000;reg  [0:5] corrent_state;
reg [0:5] next_state;wire   down_pc1,down_pc2,down_IP,down_DIP;
reg     en_pc1,en_pc2,en_IP,en_DIP;
wire [1:16] down_f;
reg  [1:16] en_f;wire [1:48] k1,k2,k3,k4,k5,k6,k7,k8,k9,k10,k11,k12,k13,k14,k15,k16;always @(posedge clk or negedge rst_n)beginif(~rst_n) begincorrent_state <= SLEEP;endelse begincorrent_state <= next_state;endendalways @(posedge clk or negedge rst_n)beginif(~rst_n) beginen_pc1<=1'b0;en_pc2<=1'b0;en_IP <=1'b0;en_f[1]<=1'b0;en_DIP <=1'b0;endelse begincase(corrent_state)6'b000010: beginen_pc1<=1'b1;end6'b000100: beginen_pc2<=1'b1;end6'b001000:beginen_IP<=1'b1;end6'b010000:beginen_f[1]<=1'b1;end6'b100000:beginen_DIP<=1'b1;enddefault:begin endendcaseendendalways @(*)beginif(~rst_n) beginnext_state = SLEEP;endelse begincase(corrent_state)6'b000001: begin next_state = PC_1; end6'b000010: begin if(down_pc1) next_state = PC_2;end6'b000100: begin if(down_pc2) next_state = IP;end6'b001000: begin if(down_IP)  next_state = CODING;end6'b010000: begin if(down_f[16]) next_state=DIP;end6'b100000: begin if(down_DIP) next_state = next_state;enddefault  : next_state = SLEEP;endcaseend
end
wire [1:56] pc1_out;
wire [1:56*16]  pc2_out;
wire [0:63] IP_out;
wire [0:63] DIP_out;
key_pc1 key_pc1_u(clk,rst_n,key,pc1_out,down_pc1,en_pc1);key_pc2 key_pc2_u(clk,rst_n,pc1_out,pc2_out,down_pc2,en_pc2);IP          IP_u    (clk,rst_n,data,IP_out,down_IP,en_IP);
assign {k1,k2,k3,k4,k5,k6,k7,k8,k9,k10,k11,k12,k13,k14,k15,k16} = pc2_out;//CODING连6'b100000:接&例化部分
wire [1:32] R0,R1,R2,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,R13,R14,R15,R16;
wire [1:32] L0,L1,L2,L3,L4,L5,L6,L7,L8,L9,L10,L11,L12,L13,L14,L15,L16;
wire [1:32] f1,f2,f3,f4,f5,f6,f7,f8,f9,f10,f11,f12,f13,f14,f15,f16;
assign {L0,R0}=IP_out;assign R1 = L0^f1;assign L1 = R0;
assign R2 = L1^f2;assign L2 = R1;
assign R3 = L2^f3;assign L3 = R2;
assign R4 = L3^f4;assign L4 = R3;
assign R5 = L4^f5;assign L5 = R4;
assign R6 = L5^f6;assign L6 = R5;
assign R7 = L6^f7;assign L7 = R6;
assign R8 = L7^f8;assign L8 = R7;
assign R9 = L8^f9;assign L9 = R8;
assign R10 = L9^f10;assign L10 = R9;
assign R11 = L10^f11;assign L11 = R10;
assign R12 = L11^f12;assign L12 = R11;
assign R13 = L12^f13;assign L13 = R12;
assign R14 = L13^f14;assign L14 = R13;
assign R15 = L14^f15;assign L15 = R14;
assign R16 = L15^f16;assign L16 = R15;
genvar i;generate for(i=1;i<16;i=i+1)begin :enalways@(*) begin en_f[i+1]=down_f[i];endend
endgeneratef f_1(clk,rst_n,R0,k1,f1,down_f[1],en_f[1]);
f f_2(clk,rst_n,R1,k2,f2,down_f[2],en_f[2]);
f f_3(clk,rst_n,R2,k3,f3,down_f[3],en_f[3]);
f f_4(clk,rst_n,R3,k4,f4,down_f[4],en_f[4]);
f f_5(clk,rst_n,R4,k5,f5,down_f[5],en_f[5]);
f f_6(clk,rst_n,R5,k6,f6,down_f[6],en_f[6]);
f f_7(clk,rst_n,R6,k7,f7,down_f[7],en_f[7]);
f f_8(clk,rst_n,R7,k8,f8,down_f[8],en_f[8]);
f f_9(clk,rst_n,R8,k9,f9,down_f[9],en_f[9]);
f f_10(clk,rst_n,R9,k10,f10,down_f[10],en_f[10]);
f f_11(clk,rst_n,R10,k11,f11,down_f[11],en_f[11]);
f f_12(clk,rst_n,R11,k12,f12,down_f[12],en_f[12]);
f f_13(clk,rst_n,R12,k13,f13,down_f[13],en_f[13]);
f f_14(clk,rst_n,R13,k14,f14,down_f[14],en_f[14]);
f f_15(clk,rst_n,R14,k15,f15,down_f[15],en_f[15]);
f f_16(clk,rst_n,R15,k16,f16,down_f[16],en_f[16]);DIP         DIP_u   (clk,rst_n,{R16,L16},DIP_out,down_DIP,en_DIP);assign result = DIP_out;
endmodule

仿真结果

上课的作业，说用什么语言写都行。正好在自学fpga，就想着写写看（孩子不懂事写着玩的）。怎么说呢？感觉除了提高了点debug的熟练度，就没啥收获了，挺费力不讨好的哈哈哈哈。接下来还是去看看有没有什么项目可以练手。