module pfd(reset, clk_40mhz, clk_128k, clk_fb_500, phase_value, clk_ref_out);input reset;
input clk_128k;  //两次分频得到的128Khz的时钟
input clk_fb_500; //电机的反馈时钟500hz
input clk_40mhz;reg  clk_ref_500;
output [7:0] phase_value;
reg [7:0] phase_reg;
output clk_ref_out;reg [7:0] cout_8bit; //8位计数器
reg [7:0] ph_reg; //8位寄存器
reg have_flag;
reg clk_fb_prv;
reg clk_ref_prv;
reg [7:0] phase_value_1;
reg [7:0] phase_value_tmp;
parameter PHASE_MAX_VALUE = 8'h7F;

wire cout_en;//8位计数器，一个always里面可以写2个if语句吗？
always @(posedge clk_128k or negedge reset) beginif(!reset)cout_8bit <= 8'b0;else cout_8bit <= cout_8bit + 1'b1;
end//产生参考时钟500HZ
always @(posedge clk_40mhz) beginif(cout_8bit == 8'h0) clk_ref_500 <= 0;else if(cout_8bit == 8'h7f)clk_ref_500 <= 1;elseclk_ref_500 <= clk_ref_500;
end//D触发器，边沿检测反馈信号上升沿和参考信号下降沿
/*
always @(posedge clk_fb_500 or negedge clk_ref_500) beginif(clk_fb_500 == 1) beginhave_flag = 1;clk_fb_prv = clk_fb_500;phase_value_1 = cout_8bit; endelse if(clk_ref_500 == 0) begin have_flag = 0;phase_value = phase_value_tmp; endelse have_flag = 0;end
*/always @(posedge clk_40mhz) beginclk_fb_prv <= clk_fb_500;clk_ref_prv <= clk_ref_500;if({clk_fb_prv,clk_fb_500} == 2'b01) begin //判断反馈信号的上升沿have_flag <= 1;phase_value_1 <= cout_8bit; endelse if({clk_ref_prv,clk_ref_500} == 2'b01) begin  //判断参考信号的上升沿have_flag <= 0;phase_reg <= phase_value_tmp; endelse have_flag <= have_flag;end//怎么去解决一个周期内有2个反馈信号的上升沿的问题？
//总线选通开关
always @(posedge clk_40mhz)begin if(have_flag == 1)phase_value_tmp <= phase_value_1;elsephase_value_tmp <= PHASE_MAX_VALUE;end
//PFD输出
//always @(posedge clk_128k)

assign clk_ref_out = clk_ref_500;
assign phase_value = phase_reg;
endmodule