SI5341驱动（verilog）

通过spi时序对si5341的寄存器进行配置；
为验证逻辑的正确性将数据写入寄存器，并通过读模块将代码读出，具体代码如下：

`timescale 1ns / 1psmodule si5341_drive#(parameter   integer        NO_OF_DIV  =  100      //100M时钟百分频
)
(input       wire                clk,input       wire                rst_n,input       wire                rd_flag,output      reg        [7:0]    rd_data, output      reg                 spi_cs_n,output      reg                 spi_mosi,output      reg                 spi_sclk,input       wire                spi_miso
);localparam      T_DELAY            =  30_000_000;   //delay 300mslocalparam      WR_CMD           =  8'b0100_0000;localparam       RD_CMD           =  8'b1000_0000;localparam       T_CYCLE          =  7400;        // one addr time localparam       HALF_OF_DIV     =   NO_OF_DIV / 2; localparam      IDLE_STATE      =   7'b000_0001;localparam      INIT_STATE      =   7'b000_0010;localparam      WAIT_STATE      =   7'b000_0100;localparam      CONF_DONE_STATE =   7'b000_1000;localparam      WAIT_CMD_STATE  =   7'b001_0000;localparam      RD_REG_STATE    =   7'b010_0000;localparam      FINISH_STATE    =  7'b100_0000;reg                    [23:0]         addr;reg                 [8:0]          reg_index;reg                 [6:0]          current_state;reg                 [6:0]          next_state;reg                 [25:0]         cnt_delay;reg                                   wr_done;reg                                 rd_done;reg                  [15:0]         cnt_index;       integer cnt_1_sck_cycle;            //产生SCK的时钟计数器integer cnt_sck;                   //SCK计数always @ (posedge clk)   beginif(rst_n == 1'b0)current_state <= IDLE_STATE;elsecurrent_state <= next_state; endalways @ (*)    beginif(rst_n == 1'b0)   beginnext_state = IDLE_STATE;endelse    begincase(current_state)IDLE_STATE      :   begin    next_state = INIT_STATE;endINIT_STATE      :   begin   if(wr_done == 1'b1) beginif(reg_index == 9'd6 && cnt_delay < 1)next_state = WAIT_STATE;elseif(reg_index == 9'd387)next_state = CONF_DONE_STATE;elsenext_state = INIT_STATE;endendWAIT_STATE      :   begin    next_state = (cnt_delay == T_DELAY) ? INIT_STATE  :  WAIT_STATE;  endCONF_DONE_STATE :   begin    next_state = (wr_done == 1'b1) ? WAIT_CMD_STATE : CONF_DONE_STATE;  endWAIT_CMD_STATE  :   begin    next_state = (rd_flag == 1'b1) ? RD_REG_STATE :   WAIT_CMD_STATE; endRD_REG_STATE    :   begin    next_state = (rd_done == 1'b1 && reg_index == 9'd387)? FINISH_STATE : RD_REG_STATE;  endFINISH_STATE    :   begin    next_state = FINISH_STATE;    enddefault :  next_state = IDLE_STATE;endcaseendend always @ (posedge clk)   beginif(rst_n == 1'b0)   beginrd_data <= 8'd0;spi_cs_n <= 1'b1;spi_mosi <= 1'b1;wr_done <= 1'b0;cnt_delay <= 26'd0;cnt_1_sck_cycle <= 0;cnt_sck  <= 0;spi_sclk <= 1'b0;reg_index <= 9'd0;cnt_index <= 16'd0;endelse    begincase(next_state)IDLE_STATE  :   beginrd_data <= 8'd0;spi_cs_n <= 1'b1;spi_mosi <= 1'b1;wr_done <= 1'b0;cnt_delay <= 26'd0;cnt_1_sck_cycle <= 0;cnt_sck  <= 0;spi_sclk <= 1'b0;reg_index <= 9'd0;cnt_index <= 16'd0;endINIT_STATE  :   beginif(cnt_1_sck_cycle<NO_OF_DIV-1) begincnt_1_sck_cycle <= cnt_1_sck_cycle+1;endelse begincnt_1_sck_cycle <= 0;endif(cnt_1_sck_cycle == NO_OF_DIV-1 && cnt_index != T_CYCLE - 1)   begincnt_sck <= cnt_sck+1;endelse  beginif(cnt_index == T_CYCLE - 1)cnt_sck <= 0;elsecnt_sck <= cnt_sck;endif(cnt_index < T_CYCLE - 1)    begincnt_index <= cnt_index + 1;endelse    begincnt_index <= 16'd0;endreg_index <= (cnt_index == T_CYCLE - 1) ? (reg_index + 1'b1) : reg_index;spi_sclk <= (cnt_1_sck_cycle<HALF_OF_DIV) ? 1'b0 : 1'b1;case(cnt_sck)0     :   begin  spi_cs_n <= 1'b1;   spi_mosi <= 1'b0;   wr_done <= 1'b0; end1     :   begin  spi_cs_n <= 1'b1;   spi_mosi <= 1'b0;             end2     :   begin  spi_cs_n <= 1'b1;   spi_mosi <= 1'b0;             end3     :   begin  spi_cs_n <= 1'b0;   spi_mosi <= 0;  end 4     :   begin  spi_cs_n <= 1'b0;   spi_mosi <= 0;  end 5     :   begin  spi_cs_n <= 1'b0;   spi_mosi <= 0;  end 6     :   begin  spi_cs_n <= 1'b0;   spi_mosi <= 0;  end 7     :   begin  spi_cs_n <= 1'b0;   spi_mosi <= 0;  end 8     :   begin  spi_cs_n <= 1'b0;   spi_mosi <= 0;  end 9     :   begin  spi_cs_n <= 1'b0;   spi_mosi <= 0;  end 10    :   begin  spi_cs_n <= 1'b0;   spi_mosi <= 0;  end 11    :   begin  spi_cs_n <= 1'b0;   spi_mosi <= 0;  end12    :   begin  spi_cs_n <= 1'b0;   spi_mosi <= 0;  end 13    :   begin  spi_cs_n <= 1'b0;   spi_mosi <= 0;  end 14    :   begin  spi_cs_n <= 1'b0;   spi_mosi <= 0;  end 15    :   begin  spi_cs_n <= 1'b0;   spi_mosi <= 0;  end 16    :   begin  spi_cs_n <= 1'b0;   spi_mosi <= 0;  end 17    :   begin  spi_cs_n <= 1'b0;   spi_mosi <= 0;  end 18    :   begin  spi_cs_n <= 1'b0;   spi_mosi <= 1;  end  19    :   begin  spi_cs_n <= 1'b1;   spi_mosi <= 1'b0;             end 20    :   begin  spi_cs_n <= 1'b1;   spi_mosi <= 1'b0;            end21    :   begin  spi_cs_n <= 1'b0;   spi_mosi <= WR_CMD[7];     end22    :   begin  spi_cs_n <= 1'b0;   spi_mosi <= WR_CMD[6];     end23    :   begin  spi_cs_n <= 1'b0;   spi_mosi <= WR_CMD[5];     end24    :   begin  spi_cs_n <= 1'b0;   spi_mosi <= WR_CMD[4];     end25    :   begin  spi_cs_n <= 1'b0;   spi_mosi <= WR_CMD[3];     end26    :   begin  spi_cs_n <= 1'b0;   spi_mosi <= WR_CMD[2];     end27    :   begin  spi_cs_n <= 1'b0;   spi_mosi <= WR_CMD[1];     end28    :   begin  spi_cs_n <= 1'b0;   spi_mosi <= WR_CMD[0];     end   29    :   begin  spi_cs_n <= 1'b0;   spi_mosi <= addr[23];  end30    :   begin  spi_cs_n <= 1'b0;   spi_mosi <= addr[22];  end31    :   begin  spi_cs_n <= 1'b0;   spi_mosi <= addr[21];  end32    :   begin  spi_cs_n <= 1'b0;   spi_mosi <= addr[20];  end33    :   begin  spi_cs_n <= 1'b0;   spi_mosi <= addr[19];  end34    :   begin  spi_cs_n <= 1'b0;   spi_mosi <= addr[18];  end35    :   begin  spi_cs_n <= 1'b0;   spi_mosi <= addr[17];  end36    :   begin  spi_cs_n <= 1'b0;   spi_mosi <= addr[16];  end   37    :   begin  spi_cs_n <= 1'b1;   spi_mosi <= 1'b0;           end 38    :   begin  spi_cs_n <= 1'b1;   spi_mosi <= 1'b0;            end39    :   begin  spi_cs_n <= 1'b0;   spi_mosi <= 0;     end40    :   begin  spi_cs_n <= 1'b0;   spi_mosi <= 0;     end41    :   begin  spi_cs_n <= 1'b0;   spi_mosi <= 0;     end42    :   begin  spi_cs_n <= 1'b0;   spi_mosi <= 0;     end43    :   begin  spi_cs_n <= 1'b0;   spi_mosi <= 0;     end44    :   begin  spi_cs_n <= 1'b0;   spi_mosi <= 0;     end45    :   begin  spi_cs_n <= 1'b0;   spi_mosi <= 0;     end46    :   begin  spi_cs_n <= 1'b0;   spi_mosi <= 0;     end  47    :   begin  spi_cs_n <= 1'b0;   spi_mosi <= addr[15];  end48    :   begin  spi_cs_n <= 1'b0;   spi_mosi <= addr[14];  end49    :   begin  spi_cs_n <= 1'b0;   spi_mosi <= addr[13];  end50    :   begin  spi_cs_n <= 1'b0;   spi_mosi <= addr[12];  end51    :   begin  spi_cs_n <= 1'b0;   spi_mosi <= addr[11];  end52    :   begin  spi_cs_n <= 1'b0;   spi_mosi <= addr[10];  end53    :   begin  spi_cs_n <= 1'b0;   spi_mosi <= addr[9];  end54    :   begin  spi_cs_n <= 1'b0;   spi_mosi <= addr[8];  end 55    :   begin  spi_cs_n <= 1'b1;   spi_mosi <= 1'b0;            end 56    :   begin  spi_cs_n <= 1'b1;   spi_mosi <= 1'b0;            end57    :   begin  spi_cs_n <= 1'b0;   spi_mosi <= WR_CMD[7];     end58    :   begin  spi_cs_n <= 1'b0;   spi_mosi <= WR_CMD[6];     end59    :   begin  spi_cs_n <= 1'b0;   spi_mosi <= WR_CMD[5];     end60    :   begin  spi_cs_n <= 1'b0;   spi_mosi <= WR_CMD[4];     end61    :   begin  spi_cs_n <= 1'b0;   spi_mosi <= WR_CMD[3];     end62    :   begin  spi_cs_n <= 1'b0;   spi_mosi <= WR_CMD[2];     end63    :   begin  spi_cs_n <= 1'b0;   spi_mosi <= WR_CMD[1];     end64    :   begin  spi_cs_n <= 1'b0;   spi_mosi <= WR_CMD[0];     end   65    :   begin  spi_cs_n <= 1'b0;   spi_mosi <= addr[7];    end66    :   begin  spi_cs_n <= 1'b0;   spi_mosi <= addr[6];       end67    :   begin  spi_cs_n <= 1'b0;   spi_mosi <= addr[5];   end68    :   begin  spi_cs_n <= 1'b0;   spi_mosi <= addr[4];       end69    :   begin  spi_cs_n <= 1'b0;   spi_mosi <= addr[3];       end70    :   begin  spi_cs_n <= 1'b0;   spi_mosi <= addr[2];       end71    :   begin  spi_cs_n <= 1'b0;   spi_mosi <= addr[1];       end72    :   begin  spi_cs_n <= 1'b0;   spi_mosi <= addr[0];       end   73    :   begin  spi_cs_n <= 1'b1;   spi_mosi <= 1'b0;   wr_done <= 1'b1;  enddefault : ;endcaseendWAIT_STATE  :   beginif(cnt_delay < T_DELAY)cnt_delay <= cnt_delay + 1'b1;elsecnt_delay <= cnt_delay;endWAIT_CMD_STATE :   beginreg_index <= 9'd0;endRD_REG_STATE :   beginif(cnt_1_sck_cycle<NO_OF_DIV-1) begincnt_1_sck_cycle <= cnt_1_sck_cycle+1;endelse begincnt_1_sck_cycle <= 0;endif(cnt_1_sck_cycle == NO_OF_DIV-1 && cnt_index != T_CYCLE - 1)   begincnt_sck <= cnt_sck+1;endelse  beginif(cnt_index == T_CYCLE - 1)cnt_sck <= 0;elsecnt_sck <= cnt_sck;endif(cnt_index < T_CYCLE - 1)    begincnt_index <= cnt_index + 1;endelse    begincnt_index <= 16'd0;endreg_index <= (cnt_index == T_CYCLE - 1) ? (reg_index + 1'b1) : reg_index;spi_sclk <= (cnt_1_sck_cycle<HALF_OF_DIV) ? 1'b0 : 1'b1;case(cnt_sck)0     :   begin  spi_cs_n <= 1'b1;   spi_mosi <= 1'b0;  rd_done <= 1'b0;   end1     :   begin  spi_cs_n <= 1'b1;   spi_mosi <= 1'b0;            end2     :   begin  spi_cs_n <= 1'b1;   spi_mosi <= 1'b0;             end3     :   begin  spi_cs_n <= 1'b0;   spi_mosi <= 0;  end 4     :   begin  spi_cs_n <= 1'b0;   spi_mosi <= 0;  end 5     :   begin  spi_cs_n <= 1'b0;   spi_mosi <= 0;  end 6     :   begin  spi_cs_n <= 1'b0;   spi_mosi <= 0;  end 7     :   begin  spi_cs_n <= 1'b0;   spi_mosi <= 0;  end 8     :   begin  spi_cs_n <= 1'b0;   spi_mosi <= 0;  end 9     :   begin  spi_cs_n <= 1'b0;   spi_mosi <= 0;  end 10    :   begin  spi_cs_n <= 1'b0;   spi_mosi <= 0;  end 11    :   begin  spi_cs_n <= 1'b0;   spi_mosi <= 0;   end12    :   begin  spi_cs_n <= 1'b0;   spi_mosi <= 0;   end 13    :   begin  spi_cs_n <= 1'b0;   spi_mosi <= 0;   end 14    :   begin  spi_cs_n <= 1'b0;   spi_mosi <= 0;   end 15    :   begin  spi_cs_n <= 1'b0;   spi_mosi <= 0;   end 16    :   begin  spi_cs_n <= 1'b0;   spi_mosi <= 0;   end 17    :   begin  spi_cs_n <= 1'b0;   spi_mosi <= 0;   end 18    :   begin  spi_cs_n <= 1'b0;   spi_mosi <= 1;   end  19    :   begin  spi_cs_n <= 1'b1;   spi_mosi <= 1'b0;             end 20    :   begin  spi_cs_n <= 1'b1;   spi_mosi <= 1'b0;            end21    :   begin  spi_cs_n <= 1'b0;   spi_mosi <= WR_CMD[7];     end22    :   begin  spi_cs_n <= 1'b0;   spi_mosi <= WR_CMD[6];     end23    :   begin  spi_cs_n <= 1'b0;   spi_mosi <= WR_CMD[5];     end24    :   begin  spi_cs_n <= 1'b0;   spi_mosi <= WR_CMD[4];     end25    :   begin  spi_cs_n <= 1'b0;   spi_mosi <= WR_CMD[3];     end26    :   begin  spi_cs_n <= 1'b0;   spi_mosi <= WR_CMD[2];     end27    :   begin  spi_cs_n <= 1'b0;   spi_mosi <= WR_CMD[1];     end28    :   begin  spi_cs_n <= 1'b0;   spi_mosi <= WR_CMD[0];     end   29    :   begin  spi_cs_n <= 1'b0;   spi_mosi <= addr[23];  end30    :   begin  spi_cs_n <= 1'b0;   spi_mosi <= addr[22];  end31    :   begin  spi_cs_n <= 1'b0;   spi_mosi <= addr[21];  end32    :   begin  spi_cs_n <= 1'b0;   spi_mosi <= addr[20];  end33    :   begin  spi_cs_n <= 1'b0;   spi_mosi <= addr[19];  end34    :   begin  spi_cs_n <= 1'b0;   spi_mosi <= addr[18];  end35    :   begin  spi_cs_n <= 1'b0;   spi_mosi <= addr[17];  end36    :   begin  spi_cs_n <= 1'b0;   spi_mosi <= addr[16];  end   37    :   begin  spi_cs_n <= 1'b1;   spi_mosi <= 1'b0;           end 38    :   begin  spi_cs_n <= 1'b1;   spi_mosi <= 1'b0;            end39    :   begin  spi_cs_n <= 1'b0;   spi_mosi <= 0;     end40    :   begin  spi_cs_n <= 1'b0;   spi_mosi <= 0;     end41    :   begin  spi_cs_n <= 1'b0;   spi_mosi <= 0;     end42    :   begin  spi_cs_n <= 1'b0;   spi_mosi <= 0;     end43    :   begin  spi_cs_n <= 1'b0;   spi_mosi <= 0;     end44    :   begin  spi_cs_n <= 1'b0;   spi_mosi <= 0;     end45    :   begin  spi_cs_n <= 1'b0;   spi_mosi <= 0;     end46    :   begin  spi_cs_n <= 1'b0;   spi_mosi <= 0;     end  47    :   begin  spi_cs_n <= 1'b0;   spi_mosi <= addr[15];  end48    :   begin  spi_cs_n <= 1'b0;   spi_mosi <= addr[14];  end49    :   begin  spi_cs_n <= 1'b0;   spi_mosi <= addr[13];  end50    :   begin  spi_cs_n <= 1'b0;   spi_mosi <= addr[12];  end51    :   begin  spi_cs_n <= 1'b0;   spi_mosi <= addr[11];  end52    :   begin  spi_cs_n <= 1'b0;   spi_mosi <= addr[10];  end53    :   begin  spi_cs_n <= 1'b0;   spi_mosi <= addr[9];  end54    :   begin  spi_cs_n <= 1'b0;   spi_mosi <= addr[8];  end 55    :   begin  spi_cs_n <= 1'b1;   spi_mosi <= 1'b0;            end 56    :   begin  spi_cs_n <= 1'b1;   spi_mosi <= 1'b0;            end57    :   begin  spi_cs_n <= 1'b0;   spi_mosi <= RD_CMD[7];     end58    :   begin  spi_cs_n <= 1'b0;   spi_mosi <= RD_CMD[6];     end59    :   begin  spi_cs_n <= 1'b0;   spi_mosi <= RD_CMD[5];     end60    :   begin  spi_cs_n <= 1'b0;   spi_mosi <= RD_CMD[4];     end61    :   begin  spi_cs_n <= 1'b0;   spi_mosi <= RD_CMD[3];     end62    :   begin  spi_cs_n <= 1'b0;   spi_mosi <= RD_CMD[2];     end63    :   begin  spi_cs_n <= 1'b0;   spi_mosi <= RD_CMD[1];     end64    :   begin  spi_cs_n <= 1'b0;   spi_mosi <= RD_CMD[0];     end   65    :   begin  spi_cs_n <= 1'b0;   spi_mosi <= 1'b0; rd_data[7] <= spi_miso;  end66    :   begin  spi_cs_n <= 1'b0;   spi_mosi <= 1'b0; rd_data[6] <= spi_miso;  end67    :   begin  spi_cs_n <= 1'b0;   spi_mosi <= 1'b0; rd_data[5] <= spi_miso;  end68    :   begin  spi_cs_n <= 1'b0;   spi_mosi <= 1'b0; rd_data[4] <= spi_miso;  end69    :   begin  spi_cs_n <= 1'b0;   spi_mosi <= 1'b0; rd_data[3] <= spi_miso;  end70    :   begin  spi_cs_n <= 1'b0;   spi_mosi <= 1'b0; rd_data[2] <= spi_miso;  end71    :   begin  spi_cs_n <= 1'b0;   spi_mosi <= 1'b0; rd_data[1] <= spi_miso;  end72    :   begin  spi_cs_n <= 1'b0;   spi_mosi <= 1'b0; rd_data[0] <= spi_miso;  end   73    :   begin  spi_cs_n <= 1'b1;   spi_mosi <= 1'b0; rd_done <= 1'b1;        enddefault : ;endcaseendFINISH_STATE :   beginrd_data <= 8'd0;spi_cs_n <= 1'b1;spi_mosi <= 1'b1;spi_sclk <= 1'b0;enddefault : ;endcaseendend
***以下为寄存器的地址，根据官方的软件ClockBuilder Pro 根据不同的时钟输出得到不同的寄存器表***
always @ (*)    begincase(reg_index)0     :   addr  =24'h0B24C0;1     :   addr  =24'h0B2500;2     :   addr  =24'h050201;3     :   addr  =24'h050503;4     :   addr  =24'h095717;5     :   addr  =24'h0B4E1A;   6     :   addr  =24'h000600;7     :   addr  =24'h000700;8     :   addr  =24'h000800;9       :   addr  =24'h000B74;10    :   addr  =24'h0017D0;11    :   addr  =24'h0018FE;12    :   addr  =24'h002109;13    :   addr  =24'h002200;14    :     addr  =24'h002B02;15    :   addr  =24'h002C31;16    :   addr  =24'h002D01;17    :   addr  =24'h002E88;18    :   addr  =24'h002F00;19      :   addr  =24'h003000;20    :   addr  =24'h003100;21    :   addr  =24'h003200;22    :   addr  =24'h003300;23    :   addr  =24'h003400;24    :   addr  =24'h003500;25    :   addr  =24'h003688;26    :   addr  =24'h003700;27    :   addr  =24'h003800;28    :   addr  =24'h003900;29    :   addr  =24'h003A00;30    :   addr  =24'h003B00;31    :   addr  =24'h003C00;32    :   addr  =24'h003D00;33    :   addr  =24'h004106;34    :   addr  =24'h004200;35    :   addr  =24'h004300;36    :   addr  =24'h004400;37    :   addr  =24'h009E00;38    :   addr  =24'h010201;39    :   addr  =24'h010806;40    :   addr  =24'h010909;41    :   addr  =24'h010A3B;42    :   addr  =24'h010B28;43    :   addr  =24'h010D06;44    :   addr  =24'h010E09;45    :   addr  =24'h010F3B;46    :   addr  =24'h011028;47    :   addr  =24'h011206;48    :   addr  =24'h011309;49    :   addr  =24'h01143B;50    :   addr  =24'h011528;51    :   addr  =24'h011706;52    :   addr  =24'h011809;53    :   addr  =24'h01193B;54    :   addr  =24'h011A28;55    :   addr  =24'h011C06;56    :   addr  =24'h011D09;57    :   addr  =24'h011E3B;58    :   addr  =24'h011F28;59    :   addr  =24'h012106;60    :   addr  =24'h012209;61    :   addr  =24'h01233B;62    :   addr  =24'h012428;63    :   addr  =24'h012606;64    :   addr  =24'h012709;65    :   addr  =24'h01283B;66    :   addr  =24'h012928;67    :   addr  =24'h012B06;68    :   addr  =24'h012C09;69    :   addr  =24'h012D3B;70    :   addr  =24'h012E28;71    :   addr  =24'h013001;72    :   addr  =24'h013109;73    :   addr  =24'h01323B;74    :   addr  =24'h013328;75    :   addr  =24'h013A02;76    :   addr  =24'h013B09;77    :   addr  =24'h013C3B;78    :   addr  =24'h013D29;79    :   addr  =24'h013F00;80    :   addr  =24'h014000;81    :   addr  =24'h014140;82    :   addr  =24'h020600;83    :   addr  =24'h020801;84    :   addr  =24'h020900;85    :   addr  =24'h020A00;86    :   addr  =24'h020B00;87    :   addr  =24'h020C00;88    :   addr  =24'h020D00;89    :   addr  =24'h020E01;90    :   addr  =24'h020F00;91    :   addr  =24'h021000;92    :   addr  =24'h021100;93    :   addr  =24'h021200;94    :   addr  =24'h021300;95    :   addr  =24'h021400;96    :   addr  =24'h021500;97    :   addr  =24'h021600;98    :   addr  =24'h021700;99    :   addr  =24'h021800;100   :   addr  =24'h021900;101   :   addr  =24'h021A00;102   :   addr  =24'h021B00;103   :   addr  =24'h021C00;104   :   addr  =24'h021D00;105   :   addr  =24'h021E00;106   :   addr  =24'h021F00;107   :   addr  =24'h022000;108   :   addr  =24'h022100;109   :   addr  =24'h022200;110   :   addr  =24'h022300;111   :   addr  =24'h022400;112   :   addr  =24'h022500;113   :   addr  =24'h022600;114   :   addr  =24'h022700;115   :   addr  =24'h022800;116   :   addr  =24'h022900;117   :   addr  =24'h022A00;118   :   addr  =24'h022B00;119   :   addr  =24'h022C00;120   :   addr  =24'h022D00;121   :   addr  =24'h022E00;122   :   addr  =24'h022F00;123   :   addr  =24'h023500;124   :   addr  =24'h023600;125   :   addr  =24'h023700;126   :   addr  =24'h023800;127   :   addr  =24'h023942;128   :   addr  =24'h023A00;129   :   addr  =24'h023B00;130   :   addr  =24'h023C00;131   :   addr  =24'h023D00;132   :   addr  =24'h023E80;133   :   addr  =24'h024A00;134   :   addr  =24'h024B00;135   :   addr  =24'h024C00;136   :   addr  =24'h024D00;137   :   addr  =24'h024E00;138   :   addr  =24'h024F00;139   :   addr  =24'h025000;140   :   addr  =24'h025100;141   :   addr  =24'h025200;142   :   addr  =24'h025300;143   :   addr  =24'h025400;144   :   addr  =24'h025500;145   :   addr  =24'h025600;146   :   addr  =24'h025700;147   :   addr  =24'h025800;148   :   addr  =24'h025900;149   :   addr  =24'h025A00;150   :   addr  =24'h025B00;151   :   addr  =24'h025C00;152   :   addr  =24'h025D00;153   :   addr  =24'h025E00;154   :   addr  =24'h025F00;155   :   addr  =24'h026000;156   :   addr  =24'h026100;157   :   addr  =24'h026200;158   :   addr  =24'h026300;159   :   addr  =24'h026400;160   :   addr  =24'h026801;161   :   addr  =24'h026900;162   :   addr  =24'h026A00;163   :   addr  =24'h026B00;164   :   addr  =24'h026C00;165   :   addr  =24'h026D00;166   :   addr  =24'h026E00;167   :   addr  =24'h026F00;168   :   addr  =24'h027000;169   :   addr  =24'h027100;170   :   addr  =24'h027200;171   :   addr  =24'h030200;172   :   addr  =24'h030300;173   :   addr  =24'h030400;174   :   addr  =24'h030500;175   :   addr  =24'h03060B;176   :   addr  =24'h030700;177   :   addr  =24'h030800;178   :   addr  =24'h030900;179   :   addr  =24'h030A00;180   :   addr  =24'h030B80;181   :   addr  =24'h030C00;182   :   addr  =24'h030D00;183   :   addr  =24'h030E00;184   :   addr  =24'h030F00;185   :   addr  =24'h031080;186   :   addr  =24'h031110;187   :   addr  =24'h031200;188   :   addr  =24'h031300;189   :   addr  =24'h031400;190   :   addr  =24'h031500;191   :   addr  =24'h0316C8;192   :   addr  =24'h031700;193   :   addr  =24'h031800;194   :   addr  =24'h031900;195   :   addr  =24'h031A00;196   :   addr  =24'h031B00;197   :   addr  =24'h031C00;198   :   addr  =24'h031D00;199   :   addr  =24'h031E00;200   :   addr  =24'h031F00;201   :   addr  =24'h032000;202   :   addr  =24'h032100;203   :   addr  =24'h032200;204   :   addr  =24'h032300;205   :   addr  =24'h032400;206   :   addr  =24'h032500;207   :   addr  =24'h032600;208   :   addr  =24'h032700;209   :   addr  =24'h032800;210   :   addr  =24'h032900;211   :   addr  =24'h032A00;212   :   addr  =24'h032B00;213   :   addr  =24'h032C00;214   :   addr  =24'h032D00;215   :   addr  =24'h032E00;216   :   addr  =24'h032F00;217   :   addr  =24'h033000;218   :   addr  =24'h033100;219   :   addr  =24'h033200;220   :   addr  =24'h033300;221   :   addr  =24'h033400;222   :   addr  =24'h033500;223   :   addr  =24'h033600;224   :   addr  =24'h033700;225   :   addr  =24'h033800;226   :   addr  =24'h03391F;227   :   addr  =24'h033B00;228   :   addr  =24'h033C00;229   :   addr  =24'h033D00;230   :   addr  =24'h033E00;231   :   addr  =24'h033F00;232   :   addr  =24'h034000;233   :   addr  =24'h034100;234   :   addr  =24'h034200;235   :   addr  =24'h034300;236   :   addr  =24'h034400;237   :   addr  =24'h034500;238   :   addr  =24'h034600;239   :   addr  =24'h034700;240   :   addr  =24'h034800;241   :   addr  =24'h034900;242   :   addr  =24'h034A00;243   :   addr  =24'h034B00;244   :   addr  =24'h034C00;245   :   addr  =24'h034D00;246   :   addr  =24'h034E00;247   :   addr  =24'h034F00;248   :   addr  =24'h035000;249   :   addr  =24'h035100;250   :   addr  =24'h035200;251   :   addr  =24'h035300;252   :   addr  =24'h035400;253   :   addr  =24'h035500;254   :   addr  =24'h035600;255   :   addr  =24'h035700;256   :   addr  =24'h035800;257   :   addr  =24'h035900;258   :   addr  =24'h035A00;259   :   addr  =24'h035B00;260   :   addr  =24'h035C00;261   :   addr  =24'h035D00;262   :   addr  =24'h035E00;263   :   addr  =24'h035F00;264   :   addr  =24'h036000;265   :   addr  =24'h036100;266   :   addr  =24'h036200;267   :   addr  =24'h080200;268   :   addr  =24'h080300;269   :   addr  =24'h080400;270   :   addr  =24'h080500;271   :   addr  =24'h080600;272   :   addr  =24'h080700;273   :   addr  =24'h080800;274   :   addr  =24'h080900;275   :   addr  =24'h080A00;276   :   addr  =24'h080B00;277   :   addr  =24'h080C00;278   :   addr  =24'h080D00;279   :   addr  =24'h080E00;280   :   addr  =24'h080F00;281   :   addr  =24'h081000;282   :   addr  =24'h081100;283   :   addr  =24'h081200;284   :   addr  =24'h081300;285   :   addr  =24'h081400;286   :   addr  =24'h081500;287   :   addr  =24'h081600;288   :   addr  =24'h081700;289   :   addr  =24'h081800;290   :   addr  =24'h081900;291   :   addr  =24'h081A00;292   :   addr  =24'h081B00;293   :   addr  =24'h081C00;294   :   addr  =24'h081D00;295   :   addr  =24'h081E00;296   :   addr  =24'h081F00;297   :   addr  =24'h082000;298   :   addr  =24'h082100;299   :   addr  =24'h082200;300   :   addr  =24'h082300;301   :   addr  =24'h082400;302   :   addr  =24'h082500;303   :   addr  =24'h082600;304   :   addr  =24'h082700;305   :   addr  =24'h082800;306   :   addr  =24'h082900;307   :   addr  =24'h082A00;308   :   addr  =24'h082B00;309   :   addr  =24'h082C00;310   :   addr  =24'h082D00;311   :   addr  =24'h082E00;312   :   addr  =24'h082F00;313   :   addr  =24'h083000;314   :   addr  =24'h083100;315   :   addr  =24'h083200;316   :   addr  =24'h083300;317   :   addr  =24'h083400;318   :   addr  =24'h083500;319   :   addr  =24'h083600;320   :   addr  =24'h083700;321   :   addr  =24'h083800;322   :   addr  =24'h083900;323   :   addr  =24'h083A00;324   :   addr  =24'h083B00;325   :   addr  =24'h083C00;326   :   addr  =24'h083D00;327   :   addr  =24'h083E00;328   :   addr  =24'h083F00;329   :   addr  =24'h084000;330   :   addr  =24'h084100;331   :   addr  =24'h084200;332   :   addr  =24'h084300;333   :   addr  =24'h084400;334   :   addr  =24'h084500;335   :   addr  =24'h084600;336   :   addr  =24'h084700;337   :   addr  =24'h084800;338   :   addr  =24'h084900;339   :   addr  =24'h084A00;340   :   addr  =24'h084B00;341   :   addr  =24'h084C00;342   :   addr  =24'h084D00;343   :   addr  =24'h084E00;344   :   addr  =24'h084F00;345   :   addr  =24'h085000;346   :   addr  =24'h085100;347   :   addr  =24'h085200;348   :   addr  =24'h085300;349   :   addr  =24'h085400;350   :   addr  =24'h085500;351   :   addr  =24'h085600;352   :   addr  =24'h085700;353   :   addr  =24'h085800;354   :   addr  =24'h085900;355   :   addr  =24'h085A00;356   :   addr  =24'h085B00;357   :   addr  =24'h085C00;358   :   addr  =24'h085D00;359   :   addr  =24'h085E00;360   :   addr  =24'h085F00;361   :   addr  =24'h086000;362   :   addr  =24'h086100;363   :   addr  =24'h090E00;364   :   addr  =24'h091C04;365   :   addr  =24'h094300;366   :   addr  =24'h094901;367   :   addr  =24'h094A10;368   :   addr  =24'h094E49;369   :   addr  =24'h094F02;370   :   addr  =24'h095E00;371   :   addr  =24'h0A0200;372   :   addr  =24'h0A0303;373   :   addr  =24'h0A0401;374   :   addr  =24'h0A0503;375   :   addr  =24'h0A1400;376   :   addr  =24'h0A1A00;377   :   addr  =24'h0A2000;378   :   addr  =24'h0A2600;379   :   addr  =24'h0A2C00;380   :   addr  =24'h0B440F;381   :   addr  =24'h0B4A1C;382   :   addr  =24'h0B5781;383   :   addr  =24'h0B5800;384   :   addr  =24'h001C01;385   :   addr  =24'h0B24C3;386     :   addr  =24'h0B2502;default       : ;endcase
end
endmodule

以上为si5341的完整逻辑代码，第一次用纯逻辑进行大批量的寄存器配置，随手记录一下。

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