关于jesd204出错

用KC705做jesd204协议的时候报下面的错，该怎么解决呢？

[Place 30-140] Unroutable Placement! A GTXE_COMMON / GTXE_CHANNEL clock component pair is not placed in a routable site pair. The GTXE_COMMON component can use the dedicated path between the GTXE_COMMON and the GTXE_CHANNEL if both are placed in the same clock region. If this sub optimal condition is acceptable for this design, you may use the CLOCK_DEDICATED_ROUTE constraint in the .xdc file to demote this message to a WARNING. However, the use of this override is highly discouraged. These examples can be used directly in the .xdc file to override this clock rule.

< set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets AD9371_wrapper1/AD9371_i/jesd204_phy_0/inst/jesd204_phy_gt_common_i/jesd204_0_common/common0_qpll_clk_in] >

AD9371_wrapper1/AD9371_i/jesd204_phy_0/inst/jesd204_phy_gt_common_i/jesd204_0_common/gtxe2_common_i (GTXE2_COMMON.QPLLOUTCLK) is provisionally placed by clockplacer on GTXE2_COMMON_X0Y3
AD9371_wrapper1/AD9371_i/jesd204_phy_0/inst/jesd204_phy_block_i/AD9371_jesd204_phy_0_0_gt/inst/AD9371_jesd204_phy_0_0_gt_i/gt0_AD9371_jesd204_phy_0_0_gt_i/gtxe2_i (GTXE2_CHANNEL.QPLLCLK) is provisionally placed by clockplacer on GTXE2_CHANNEL_X0Y11
AD9371_wrapper1/AD9371_i/jesd204_phy_0/inst/jesd204_phy_block_i/AD9371_jesd204_phy_0_0_gt/inst/AD9371_jesd204_phy_0_0_gt_i/gt1_AD9371_jesd204_phy_0_0_gt_i/gtxe2_i (GTXE2_CHANNEL.QPLLCLK) is locked to GTXE2_CHANNEL_X0Y12
AD9371_wrapper1/AD9371_i/jesd204_phy_0/inst/jesd204_phy_block_i/AD9371_jesd204_phy_0_0_gt/inst/AD9371_jesd204_phy_0_0_gt_i/gt2_AD9371_jesd204_phy_0_0_gt_i/gtxe2_i (GTXE2_CHANNEL.QPLLCLK) is locked to GTXE2_CHANNEL_X0Y15
AD9371_wrapper1/AD9371_i/jesd204_phy_0/inst/jesd204_phy_block_i/AD9371_jesd204_phy_0_0_gt/inst/AD9371_jesd204_phy_0_0_gt_i/gt3_AD9371_jesd204_phy_0_0_gt_i/gtxe2_i (GTXE2_CHANNEL.QPLLCLK) is provisionally placed by clockplacer on GTXE2_CHANNEL_X0Y10

The above error could possibly be related to other connected instances. Following is a list of
all the related clock rules and their respective instances.

Clock Rule: rule_bufh_bufr_ramb
Status: PASS
Rule Description: Reginal buffers in the same clock region must drive a total number of brams less
than the capacity of the region
AD9371_wrapper1/AD9371_i/jesd204_phy_0/inst/jesd204_phy_block_i/AD9371_jesd204_phy_0_0_gt/inst/AD9371_jesd204_phy_0_0_gt_i/cpll_railing0_i/refclk_buf (BUFH.O) is provisionally placed by clockplacer on BUFHCE_X1Y77

Clock Rule: rule_bufds_bufhce
Status: PASS
Rule Description: A BUFDS driving a BUFH must both be in the same horizontal row (clockregion-wise)
ibufds_refclk0 (IBUFDS_GTE2.O) is locked to IBUFDS_GTE2_X0Y7
AD9371_wrapper1/AD9371_i/jesd204_phy_0/inst/jesd204_phy_block_i/AD9371_jesd204_phy_0_0_gt/inst/AD9371_jesd204_phy_0_0_gt_i/cpll_railing0_i/refclk_buf (BUFH.I) is provisionally placed by clockplacer on BUFHCE_X1Y77
AD9371_wrapper1/AD9371_i/jesd204_phy_1/inst/jesd204_phy_block_i/AD9371_jesd204_phy_1_0_gt/inst/AD9371_jesd204_phy_1_0_gt_i/cpll_railing0_i/refclk_buf (BUFH.I) is provisionally placed by clockplacer on BUFHCE_X1Y78

Clock Rule: rule_bufds_gtxchannel_intelligent_pin
Status: PASS
Rule Description: A BUFDS driving a GTXChannel must both be placed in the same or adjacent clock region
(top/bottom)
ibufds_refclk0 (IBUFDS_GTE2.O) is locked to IBUFDS_GTE2_X0Y7
AD9371_wrapper1/AD9371_i/jesd204_phy_0/inst/jesd204_phy_block_i/AD9371_jesd204_phy_0_0_gt/inst/AD9371_jesd204_phy_0_0_gt_i/gt0_AD9371_jesd204_phy_0_0_gt_i/gtxe2_i (GTXE2_CHANNEL.GTREFCLK0) is provisionally placed by clockplacer on GTXE2_CHANNEL_X0Y11
AD9371_wrapper1/AD9371_i/jesd204_phy_0/inst/jesd204_phy_block_i/AD9371_jesd204_phy_0_0_gt/inst/AD9371_jesd204_phy_0_0_gt_i/gt1_AD9371_jesd204_phy_0_0_gt_i/gtxe2_i (GTXE2_CHANNEL.GTREFCLK0) is locked to GTXE2_CHANNEL_X0Y12
AD9371_wrapper1/AD9371_i/jesd204_phy_0/inst/jesd204_phy_block_i/AD9371_jesd204_phy_0_0_gt/inst/AD9371_jesd204_phy_0_0_gt_i/gt2_AD9371_jesd204_phy_0_0_gt_i/gtxe2_i (GTXE2_CHANNEL.GTREFCLK0) is locked to GTXE2_CHANNEL_X0Y15
AD9371_wrapper1/AD9371_i/jesd204_phy_0/inst/jesd204_phy_block_i/AD9371_jesd204_phy_0_0_gt/inst/AD9371_jesd204_phy_0_0_gt_i/gt3_AD9371_jesd204_phy_0_0_gt_i/gtxe2_i (GTXE2_CHANNEL.GTREFCLK0) is provisionally placed by clockplacer on GTXE2_CHANNEL_X0Y10
AD9371_wrapper1/AD9371_i/jesd204_phy_1/inst/jesd204_phy_block_i/AD9371_jesd204_phy_1_0_gt/inst/AD9371_jesd204_phy_1_0_gt_i/gt1_AD9371_jesd204_phy_1_0_gt_i/gtxe2_i (GTXE2_CHANNEL.GTREFCLK0) is locked to GTXE2_CHANNEL_X0Y14
AD9371_wrapper1/AD9371_i/jesd204_phy_1/inst/jesd204_phy_block_i/AD9371_jesd204_phy_1_0_gt/inst/AD9371_jesd204_phy_1_0_gt_i/gt0_AD9371_jesd204_phy_1_0_gt_i/gtxe2_i (GTXE2_CHANNEL.GTREFCLK0) is locked to GTXE2_CHANNEL_X0Y13

Clock Rule: rule_bufds_gtxcommon_intelligent_pin
Status: PASS
Rule Description: A BUFDS driving a GTXCommon must both be placed in the same or adjacent clock region
(top/bottom)
ibufds_refclk0 (IBUFDS_GTE2.O) is locked to IBUFDS_GTE2_X0Y7

AD9371_wrapper1/AD9371_i/jesd204

解决办法：

卡了好久终于解决，这里只是提供下思路吧，毕竟每个人都不一样

1、我是因为四个时钟共用一个，参考下面链接办法，没有解决，最后将时钟改成一个，问题解决，下面链接说明了具体的原因。

https://forums.xilinx.com/t5/Serial-Transceivers/Place-30-140-Unroutable-Placement-A-GTXE-COMMON-GTXE-CHANNEL/m-p/735730/highlight/true#M1858

2、用专用7系列传输核来做

7系列开发板有专用的传输核，这里给个链接你自己参考去产生，这里支持很多协议的传输，我用的是jesd204。

https://www.xilinx.com/support/documentation/application_notes/xapp1200-k7-xcvr-wiz-example-design.pdf

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