1module SampleLogicRealTime(
 2  input       rst_n,
 3  input       iclk,
 4  input       trig,
 5  output      oclk
 6  );
 7  
 8parameter IDLE        = 2'b01,
 9          SAMPLE      = 2'b10;
10          
11parameter LENGTH      = 9'd300;
12
13reg [1:0] current_state,  //state
14          next_state;
15          
16reg       r_data_in0,     //detect the risingedge reg
17          r_data_in1,
18          o_rising_edge;
19          
20reg [8:0] count;          //count for delay     
21reg       count_rst_n;
22
23// sequential circuit
24always@(posedge iclk, negedge rst_n) begin
25  if (!rst_n) begin
26    current_state <= IDLE;
27  end
28  else begin
29    current_state <= next_state;
30  end
31end
32// combinational circuit for state logic
33always@(current_state,count,o_rising_edge) begin
34  next_state = IDLE;
35  
36  case (current_state)
37    IDLE      : next_state = o_rising_edge          ? SAMPLE    : IDLE;
38    SAMPLE    : next_state = (count >= LENGTH)      ? IDLE      : SAMPLE;
39  endcase
40end
41
42assign oclk = (count_rst_n ==1'b0)?   1'b0  : iclk;
43// combinational circuit for output logic
44always@(current_state,iclk) begin
45  
46  case (current_state)
47  IDLE      : begin 
48                count_rst_n <= 1'b0;
49              end
50  SAMPLE    : begin
51                count_rst_n <= 1'b1;
52              end
53  endcase    
54end
55  
56//detect the rising edge
57always@(posedge iclk) begin
58 r_data_in0 <= r_data_in1;
59 r_data_in1 <= trig;
60end
61always@(r_data_in0,r_data_in1) begin
62  o_rising_edge = ~r_data_in0 & r_data_in1; //o_rising_edge output
63end
64
65//counter
66always@(posedge iclk) begin
67  if(~count_rst_n)
68    count <= 9'b0_0000_0000;
69  else
70    count <= count + 1'b1;
71end
72
73endmodule
74