NEXYS4_DDR迪芝伦XC7A100TCSG324-1型，ADT7420测温
2024-06-21 09:11:41
ADT7420测温
- 0. 未理解的点
- 1. ADT7420简介
- 1.1 特性
- 1.2 引脚配置与原理图
- 1.3 寄存器
- 1.4 读写等操作时序
- 1.4.1 写单字节数据
- 1.4.2 写双字节数据
- 1.4.3 读配置寄存器数据
- 1.4.4 读温度寄存器数据
- 1.5 温度计算
- 2. 系统框图
- 3. 状态转移图
- 4. 时序图
- 4.1 生成i2c_clk信号
- 4.2 i2c_sda 与 i2c_scl 等信号
- 5. 设计文件
- 5.1 i2c_adt7420.v
- 5.2 i2c_adt7420_ctrl.v
- 5.3 seg_dynamic.v
- 5.4 bcd_8421.v
- 6. NEXYS4_DDR迪芝伦XC7A100TCSG324-1型的原理图与管脚绑定
0. 未理解的点
使用下面注释的代码会出现错误
//cnt_bit
always@(posedge i2c_clk or negedge sys_rst_n) if(sys_rst_n == 1'b0)cnt_bit <= 3'd0;else if(state == IDLE || state == START || state == ACK_1 || state == ACK_2 ||state == RE_START || state == ACK_3 || state == MASTER_ACK || state == NO_ACK)cnt_bit <= 3'd0;else if((cnt_bit == 3'd7) && (cnt_i2c_clk == 2'd3))cnt_bit <= 3'd0;else if((cnt_i2c_clk == 2'd3) && (state != IDLE))cnt_bit <= cnt_bit + 1'b1;/* else if(state == STOP && cnt_i2c_clk == 2'd3 && cnt_bit == 3'd3)cnt_bit <= 3'd0;else if((state == SEND_D_ADDR || state == SEND_R_ADDR || state == RSEND_D_ADDR || state == RD_DATA_MSB || state == RD_DATA_LSB|| state == STOP) && cnt_i2c_clk == 2'd3)cnt_bit <= cnt_bit + 1'b1; */
体现在使用 ila 核抓取数据时
写设备地址和寄存器地址都出现了重复写的问题，导致后面状态无法转移
正常状态抓取
1. ADT7420简介
1.1 特性
ADT7420是基于 I2C 协议的16-bit数字温度传感器，精度为0.25摄氏度
其中，scl 的最高时钟频率可达 400kHz；
上电后默认工作在13-bit模式下；第一次快速转换在6ms后完成，精度为5摄氏度，此后240ms完成一次转换
1.2 引脚配置与原理图
原理图中 A1A0 = 11;
文档中有表述：
The five MSBs of this address for the ADT7420 are hardwired internally to 10010. Pin A1 and Pin A0 set the two LSBs.
即 7bit 设备地址为 10010_11
1.3 寄存器
全部的寄存器地址
在读取温度的过程中，主要关注温度高低位寄存器,即 0x00 和 0x01
正常读取的模式下，还需要指针寄存器 (pointer register) 的地址，但是读取完高位 (0x00) 的数据后，指针会自动指向下一个地址，即 0x01
温度寄存器
默认13-bit的情况下，主要关注 reg[15:3]
1.4 读写等操作时序
1.4.1 写单字节数据
1.4.2 写双字节数据
1.4.3 读配置寄存器数据
1.4.4 读温度寄存器数据
1.5 温度计算
符号判断 bits[15] = 0，正数；bits[15] = 1，负数；
数值计算 bits[14:3] * 0.0625
2. 系统框图
3. 状态转移图
定义的状态
4. 时序图
4.1 生成i2c_clk信号
4.2 i2c_sda 与 i2c_scl 等信号
5. 设计文件
5.1 i2c_adt7420.v
module i2c_adt7420
(input wire sys_clk ,input wire sys_rst_n ,inout wire i2c_sda ,output wire i2c_scl ,output wire [7:0] sel ,output wire [7:0] seg
);wire [26:0] rd_data;i2c_adt7420_ctrl
#(.DEVICE_ADDR ( 7'b1001_011 ),.SYS_CLK_FREQ ( 'd100_000_000),.SCL_FREQ ( 'd250_000 )
)
i2c_adt7420_ctrl_inst
(.sys_clk (sys_clk ),.sys_rst_n (sys_rst_n),.i2c_sda (i2c_sda ),.i2c_scl (i2c_scl ),.rd_data (rd_data ));seg_dynamic
#(.CNT_MAX(17'd99_999)
)
seg_dynamic_inst
(.sys_clk (sys_clk ),.sys_rst_n (sys_rst_n),.data (rd_data ),.sel (sel ),.seg (seg )
);endmodule5.2 i2c_adt7420_ctrl.v
module i2c_adt7420_ctrl
#(parameter DEVICE_ADDR = 7'b1001_011 ,parameter SYS_CLK_FREQ = 'd100_000_000,parameter SCL_FREQ = 'd200_000
)
(input wire sys_clk ,input wire sys_rst_n ,inout wire i2c_sda ,output reg i2c_scl ,output reg [26:0] rd_data );parameter CNT_CLK_MAX = (SYS_CLK_FREQ / SCL_FREQ) >> 3;
parameter CNT_DELAY_MAX = 20'd125_000;parameter IDLE = 4'd0,START = 4'd1,SEND_D_ADDR = 4'd2,ACK_1 = 4'd3,SEND_R_ADDR = 4'd4,ACK_2 = 4'd5,RE_START = 4'd6,RSEND_D_ADDR = 4'd7,ACK_3 = 4'd8,RD_DATA_MSB = 4'd9,MASTER_ACK = 4'd10,RD_DATA_LSB = 4'd11,NO_ACK = 4'd12,STOP = 4'd13;reg [19:0] cnt_delay ;
reg i2c_scl_reg ;
reg [7:0] cnt_clk ;
reg i2c_clk ;
reg [3:0] state ;
reg [1:0] cnt_i2c_clk ;
reg cnt_i2c_clk_en ;
reg [3:0] cnt_bit ;
wire sda_in ;
reg sda_out ;
wire sda_en ;
reg [15:0] rd_data_reg ;
reg ack ;//cnt_clk
always@(posedge sys_clk or negedge sys_rst_n) if(sys_rst_n == 1'b0)cnt_clk <= 8'd0;else if(cnt_clk == CNT_CLK_MAX - 1)cnt_clk <= 8'd0;elsecnt_clk <= cnt_clk + 1'b1;
//i2c_clk
always@(posedge sys_clk or negedge sys_rst_n) if(sys_rst_n == 1'b0)i2c_clk <= 1'b1;else if(cnt_clk == CNT_CLK_MAX - 1)i2c_clk <= ~i2c_clk;
//cnt_delay 延时500ms,等待温度转换完成(初始6ms,正常240ms)
always@(posedge i2c_clk or negedge sys_rst_n) if(sys_rst_n == 1'b0)cnt_delay <= 20'd0;else if(cnt_delay == CNT_DELAY_MAX - 1)cnt_delay <= 20'd0;else if(cnt_i2c_clk == 2'd3 && state == IDLE)cnt_delay <= cnt_delay + 1'b1;
//state
always@(posedge i2c_clk or negedge sys_rst_n) if(sys_rst_n == 1'b0)state <= IDLE;else case(state)IDLE ://0if(cnt_delay == CNT_DELAY_MAX - 1)state <= START;elsestate <= state;START ://1if(cnt_i2c_clk == 2'd3)state <= SEND_D_ADDR;elsestate <= state;SEND_D_ADDR ://2if(cnt_i2c_clk == 2'd3 && cnt_bit == 3'd7)state <= ACK_1;elsestate <= state;ACK_1 ://3if(cnt_i2c_clk == 2'd3 && ack == 1'b0)state <= SEND_R_ADDR;elsestate <= state;SEND_R_ADDR ://4if(cnt_i2c_clk == 2'd3 && cnt_bit == 3'd7)state <= ACK_2;elsestate <= state;ACK_2 ://5if(cnt_i2c_clk == 2'd3 && ack == 1'b0)state <= RE_START;elsestate <= state;RE_START :if(cnt_i2c_clk == 2'd3)state <= RSEND_D_ADDR;elsestate <= state;RSEND_D_ADDR :if(cnt_i2c_clk == 2'd3 && cnt_bit == 3'd7)state <= ACK_3;elsestate <= state;ACK_3 :if(cnt_i2c_clk == 2'd3 && ack == 1'b0)state <= RD_DATA_MSB;elsestate <= state;RD_DATA_MSB :if(cnt_i2c_clk == 2'd3 && cnt_bit == 3'd7)state <= MASTER_ACK;elsestate <= state;MASTER_ACK :if(cnt_i2c_clk == 2'd3)state <= RD_DATA_LSB;elsestate <= state;RD_DATA_LSB :if(cnt_i2c_clk == 2'd3 && cnt_bit == 3'd7)state <= NO_ACK;elsestate <= state;NO_ACK :if(cnt_i2c_clk == 2'd3)state <= STOP;elsestate <= state;STOP ://13if(cnt_i2c_clk == 2'd3 && cnt_bit == 3'd3)beginstate <= IDLE;//cnt_bit <= 3'd0;endelsestate <= state;default : state <= IDLE;endcase//cnt_i2c_clk
always@(posedge i2c_clk or negedge sys_rst_n) if(sys_rst_n == 1'b0)cnt_i2c_clk <= 2'd0;//else if(cnt_i2c_clk_en == 1'b1)else if(state == STOP && cnt_i2c_clk == 2'd3 && cnt_bit == 3'd3)cnt_i2c_clk <= 2'd0;elsecnt_i2c_clk <= cnt_i2c_clk + 1'b1;
//cnt_i2c_clk_en
always@(posedge i2c_clk or negedge sys_rst_n) if(sys_rst_n == 1'b0)cnt_i2c_clk_en <= 1'b0;else if(state == STOP && cnt_i2c_clk == 2'd3 && cnt_bit == 3'd3)cnt_i2c_clk_en <= 1'b0;else if(state == IDLE && cnt_i2c_clk == 2'd3)cnt_i2c_clk_en <= 1'b1;
//cnt_bit
always@(posedge i2c_clk or negedge sys_rst_n) if(sys_rst_n == 1'b0)cnt_bit <= 3'd0;else if(state == IDLE || state == START || state == ACK_1 || state == ACK_2 ||state == RE_START || state == ACK_3 || state == MASTER_ACK || state == NO_ACK)cnt_bit <= 3'd0;else if((cnt_bit == 3'd7) && (cnt_i2c_clk == 2'd3))cnt_bit <= 3'd0;else if((cnt_i2c_clk == 2'd3) && (state != IDLE))cnt_bit <= cnt_bit + 1'b1;/* else if(state == STOP && cnt_i2c_clk == 2'd3 && cnt_bit == 3'd3)cnt_bit <= 3'd0;else if((state == SEND_D_ADDR || state == SEND_R_ADDR || state == RSEND_D_ADDR || state == RD_DATA_MSB || state == RD_DATA_LSB|| state == STOP) && cnt_i2c_clk == 2'd3)cnt_bit <= cnt_bit + 1'b1; *///i2c_sda
assign i2c_sda = (sda_en == 1'b1) ? sda_out : 1'bz;
//sda_in
assign sda_in = i2c_sda;
//sda_out
always@(*)case(state)IDLE :sda_out <= 1'b1;START :if(cnt_i2c_clk == 2'd0)sda_out <= 1'b1;elsesda_out <= 1'b0;SEND_D_ADDR :if(cnt_bit == 3'd7)sda_out <= 1'b0;else sda_out <= DEVICE_ADDR[6 - cnt_bit];ACK_1 :sda_out <= 1'b0;SEND_R_ADDR :sda_out <= 1'b0;ACK_2 :sda_out <= 1'b1;RE_START :if(cnt_i2c_clk <= 2'd1)sda_out <= 1'b1;elsesda_out <= 1'b0;RSEND_D_ADDR :if(cnt_bit == 3'd7)sda_out <= 1'b1;else sda_out <= DEVICE_ADDR[6 - cnt_bit];ACK_3 :sda_out <= 1'b1;RD_DATA_MSB :sda_out <= 1'b1;MASTER_ACK :sda_out <= 1'b0;RD_DATA_LSB :sda_out <= 1'b1;NO_ACK :sda_out <= 1'b1;STOP :if(cnt_bit == 3'd0 && cnt_i2c_clk < 2'd3)sda_out <= 1'b0;elsesda_out <= 1'b1;default : sda_out <= 1'b1;endcase
//sda_en
assign sda_en = (state == ACK_1 || state == ACK_2 || state == ACK_3 ||state == RD_DATA_MSB || state == RD_DATA_LSB) ? 1'b0 : 1'b1;//rd_data_reg[15:0]
always@(posedge i2c_clk or negedge sys_rst_n) if(sys_rst_n == 1'b0)rd_data_reg <= 16'd0;else case(state)RD_DATA_MSB :if(cnt_i2c_clk == 2'b1)rd_data_reg[15 - cnt_bit] <= sda_in;elserd_data_reg <= rd_data_reg;RD_DATA_LSB :if(cnt_i2c_clk == 2'b1)rd_data_reg[7 - cnt_bit] <= sda_in;elserd_data_reg <= rd_data_reg;endcase
//rd_data
always@(posedge i2c_clk or negedge sys_rst_n) if(sys_rst_n == 1'b0)rd_data <= 27'd0;else if(state == RD_DATA_LSB && cnt_bit == 3'd7 && cnt_i2c_clk == 2'd3)rd_data <= rd_data_reg[14:3] * 625;
//i2c_scl
always@(posedge i2c_clk or negedge sys_rst_n) if(sys_rst_n == 1'b0)i2c_scl <= 1'b1;else if((cnt_i2c_clk == 2'd2 || cnt_i2c_clk == 2'd3) && (state != STOP)&& (state != IDLE))i2c_scl <= 1'b0;elsei2c_scl <= 1'b1;//ack
always@(*)case(state) ACK_1,ACK_2,ACK_3 :if(cnt_i2c_clk == 2'b0)ack <= sda_in;elseack <= ack;default : ack <= 1'b1;endcaseendmodule
5.3 seg_dynamic.v
module seg_dynamic
#(parameter CNT_MAX = 17'd99_999
)
(input wire sys_clk ,input wire sys_rst_n ,input wire [26:0] data ,output reg [7:0] sel ,output reg [7:0] seg
);wire [3:0] in ;
wire [3:0] ten ;
wire [3:0] hun ;
wire [3:0] tho ;
wire [3:0] ten_tho ;
wire [3:0] hun_tho ;
wire [3:0] mil ;
wire [3:0] must ;reg [3:0] seg_data ;
reg [2:0] cnt_sel ;reg [16:0] cnt_1ms ;
reg flag_1ms ;//cnt_1ms:1ms循环计数
always@(posedge sys_clk or negedge sys_rst_n)if(sys_rst_n == 1'b0)cnt_1ms <= 17'd0;else if(cnt_1ms == CNT_MAX)cnt_1ms <= 17'd0;elsecnt_1ms <= cnt_1ms + 1'b1;//flag_1ms:1ms标志信号
always@(posedge sys_clk or negedge sys_rst_n)if(sys_rst_n == 1'b0)flag_1ms <= 1'b0;else if(cnt_1ms == CNT_MAX - 1'b1)flag_1ms <= 1'b1;elseflag_1ms <= 1'b0;//cnt_sel：从0到7循环数，用于选择当前显示的数码管
always@(posedge sys_clk or negedge sys_rst_n)if(sys_rst_n == 1'b0)cnt_sel <= 3'd0;else if((cnt_sel == 3'd7) && (flag_1ms == 1'b1))cnt_sel <= 3'd0;else if(flag_1ms == 1'b1)cnt_sel <= cnt_sel + 1'b1;elsecnt_sel <= cnt_sel;always@(posedge sys_clk or negedge sys_rst_n)if(sys_rst_n == 1'b0)seg_data <= 8'b0000_0011;elsebegincase(cnt_sel)3'd0: seg_data <= in ;3'd1: seg_data <= ten ;3'd2: seg_data <= hun ;3'd3: seg_data <= tho ;3'd4: seg_data <= ten_tho;3'd5: seg_data <= hun_tho;3'd6: seg_data <= mil ;3'd7: seg_data <= must ;endcaseendalways@(posedge sys_clk or negedge sys_rst_n)if(sys_rst_n == 1'b0)sel <= 8'b0111_1111;else if(flag_1ms == 1'b1)begincase(cnt_sel)3'd0: sel <= 8'b0111_1110;3'd1: sel <= 8'b1111_1101;3'd2: sel <= 8'b1111_1011;3'd3: sel <= 8'b1111_0111;3'd4: sel <= 8'b1110_1111;3'd5: sel <= 8'b1101_1111;3'd6: sel <= 8'b1011_1111;3'd7: sel <= 8'b0111_1111;endcaseendalways@(posedge sys_clk or negedge sys_rst_n)if(sys_rst_n == 1'b0)seg <= 8'b0000_0011;else if(flag_1ms == 1'b1)begincase(seg_data)4'd0: seg <= 8'b0000_0011;4'd1: seg <= 8'b1001_1111;4'd2: seg <= 8'b0010_0101;4'd3: seg <= 8'b0000_1101;4'd4: seg <= 8'b1001_1001;4'd5: seg <= 8'b0100_1001;4'd6: seg <= 8'b0100_0001;4'd7: seg <= 8'b0001_1111;4'd8: seg <= 8'b0000_0001;4'd9: seg <= 8'b0000_1001;endcaseendelseseg <= seg;bcd_8421 bcd_8421_inst
(.sys_clk (sys_clk ),.sys_rst_n (sys_rst_n),.data (data ),.in (in ), //个.ten (ten ), //十.hun (hun ), //百.tho (tho ), //千.ten_tho (ten_tho ), //万.hun_tho (hun_tho ), //十万.mil (mil ), //百万.must (must ) //千万
);endmodule
5.4 bcd_8421.v
module bcd_8421
(input wire sys_clk ,input wire sys_rst_n ,input wire [26:0] data ,output reg [3:0] in , //个output reg [3:0] ten , //十output reg [3:0] hun , //百output reg [3:0] tho , //千output reg [3:0] ten_tho , //万output reg [3:0] hun_tho , //十万output reg [3:0] mil , //百万output reg [3:0] must //千万);reg [4:0] cnt_shift ;
reg [58:0] data_shift ;
reg shift_flag ;always@(posedge sys_clk or negedge sys_rst_n)if(sys_rst_n == 1'b0)cnt_shift <= 5'd0;else if((cnt_shift == 5'd28) && (shift_flag == 1'b1))cnt_shift <= 5'd0;else if(shift_flag == 1'b1)cnt_shift <= cnt_shift + 1'b1;elsecnt_shift <= cnt_shift;always@(posedge sys_clk or negedge sys_rst_n)if(sys_rst_n == 1'b0)data_shift <= 59'd0;else if(cnt_shift == 5'd0)data_shift <= {32'b0,data};else if((cnt_shift <= 5'd27) && (shift_flag == 1'b0))begindata_shift[30:27] <= (data_shift[30:27] > 4) ? (data_shift[30:27] + 2'd3) : (data_shift[30:27]);data_shift[34:31] <= (data_shift[34:31] > 4) ? (data_shift[34:31] + 2'd3) : (data_shift[34:31]);data_shift[38:35] <= (data_shift[38:35] > 4) ? (data_shift[38:35] + 2'd3) : (data_shift[38:35]);data_shift[42:39] <= (data_shift[42:39] > 4) ? (data_shift[42:39] + 2'd3) : (data_shift[42:39]);data_shift[46:43] <= (data_shift[46:43] > 4) ? (data_shift[46:43] + 2'd3) : (data_shift[46:43]);data_shift[50:47] <= (data_shift[50:47] > 4) ? (data_shift[50:47] + 2'd3) : (data_shift[50:47]);data_shift[54:51] <= (data_shift[54:51] > 4) ? (data_shift[54:51] + 2'd3) : (data_shift[54:51]);data_shift[58:55] <= (data_shift[58:55] > 4) ? (data_shift[58:55] + 2'd3) : (data_shift[58:55]);endelse if((cnt_shift <= 5'd27) && (shift_flag == 1'b1)) data_shift <= data_shift << 1;elsedata_shift <= data_shift;always@(posedge sys_clk or negedge sys_rst_n)if(sys_rst_n == 1'b0)shift_flag <= 1'b0;elseshift_flag <= ~shift_flag;always@(posedge sys_clk or negedge sys_rst_n)if(sys_rst_n == 1'b0)beginin <= 4'b0;ten <= 4'b0;hun <= 4'b0;tho <= 4'b0;ten_tho <= 4'b0;hun_tho <= 4'b0;mil <= 4'b0;must <= 4'b0;endelse if(cnt_shift == 5'd28)beginin <= data_shift[30:27];ten <= data_shift[34:31];hun <= data_shift[38:35];tho <= data_shift[42:39];ten_tho <= data_shift[46:43];hun_tho <= data_shift[50:47];mil <= data_shift[54:51];must <= data_shift[58:55];endendmodule
6. NEXYS4_DDR迪芝伦XC7A100TCSG324-1型的原理图与管脚绑定
此处的管脚只使用到 scl 与 sda
set_property IOSTANDARD LVCMOS33 [get_ports i2c_scl]
set_property IOSTANDARD LVCMOS33 [get_ports i2c_sda]
set_property PACKAGE_PIN C14 [get_ports i2c_scl]
set_property PACKAGE_PIN C15 [get_ports i2c_sda]set_property IOSTANDARD LVCMOS33 [get_ports sys_clk]
set_property IOSTANDARD LVCMOS33 [get_ports sys_rst_n]set_property IOSTANDARD LVCMOS33 [get_ports {seg[7]}]
set_property IOSTANDARD LVCMOS33 [get_ports {seg[6]}]
set_property IOSTANDARD LVCMOS33 [get_ports {seg[5]}]
set_property IOSTANDARD LVCMOS33 [get_ports {seg[4]}]
set_property IOSTANDARD LVCMOS33 [get_ports {seg[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {seg[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {seg[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {seg[0]}]set_property IOSTANDARD LVCMOS33 [get_ports {sel[7]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sel[6]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sel[5]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sel[4]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sel[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sel[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sel[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {sel[0]}]set_property PACKAGE_PIN E3 [get_ports sys_clk]
set_property PACKAGE_PIN J15 [get_ports sys_rst_n]set_property PACKAGE_PIN J17 [get_ports {sel[0]}]
set_property PACKAGE_PIN J18 [get_ports {sel[1]}]
set_property PACKAGE_PIN T9 [get_ports {sel[2]}]
set_property PACKAGE_PIN J14 [get_ports {sel[3]}]
set_property PACKAGE_PIN P14 [get_ports {sel[4]}]
set_property PACKAGE_PIN T14 [get_ports {sel[5]}]
set_property PACKAGE_PIN K2 [get_ports {sel[6]}]
set_property PACKAGE_PIN U13 [get_ports {sel[7]}]set_property PACKAGE_PIN H15 [get_ports {seg[0]}]
set_property PACKAGE_PIN L18 [get_ports {seg[1]}]
set_property PACKAGE_PIN T11 [get_ports {seg[2]}]
set_property PACKAGE_PIN P15 [get_ports {seg[3]}]
set_property PACKAGE_PIN K13 [get_ports {seg[4]}]
set_property PACKAGE_PIN K16 [get_ports {seg[5]}]
set_property PACKAGE_PIN R10 [get_ports {seg[6]}]
set_property PACKAGE_PIN T10 [get_ports {seg[7]}]NEXYS4_DDR迪芝伦XC7A100TCSG324-1型，ADT7420测温相关推荐
- NEXYS4_DDR迪芝伦XC7A100TCSG324-1型，VGA接口显示彩条
vga彩条显示,640*480模式可以显示1600*900 1. VGA显示 1.1 VGA的端口定义 1.2 VGA的显示时序 1.3 像素点与时序 1.4 此处选择DELL_E2016HV型显示器 ...
- NEXYS4_DDR迪芝伦XC7A100TCSG324-1型，点亮板载的8个8位数码管
简化版动态点亮 1. vivado文件编写,根据模块设计图 1.1 点亮数码管之前首先产生一个100ms自增长的数据data[26:0] 1.1.1 时序图 1.1.2 data_gen.v 文件 1 ...
- 基于op07的k型热电偶测量电路_k型热电偶测温电路图解析
K型热电偶是一种温度传感器,K型热电偶通常和显示仪表,记录仪表和电子调节器配套使用.K型热电偶通常由感温元件.安装固定装置和接线盒等主要部件组成. k型热电偶 K型热电偶作为一种温度传感器,K型热电偶 ...
- 基于STM32单片机的K型热电偶测温（Proteus仿真+程序）
编号:17 基于STM32单片机的K型热电偶测温 功能描述: 本设计由STM32单片机+MAX7765+TCK热电偶+1602液晶显示模块组成. 1.主控制器是STM32单片机 2.TCK热电偶测温通 ...
- 基于MAX6675的k型热电偶测温系统
基于MAX6675的k型热电偶测温系统 亲测 本人亲测代码有效 测温整数误差控制在0摄氏度 如果所显示和实际误差相差25摄氏度 请在仿真中点击MAX6675属性调节把环境温度改为0 即k型热电偶冷端温 ...
- 【Proteus仿真】【51单片机】K型热电偶测温系统设计
文章目录 一.功能简介 二.软件设计 三.实验现象 联系作者 一.功能简介 本项目使用Proteus8仿真51单片机控制器,使用LCD1602显示模块.按键模块.蜂鸣器.MAX6675.K型热电偶传感 ...
- 基于op07的k型热电偶测量电路_基于K型热电偶的测温装置设计
基于 K 型热电偶的测温装置设计 * 王安敏 孔令布 孟海彦 [摘 要] 摘 要 工业现场的温度检测大多以 K 型热电偶为传感器测量高温,针 对热电偶测量温度存在线性度差,测量误差大等问题.现采用 K ...
- 自己做量化交易软件(35)小白量化实战8--事件型回测程序
自己做量化交易软件(35)小白量化实战8–事件型回测程序 小白量化第二代程序也提供了一个简单的事件型回测程序,我们前面的博客文章有介绍这方面的知识.当时用MT5 做的回测演示,见文章:自己做量化交易软 ...
- 一种基于STM32F1 MCU的增量型编码器测速的方法
遇到的问题 1. 编码器信号,用来计量长度,如果需要同时测量当前实时速度,在不增加接口的情况下,实现较为准确实时的测速 2. 简单的M法速度,对于低速信号,测量精度较差,实时性也不高. 测速方法 之前 ...
最新文章
- 谷歌最新薪资曝光：研究岗年薪最高达200多万，但远逊于人事主管
- ajax无刷新页面切换,历史记录后退前进解决方案
- 1024到了，默默给自己点个赞！
- centos系统linux复制命令行,linux系统CentOS7中find命令使用
- JavaScript：画廊案例
- 根据前序和中序构造整个二叉树
- 1.PHP数据库陷阱
- vue3实现商城左右联动数据---BScroll（vue3代码复制就能用）
- web端文字转语音播放的几种方式
- 电脑端思维导图软件推荐
- 如何用SPSS对数据进行标准化处理？
- 如何书写论文中的参考文献并正确标注页码
- 内网渗透篇-信息收集
- Python：for...in range() 、 for...in enumerate() 、for...in() 、for...in zip()的用法
- 【对比Java学Kotlin】协程-创建和取消
- moses gcc link failed
- （转）（异常分析） org.hibernate.MappingException: entity class not found
- 教你如何使用Python破解WIFI密码
- PS 复位/反选功能/抠图功能
- javaScript 实现表格table分页