TI 280049 FLASH 翻译

2.1 TI 280049 FLASH
3.12 Flash 和 OTP 存储器
闪存是一种电可擦除/可编程非易失性存储器，可以多次编程和擦除以简化代码开发。闪存主要用作内核的程序存储器，其次用作静态数据存储器。
本节介绍配置闪存等待状态和操作模式的正确顺序。它还包括有关闪存和 OTP 电源模式、如何通过启用闪存预取/缓存模式来提高闪存性能以及 SECDED 安全功能的信息。

3.12 Flash and OTP Memory
Flash is an electrically erasable/programmable nonvolatile memory that can be programmed and erased many times to ease code development. Flash memory can be used primarily as a program memory for the core, and secondarily as static data memory.
This section describes the proper sequence to configure the wait states and operating mode of flash. It also includes information on flash and OTP power modes, how to improve flash performance by enabling the flash prefetch/cache mode, and the SECDED safety feature.

2.1.1 3.12.1 Features

3.12.1 特点
闪存的特点包括：
• 最多两个闪存库（Bank0 和 Bank1）（有关闪存库的数量和大小，请参阅您的设备特定数据手册）
• 一个 FMC 控制最多两个 Flash bank
• 可以与 ECC 一起编程 128 位（组宽度）
• 多个扇区提供将某些扇区编程并仅擦除特定扇区的选项
• 用户可编程 OTP 位置（在用户可配置 DCSM OTP 中，也称为 USER OTP）用于配置
安全性、OTP 引导模式和引导模式选择引脚（如果您无法使用出厂默认引导模式选择引脚）
• 两个bank行共享的闪存的通道
• 使用 FMC 中的代码预取机制和数据缓存增强性能
• 可配置的等待状态，为给定的执行速度提供最佳性能
• 安全特性：
– FMC 中支持 SECDED 单错误纠正和双错误检测
– 地址位包含在 ECC 中
– 用于检查 ECC 逻辑健康状况的测试模式
• 支持闪存组和泵的低功耗模式以实现节能
• 内置功率模式控制逻辑
• FMC 中的集成闪存编程/擦除状态机 (FSM)
– 简单的 Flash API 算法
– 快速擦除和编程时间（有关详细信息，请参阅特定于设备的数据手册）
• 双代码安全模块 (DCSM) 可防止未经授权的人员访问闪存（详情请参阅第 3.13 节）

3.12.1 Features
Features of Flash memory include:
• Up to two Flash banks (Bank0 and Bank1) (refer to your device-specific data manual for the number and size of the Flash banks)
• One FMC controlling up to two Flash banks
• 128 bits (bank width) can be programmed at a time along with ECC
• Multiple sectors providing the option of leaving some sectors programmed and only erasing specific sectors
• User-programmable OTP locations (in user-configurable DCSM OTP, also called USER OTP) for configuring
security, OTP boot-mode and boot-mode select pins (if you are unable to use the factory-default boot-mode select pins)
• Flash pump shared by the two banks
• Enhanced performance using the code-prefetch mechanism and data cache in FMC
• Configurable wait states to give the best performance for a given execution speed
• Safety Features:
– SECDED-single error correction and double error detection is supported in the FMC
– Address bits are included in ECC
– Test mode to check the health of ECC logic
• Supports low-power modes for Flash bank and pump for power savings
• Built-in power mode control logic
• Integrated Flash program/erase state machine (FSM) in the FMC
– Simple Flash API algorithms
– Fast erase and program times (refer to your device-specific data manual for details)
• Dual Code Security Module (DCSM) to prevent access to the flash by unauthorized persons (refer to Section 3.13 for details)

2.1.2 3.12.3 Default Flash Configuration

3.12.3 默认闪存配置
以下是上电时的 Flash 模块配置设置：
• 闪存组处于睡眠电源模式（FBFALLBAC 寄存器中的 BNKPWR 位域）
• 共享泵处于睡眠电源模式（FPAC1 寄存器中的 PMPPWR 位域）
• ECC 已启用
• 等待状态设置为最大值 (0xF)
• 在 FMC 中禁用代码预取机制和数据缓存
• 组和泵活动宽限期设置为 0x0（参见 FBAC 寄存器中的 BAGP 字段和 FPAC2 寄存器中的 PAGP 位字段）
请注意，引导 ROM 会将 BNKPWR 和 PMPPWR 位字段更改为活动模式。
用户应用软件必须使用 FRDCNTL 寄存器初始化等待状态，并配置缓存/预取
功能使用 FRD_INTF_CTRL 寄存器，以实现最佳系统性能。配置闪存设置（如等待状态、缓存/预取功能等）的软件必须仅从 RAM 内存中执行，而不能从闪存中执行。
笔记
在初始化等待状态之前，关闭 FRD_INTF_CTRL 寄存器中的预取和数据缓存。

3.12.3 Default Flash Configuration
The following are Flash module configuration settings at power-up:
• Flash banks are in sleep power mode (BNKPWR bit field in the FBFALLBAC register)
• Shared pump is in sleep power mode (PMPPWR bit field in the FPAC1 register)
• ECC is enabled
• Wait-states are set to the maximum (0xF)
• Code-prefetch mechanism and data cache are disabled in the FMC
• Bank and pump active grace periods are set to 0x0 (refer to the BAGP field in the FBAC register and PAGP bit field in the FPAC2 register)
Note that boot ROM changes the BNKPWR and PMPPWR bit fields to active mode.
User application software must initialize wait-states using the FRDCNTL register, and configure cache/prefetch
features using the FRD_INTF_CTRL register, to achieve optimum system performance. Software that configures Flash settings like wait-states, cache/prefetch features, and so on, must be executed only from RAM memory,not from Flash memory.
Note
Before initializing wait-states, turn off the pre-fetch and data caching in the FRD_INTF_CTRL register.

2.1.3 3.12.4 Flash Bank, OTP and Pump

有两个闪存库，Bank0 和 Bank1（有关可用库的数量，请参阅器件数据手册）。此外，还有一种称为 USER OTP 的一次性可编程 (OTP) 存储器，用户只能对其进行一次编程且无法擦除。 Flash 和 OTP 统一映射在程序和数据存储空间中。
还有一个 TI-OTP，其中包含制造信息，例如闪存状态机用于擦除和编程操作的设置等。用户可以读取 TI-OTP，但不能对其进行编程或擦除。
有关bank、TI-OTP、USER OTP以及相应ECC位置的内存映射和大小信息，请参阅器件数据手册。
Bank0 和 Bank1 共用一个闪蒸泵；因此，一次只能对一个组进行编程或擦除。支持从一个 bank 执行或读取，而另一 bank 正在进行擦除或编程。
图 3-19 描述了 USER-OTP 中用户可编程的 OTP 位置。有关这些字段功能的更多信息，请参阅第 3.13 节和 ROM 代码和外设引导一章。

There are two flash banks, Bank0 and Bank1 (refer to the device data manual for the number of banks available). Also, there is a one-time programmable (OTP) memory called USER OTP, which the user can program only once and cannot erase. Flash and OTP are uniformly mapped in both program and data memory space.
There is also a TI-OTP which contains manufacturing information like settings used by the flash state machine for erase and program operations, and so on. Users may read TI-OTP but it cannot be programmed or erased.
For memory map and size information of the banks, TI-OTP, USER OTP, and corresponding ECC locations,please refer to the device data manual.
Bank0 and Bank1 share a common flash pump; therefore, only one bank can be programmed or erased at a time. Execution or reads from one bank, while erase or program is in progress on the other bank, is supported.
Figure 3-19 depicts the user-programmable OTP locations in USER-OTP . For more information on the functionality of these fields, refer to Section 3.13 and the ROM Code and Peripheral Booting chapter.

2.1.4 3.12.5 闪存模块控制器（FMC）

单个 FMC 控制 Bank0 和 Bank1，见图 3-15。 CPU 与 FMC 接口，FMC 又与 Bank0 和 Bank1 以及共享泵接口，以执行擦除或编程操作，读取数据，并从这些 Flash bank 执行代码。
FMC 中有一个状态机，可以在硬件中生成擦除/编程序列。这简化了在 FMC 中配置控制寄存器以执行闪存擦除和编程操作的闪存 API 软件。
有关 Flash API 的详细信息，请参阅 TMS320F28004x Flash API 参考指南以获取更多信息。
第 3.12.6 节到第 3.12.10 节详细描述了 FMC。

3.12.5 Flash Module Controller (FMC)
A single FMC controls both Bank0 and Bank1, see Figure 3-15. The CPU interfaces with the FMC, which in turn interfaces with Bank0 and Bank1 and the shared pump, to perform erase or program operations, to read data,and execute code from these Flash banks.
There is a state machine in FMC that generates the erase/program sequences in hardware. This simplifies the Flash API software that configures control registers in the FMC to perform Flash erase and program operations.
Refer to the TMS320F28004x Flash API Reference Guide for more information for details on Flash API.
Section 3.12.6 through Section 3.12.10 describe FMC in detail.

2.1.5 3.12.6 Flash 和 OTP 以及唤醒掉电模式

闪存组和泵在活动时会消耗大量电量。闪存模块提供了一种关闭闪存库和泵的机制。特殊定时器自动对 Bank0 和 Bank1 的上电和断电顺序进行独立排序。共享电荷泵模块也有自己独立的上电和断电定时器。

3.12.6 Flash and OTP and Wakeup Power-Down Modes
The flash banks and pump consume a significant amount of power when active. The flash module provides a mechanism to power-down flash banks and pump. Special timers automatically sequence the power-up and power-down of Bank0 and Bank1 independently of each other. The shared charge pump module has its own independent power-up and power-down timers as well.

3.12.6.1 Flash/OTP 和泵功率模式和唤醒

闪存组和 OTP 在三种电源模式下运行：
• 睡眠状态（最低功耗）
这是设备复位后的状态。在这种状态下，CPU 数据读取或操作码获取将自动启动电源模式到待机状态然后到活动状态的更改。在转换到活动状态的这段时间内，CPU 将自动停止。
• 待机状态
此状态比睡眠状态使用更多的功率，但转换到活动或读取状态所需的时间更短。在这种状态下，CPU 数据读取或操作码获取将自动启动电源模式到活动状态的更改。在转换到活动状态的这段时间内，CPU 将自动停止。一旦闪存/OTP 达到活动状态，CPU 访问将正常完成。
• 活动状态（最高功率）
在此状态下，组和泵处于有功功率模式状态。
电荷泵在两种功率模式下运行：
• 睡眠（最低功耗）
• 有源（最高功率）

如果电荷泵处于睡眠模式，则对任何闪存组/OTP 的任何访问都会导致电荷泵进入活动模式。此外，任何擦除或编程命令都会导致电荷泵和存储体变为活动状态。如果任何 bank 处于活动状态或处于待机模式，电荷泵将处于活动模式，独立于电荷泵功率模式控制。
配置（参见 FPAC1 寄存器中的 PMPPWR 位域）。当泵处于休眠状态时，电荷泵休眠计数器保存一个用户可配置的值（FPAC1 寄存器中的 PSLEEP 位域），当电荷泵退出休眠电源模式时，向下计数器从 0 延迟到 PSLEEP 预分频的 SYSCLK 时钟周期（预分频时钟为 SYSCLK/2），然后再将电荷泵置于有源功率模式。请注意，配置的 PPSLEEP 值应至少产生 20 μs 的延迟，以使泵进入活动模式。有关详细信息，请参阅第 3.14 节。
以下是bank和泵从低功耗模式唤醒所需的周期数。

将睡眠泵送至活动状态 = PSLEEP * (SYSCLK/2) 周期
Bank 休眠到待机 = 254 Flash 时钟周期
Bank 待机到活动 = 55 Flash 时钟周期
其中 Flash 时钟 = SYSCLK/(RWAIT+1)

3.12.6.1 Flash/OTP and Pump Power Modes and Wakeup
The flash banks and OTP operate in three power modes:
• Sleep State (lowest power)
This is the state after a device reset. In this state, a CPU data read or opcode fetch will automatically initiate a change in power mode to the standby state and then to the active state. During this transition time to the active state, the CPU will automatically be stalled.
• Standby State
This state uses more power than the sleep state, but takes a shorter time to transition to the active or read state. In this state, a CPU data read or opcode fetch will automatically initiate a change in power mode to the active state. During this transition time to the active state, the CPU will automatically be stalled. Once the flash/OTP has reached the active state, the CPU access will complete as normal.
• Active State (highest power)
In this state, the bank and pump are in active power mode state.
The charge pump operates in two power modes:
• Sleep (lowest power)
• Active (highest power)
Any access to any flash bank/OTP causes the charge pump to go into active mode, if it is in sleep mode. Also,any erase or program command causes the charge pump and bank to become active. If any bank is active or in standby mode, the charge pump will be in active mode, independent of the charge pump power mode control
configuration (refer to the PMPPWR bit field in the FPAC1 register). While the pump is in sleep state, a charge pump sleep down counter holds a user-configurable value (PSLEEP bit field in the FPAC1 register) and when the charge pump exits sleep power mode, the down counter delays from 0 to PSLEEP prescaled SYSCLK clock cycles (prescaled clock is SYSCLK/2) before putting the charge pump into active power mode. Note that the configured PPSLEEP value should yield at least a delay of 20 μs for the pump to go to active mode. Refer to Section 3.14 for detailed information.
Following are the number of cycles it takes for the bank and pump to wake up from low-power modes.

Pump sleep to active = PSLEEP * (SYSCLK/2) cycles
Bank sleep to standby = 254 Flash clock cycles
Bank standby to active = 55 Flash clock cycles
Where in Flash clock = SYSCLK/(RWAIT+1)

2.1.6 3.12.8 Flash 访问接口
本节提供有关访问闪存/OTP 和控制读取接口的配置寄存器的模式的详细信息。除了标准读取模式外，FMC 还具有内置预取和缓存机制，可在适用的情况下提高时钟速度和 CPU 吞吐量。

3.12.8 Flash Access Interface
This section provides details about the modes to access flash/OTP and the configuration registers which control the read interface. In addition to a standard read mode, the FMC has a built-in prefetch and cache mechanism to allow increased clock speeds and CPU throughput wherever applicable.

3.12.8.1 标准接入方式
标准访问模式定义为禁用代码预取机制和数据缓存时有效的访问模式。也是复位后的默认模式。在此模式下，对闪存的每次访问都由闪存包装器解码，以从寻址位置读取/获取数据/代码，并在 RWAIT+1 个周期后返回数据/代码。
与预取机制和数据缓存相关的预取缓冲区在标准访问模式下被绕过；因此，每次访问 flash/OTP 都会立即被 CPU 使用，并且每次访问都会创建一个唯一的 flash bank 访问。
标准访问模式是较低系统频率操作的推荐模式，其中 RWAIT 可以设置为零以提供单周期访问操作。 FMC 可以使用标准访问模式以更高的频率运行，但会增加等待状态。在较高的系统频率下，建议启用缓存和预取机制以提高性能。参考设备特定的数据手册来确定标准访问模式下允许的最大闪存频率（即 RWAIT=0 时的最大闪存时钟频率，FCLKmax）。

3.12.8.1 Standard Access Mode
Standard access mode is defined as the access mode in effect when the code prefetch-mechanism and data cache are disabled. It is also the default mode after reset. During this mode, each access to flash is decoded by the flash wrapper to read/fetch the data/code from the addressed location and the data/code is returned after the RWAIT+1 number of cycles.
The prefetch buffer associated with the prefetch mechanism and data cache is bypassed in standard access mode; therefore, every access to the flash/OTP is used by the CPU immediately, and every access creates a unique flash bank access.
Standard access mode is the recommended mode for lower system frequency operation in which RWAIT can be set to zero to provide single-cycle access operation. The FMC can operate at higher frequencies using standard access mode at the expense of adding wait states. At higher system frequencies, it is recommended to enable cache and prefetch mechanisms to improve performance. Refer to the device-specific data manual to determine the maximum flash frequency allowed in standard access mode (that is, maximum flash clock frequency with RWAIT=0, FCLKmax).

3.12.8.2 预取模式
闪存通常用于存储应用程序代码。在代码执行期间，指令从连续的存储器地址中获取，除非发生不连续性。通常，驻留在顺序地址中的代码部分构成了应用程序代码的大部分，被称为线性代码。为了提高线性代码执行的性能，FMC 中实施了闪存预取机制。图 3-16 说明了此模式的功能。
这种预取机制对从最后一条指令取指的地址开始的线性地址增量进行前瞻预取。默认情况下禁用闪存预取机制。设置 FRD_INTF_CTRL 寄存器中的 PREFETCH_EN 位可启用此预取模式。
从闪存或 OTP 中提取的指令每次访问读取 128 位。从闪存访问的起始地址自动对齐到 128 位边界，以便指令位置在要获取的 128 位内。启用闪存预取模式后，从指令提取中读取的 128 位存储在 128 位宽、2 级深的指令预取缓冲区中。然后，该预取缓冲区的内容会根据需要发送到 CPU 进行处理。
最多四个 32 位或八个 16 位指令可以驻留在单个 128 位访问中。大多数 C28x 指令是 16 位，因此对于从闪存库中每提取 128 位指令，预取缓冲区中可能有多达 8 条指令准备通过 CPU 进行处理。在处理这些指令期间，闪存预取机制会自动启动对闪存库的另一次访问，以预取接下来的 128 位。通过这种方式，闪存预取机制在后台工作，以保持指令预取缓冲区尽可能满。使用这种技术，从闪存或 OTP 顺序执行代码的整体效率得到显着提高。

笔记
如果启用了预取机制，则不应使用在其边界之外没有有效地址的 bank 的最后两行（16 个 16 位字，即 256 位），因为执行先行预取的预取逻辑将尝试从存储体外部取数据并导致 ECC 错误。
Flash 预取仅在由执行诸如分支、BANZ、调用或循环等指令引起的 PC 中断时中止。发生这种情况时，预取机制将中止并刷新预取缓冲区的内容。发生这种情况时有两种可能的情况：

如果目标地址在闪存或 OTP 内，预取将中止，然后在目标地址处恢复。
如果目标地址在闪存和 OTP 之外，则预取将中止并仅在分支返回闪存或 OTP 时重新开始。 Flash 预取机制仅适用于从程序空间取指令。从数据存储器和程序存储器读取的数据不利用预取缓冲器功能，因此绕过预取缓冲器。例如，MAC、DMAC 和 PREAD 等指令从程序存储器读取数据值。发生此读取时，会绕过预取缓冲区，但不会刷新缓冲区。如果在启动数据读取操作时已经在进行指令预取，则数据读取将被暂停，直到预取完成。
请注意，当 RWAIT 配置为零时，预取机制将被绕过。

3.12.8.2 Prefetch Mode
Flash memory is typically used to store application code. During code execution, instructions are fetched from sequential memory addresses, except when a discontinuity occurs. Usually the portion of the code that resides in sequential addresses makes up the majority of the application code and is referred to as linear code. To improve the performance of linear code execution, a flash prefetch-mechanism has been implemented in the FMC. Figure 3-16 illustrates how this mode functions.
This prefetch mechanism does a look-ahead prefetch on linear address increments starting from the address of the last instruction fetch. The flash prefetch mechanism is disabled by default. Setting the PREFETCH_EN bit in the FRD_INTF_CTRL register enables this prefetch mode.
An instruction fetch from the flash or OTP reads out 128 bits per access. The starting address of the access from flash is automatically aligned to a 128-bit boundary, such that the instruction location is within the 128 bits to be fetched. With the flash prefetch mode enabled, the 128 bits read from the instruction fetch are stored in a 128-bit wide by 2-level deep instruction prefetch buffer. The contents of this prefetch buffer are then sent to the CPU for processing as required.
Up to four 32-bit or eight 16-bit instructions can reside within a single 128-bit access. The majority of C28x instructions are 16 bits, so for every 128-bit instruction fetch from the flash bank, it is likely that there are up to eight instructions in the prefetch buffer ready to process through the CPU. During the time it takes to process these instructions, the flash prefetch mechanism automatically initiates another access to the flash bank to prefetch the next 128 bits. In this manner, the flash prefetch mechanism works in the background to keep the instruction prefetch buffers as full as possible. Using this technique, the overall efficiency of sequential code execution from flash or OTP is improved significantly.

Note
If the prefetch mechanism is enabled, then the last two rows (16 16-bit words, that is, 256 bits) of the bank that does not have a valid address beyond its boundary should not be used, because the
prefetch logic that does a look-ahead prefetch, will try to fetch from outside the bank and would result in an ECC error.
The flash prefetch is aborted only on a PC discontinuity caused by executing an instruction such as a branch,BANZ, call, or loop. When this occurs, the prefetch mechanism is aborted and the contents of the prefetch buffer are flushed. There are two possible scenarios when this occurs:

If the destination address is within the flash or OTP, the prefetch aborts and then resumes at the destination address.
If the destination address is outside of the flash and OTP, the prefetch is aborted and begins again only when a branch is made back into the flash or OTP. The flash prefetch mechanism only applies to instruction fetches from program space. Data reads from data memory and from program memory do not utilize the prefetch buffer capability and thus bypass the prefetch buffer. For example, instructions such as MAC, DMAC, and PREAD read a data value from program memory. When this read happens, the prefetch buffer is bypassed but the buffer is not flushed. If an instruction prefetch is already in progress when a data read operation is initiated, then the data read will be stalled until the prefetch completes.
Note that the prefetch mechanism gets bypassed when RWAIT is configured as zero.

3.12.8.3 数据缓存
除了预取机制外，还实现了 128 位宽的数据缓存，以提高数据空间读取和程序空间读取性能。该数据缓存不会被预取机制填充。当 CPU 从 bank 中的某个地址进行任何类型的数据空间读取或程序空间读取时，如果所请求地址对应的数据不在数据缓存中，则将从中读取 128 位数据bank 并加载到数据缓存中。这些数据最终会被发送到 CPU 进行处理。从闪存访问的起始地址自动对齐到 128 位边界，以便请求的地址位置在要从存储体读取的 128 位内。默认情况下，该数据缓存被禁用，可以通过设置 FRD_INTF_CTRL 寄存器中的 DATA_CACHE_EN 位来启用。请注意，当 RWAIT 配置为零时，数据缓存将被绕过。
使用闪存/ OTP 时要记住的其他一些要点：
• 对 USER OTP 位置的读取被硬连线用于 10 个等待状态。 RWAIT 位对这些位置没有影响。
• CPU 对闪存或 OTP 存储器映射区域的写入将被忽略。它们在一个周期内完成。
• 如果安全区域处于锁定状态，并且各自的密码锁定位不全为 1，则，
– 读取 Zx-CSMPSWD 的数据将返回 0
– 读取 Zx-CSMPSWD 的程序空间将返回 0
– 程序获取 Zx-CSMPSWD 将返回 0
• 当双代码安全模块 (DCSM) 受到保护时，从安全区外部读取闪存/OTP 存储器映射区域的周期数与正常访问相同。但是，读取操作返回零。
• FMC 中的仲裁方案按数据读取（最高优先级）、程序空间读取和程序读取/程序预取（最低优先级）的固定优先级顺序确定 CPU 访问的优先级。
• 当 FSM 接口为擦除/编程操作激活时，FMC 中的预取缓冲区和数据缓存中的数据将被刷新。
启用数据缓存后，向 Flash/OTP 空间打开的调试器内存窗口将调用数据缓存。因此，在对代码进行性能基准测试时，不应为 Flash/OTP 空间打开调试器内存窗口。
笔记
Flash 内容在进入预取缓冲区或数据缓存之前验证 ECC 的正确性，而不是在预取缓冲区或数据缓存本身内部。

3.12.8.3 Data Cache
Along with the prefetch mechanism, a data cache of 128-bits wide is also implemented to improve data-space read and program-space read performance. This data cache will not be filled by the prefetch mechanism. When any kind of data-space read or program-space read is made by the CPU from an address in the bank, and if the data corresponding to the requested address is not in the data cache, then 128 bits of data will be read from the bank and loaded in the data cache. This data is eventually sent to the CPU for processing. The starting address of the access from flash is automatically aligned to a 128-bit boundary such that the requested address location is within the 128 bits to be read from the bank. By default, this data cache is disabled and can be enabled by setting DATA_CACHE_EN bit in the FRD_INTF_CTRL register. Note that the data cache gets bypassed when RWAIT is configured as zero.
Some other points to keep in mind when working with flash/ OTP:
• Reads of the USER OTP locations are hardwired for 10 wait states. The RWAIT bits have no effect on these
locations.
• CPU writes to the flash or OTP memory map areas are ignored. They complete in a single cycle.
• If a security zone is in the locked state and the respective password lock bits are not all 1s, then,
– Data reads to Zx-CSMPSWD will return 0
– Program space reads to Zx-CSMPSWD will return 0
– Program fetches to Zx-CSMPSWD will return 0
• When the Dual Code Security Module (DCSM) is secured, reads to the flash/OTP memory map area from outside the secure zone take the same number of cycles as a normal access. However, the read operation returns a zero.
• The arbitration scheme in FMC prioritizes CPU accesses in the fixed priority order of data read (highest priority), program space read and program fetches/program prefetches (lowest priority).
• When FSM interface is active for erase/program operations, data in the prefetch buffers and data cache in FMC will be flushed.
When the data cache is enabled, the debugger memory window open to Flash/OTP space will invoke data caching. Therefore, the debugger memory window should not be left open for Flash/OTP space when benchmarking the code for performance.
Note
Flash contents are verified for ECC correctness before they enter prefetch buffer or data cache and not inside the prefetch buffer or data cache itself.

2.1.7 3.12.9 Erase/Program Flash

3.12.9 擦除/编程闪存
闪存可以通过使用 CCS 闪存插件或使用 Uniflash 进行编程。如果这些方法在应用程序中不可行，则可以使用 API。 Flash 存储器只能使用 F021 Flash API 库进行编程、擦除和验证。这些函数由德州仪器编写、编译和验证。闪存模块包含一个闪存状态机 (FSM)，用于执行编程和擦除操作。
本节仅提供对这些操作的高级描述；有关更多信息，请参阅 TMS320F28004x 闪存 API 参考指南。
请注意，Flash API 执行是可中断的。但是，不应对正在进行擦除/编程操作的闪存组进行任何读取/获取访问。在单组设备中，Flash API 必须从 RAM 执行。在双存储体设备中，闪存 API 可以从一个存储体执行以在另一存储体上执行擦除/编程操作。如果启用预取，请注意在擦除/编程 Bank1 时不应访问 Bank0 的最后 128 位，因为访问它们将导致对 Bank1 的预取访问。
闪存编程的典型流程是：
擦除 → 编程 → 验证
请始终参考 C2000Ware 中特定于设备的支持文件夹以获取最新的 Flash API 库。

3.12.9 Erase/Program Flash
Flash memory may be programmed either by using the CCS Flash plugin or by using Uniflash. If these methods are not feasible in an application, the API may be used. The Flash memory should be programmed, erased, and verified only by using the F021 Flash API library. These functions are written, compiled and validated by Texas Instruments. The flash module contains a flash state machine (FSM) to perform program and erase operations.
This section only provides a high-level description for these operations; for more information, refer to the TMS320F28004x Flash API Reference Guide.
Note that Flash API execution is interruptible. However, there should not be any read/fetch access from the Flash bank on which an erase/program operation is in progress. In single-bank devices, Flash API must be executed from RAM. In dual-bank devices Flash API can execute from one bank to perform erase/program operations on another bank. If prefetch is enabled, note that the last 128 bits of Bank0 should not be accessed when erasing/programming Bank1 since accessing them will cause a prefetch access to Bank1.
A typical flow to program flash is:
Erase → Program → Verify
Always refer to the device-specific support folder in C2000Ware for the latest Flash API library.

3.12.9.1 擦除
当目标闪存被擦除时，它读取为全 1。这种状态称为“空白”。擦除功能必须在编程前执行。用户不应跳过读取为“空白”的扇区的擦除，因为这些扇区可能需要额外的擦除，因为这些扇区可能会由于边缘擦除位列而需要额外擦除。 FSM 提供“擦除扇区”命令来擦除目标扇区。擦除功能将数据和 ECC 一起擦除。该命令由以下 Flash API 函数实现： Fapi_issueAsyncCommandWithAddress();
Flash API 提供以下函数来确定闪存库是否为“空白”： Fapi_doBlankCheck();

3.12.9.1 Erase
When the target flash is erased, it reads as all 1’s. This state is called ‘blank.’ The erase function must be executed before programming. The user should NOT skip erase on sectors that read as ‘blank’ because these sectors may require additional erasing due to marginally erased bits columns. The FSM provides an “Erase Sector” command to erase the target sector. The erase function erases the data and the ECC together. This command is implemented by the following Flash API function: Fapi_issueAsyncCommandWithAddress();
The Flash API provides the following function to determine if the flash bank is ‘blank’: Fapi_doBlankCheck();

3.12.9.2 编程 Programming
FSM 提供了一个命令来对 USER OTP 和 Flash 进行编程。该命令还用于编程 ECC 校验位。
该命令由以下 Flash API 函数实现：
Fapi_issueProgrammingCommand();
编程功能提供了编程不带 ECC 的数据、带有用户提供的 ECC 数据和由 API 软件计算的 ECC 的数据以及仅编程 ECC 的选项。
笔记
主阵列闪存编程必须与 64 位地址边界对齐，并且每个 64 位字每个写/擦除周期只能编程一次。
DCSM OTP 编程必须与 128 位地址边界对齐，并且每个 128 位字只能编程一次。例外情况是：
• DCSM OTP 中的 DCSM Zx-LINKPOINTER1 和 Zx-LINKPOINTER2 值应该一起编程，并且可以根据 DCSM 操作的要求一次编程 1 位。
• DCSM OTP 中的 DCSM Zx-LINKPOINTER3 值可以在 64 位边界上一次编程 1 位，以将其与 Zx-PSWDLOCK 分开，Zx-PSWDLOCK 只能编程一次。

3.12.9.2 Program
The FSM provides a command to program the USER OTP and Flash. This command is also used to program ECC check bits.
This command is implemented by the following Flash API function:
Fapi_issueProgrammingCommand();
The Program function provides the options to program data without ECC, data with user-provided ECC data with ECC calculated by API software, and to program ECC only.
Note
The main array Flash programming must be aligned to 64-bit address boundaries and each 64-bit word may only be programmed once per write/erase cycle.
The DCSM OTP programming must be aligned to 128-bit address boundaries and each 128-bit word may only be programmed once. The exceptions are:
• The DCSM Zx-LINKPOINTER1 and Zx-LINKPOINTER2 values in the DCSM OTP should be programmed together, and may be programmed 1 bit at a time as required by the DCSM operation.
• The DCSM Zx-LINKPOINTER3 values in the DCSM OTP may be programmed 1 bit at a time on a 64-bit boundary to separate it from Zx-PSWDLOCK, which must only be programmed once.

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