异步FIFO代码（包含almost_full以及almost_empty信号），测试代码，功能仿真结果

更新一波代码以及测试，之前的输出没有用寄存器输出。
这次改进的代码加入了将满almost_full以及将空almost_empty信号

Verilog代码

module async_FIFO_01 #(parameter data_width = 8,addr_width = 6,depth = 64,almost_full_gap = 50,almost_empty_gap = 10)(  input rst_n,        //复位input wr_clk,       //写时钟input wr_en,       //写使能信号input [data_width-1:0] data_in,      //外部输入数据input rd_clk,       //读时钟input rd_en,       //读使能output [data_width-1:0] data_out,  //数据输出output reg full,output reg empty,output reg almost_full,output reg almost_empty);reg [addr_width:0] wr_addr_ptr,wr_addr_ptr_next;         //write address pointerreg [addr_width:0] rd_addr_ptr,rd_addr_ptr_next;     //read address pointerwire [addr_width:0] wr_addr_ptr_gray;wire [addr_width:0] rd_addr_ptr_gray;reg [addr_width:0] wr_addr_ptr_gray_1,wr_addr_ptr_gray_2;reg [addr_width:0] rd_addr_ptr_gray_1,rd_addr_ptr_gray_2;reg [addr_width-1:0] wr_addr;                         //write addresswire [addr_width-1:0] wr_addr_next;                  reg [addr_width-1:0] rd_addr;                           //read addresswire [addr_width-1:0] rd_addr_next;               wire full_next,empty_next;wire almost_full_next,almost_empty_next;assign SRAM_wr_en = wr_en && !full_next;assign SRAM_rd_en = rd_en && !empty_next;   //write address pointer updatealways @ (*)if (!rst_n)wr_addr_ptr_next = 'b0;else if (wr_en && !full_next)wr_addr_ptr_next = wr_addr_ptr + 1'b1;elsewr_addr_ptr_next = wr_addr_ptr;//read address pointer updatealways @ (*)if (!rst_n)rd_addr_ptr_next = 'b0;else if (rd_en && !empty_next)rd_addr_ptr_next = rd_addr_ptr + 1'b1;elserd_addr_ptr_next = rd_addr_ptr;//write and read address updateassign wr_addr_next = wr_addr_ptr_next[addr_width-1:0];assign rd_addr_next = rd_addr_ptr_next[addr_width-1:0];//写地址指针格雷码转换assign wr_addr_ptr_gray = (wr_addr_ptr >> 1) ^ wr_addr_ptr;//读地址指针格雷码转换assign rd_addr_ptr_gray = (rd_addr_ptr >> 1) ^ rd_addr_ptr;//写地址指针格雷码同步到读时钟域always @ (posedge rd_clk or negedge rst_n)if (!rst_n)beginwr_addr_ptr_gray_1 <= 'b0;wr_addr_ptr_gray_2 <= 'b0;endelsebeginwr_addr_ptr_gray_1 <= wr_addr_ptr_gray;wr_addr_ptr_gray_2 <= wr_addr_ptr_gray_1;end//读地址指针格雷码同步到写时钟域always @ (posedge wr_clk or negedge rst_n)if (!rst_n)beginrd_addr_ptr_gray_1 <= 'b0;rd_addr_ptr_gray_2 <= 'b0;endelsebeginrd_addr_ptr_gray_1 <= rd_addr_ptr_gray;rd_addr_ptr_gray_2 <= rd_addr_ptr_gray_1;end//同步过后的格雷码进行二进制转换，用于产生将空将满wire [addr_width:0] wr_addr_ptr_gray_to_bin;wire [addr_width:0] rd_addr_ptr_gray_to_bin;assign  wr_addr_ptr_gray_to_bin[addr_width] = wr_addr_ptr_gray_2[addr_width];assign  rd_addr_ptr_gray_to_bin[addr_width] = rd_addr_ptr_gray_2[addr_width];genvar i;generatefor (i=0;i<addr_width;i=i+1)beginassign wr_addr_ptr_gray_to_bin[i] = wr_addr_ptr_gray_2[i]^wr_addr_ptr_gray_to_bin[i+1];assign rd_addr_ptr_gray_to_bin[i] = rd_addr_ptr_gray_2[i]^rd_addr_ptr_gray_to_bin[i+1];endendgenerate//full_next信号产生assign full_next = ({~wr_addr_ptr_gray[addr_width:addr_width-1],wr_addr_ptr_gray[addr_width-2:0]}) == rd_addr_ptr_gray_2 ? 1'b1:1'b0;//empty_next信号产生assign empty_next = wr_addr_ptr_gray_2 == rd_addr_ptr_gray ? 1'b1: 1'b0;reg [addr_width-1:0] data_avail;reg [addr_width-1:0] room_avail;//data_avail信号生成，用于进行将满判断always @ (*)beginif (wr_addr_ptr[addr_width]!=rd_addr_ptr_gray_to_bin[addr_width])beginif (wr_addr_ptr[addr_width-1:0]==rd_addr_ptr_gray_to_bin[addr_width-1:0])data_avail = depth-1;elsedata_avail = depth-(rd_addr_ptr_gray_to_bin[addr_width-1:0]-wr_addr_ptr[addr_width-1:0]);endelsedata_avail = wr_addr_ptr[addr_width-1:0]-rd_addr_ptr_gray_to_bin[addr_width-1:0];endassign almost_full_next = (data_avail >= almost_full_gap)? 1'b1: 1'b0;//room_avail信号生成，用于进行将空判断always @ (*)beginif (rd_addr_ptr[addr_width]==wr_addr_ptr_gray_to_bin[addr_width])beginif (wr_addr_ptr_gray_to_bin[addr_width-1:0]==rd_addr_ptr[addr_width-1:0])room_avail = depth-1;elseroom_avail = depth-(wr_addr_ptr_gray_to_bin[addr_width-1:0]-rd_addr_ptr[addr_width-1:0]);endelseroom_avail = rd_addr_ptr[addr_width-1:0]-wr_addr_ptr_gray_to_bin[addr_width-1:0];endassign almost_empty_next = (room_avail >= (depth-almost_empty_gap))? 1'b1:1'b0;//输出信号打拍always @ (posedge wr_clk or negedge rst_n)if (!rst_n)beginwr_addr_ptr <= 'b0;full <= 'b0;almost_full <= 'b0;wr_addr <= 'b0;endelsebeginwr_addr_ptr <= wr_addr_ptr_next;full <= full_next;almost_full <= almost_full_next;wr_addr <= wr_addr_next;endalways @ (posedge rd_clk or negedge rst_n)if (!rst_n)beginrd_addr_ptr <= 'b0;empty <= 'b0;almost_empty <= 'b0;rd_addr <= 'b0;endelsebeginrd_addr_ptr <= rd_addr_ptr_next;empty <= empty_next;almost_empty <= almost_empty_next;rd_addr <= rd_addr_next;end//模块例化sram m0 (.wr_clk (wr_clk),.wr_en (SRAM_wr_en ),.wr_addr (wr_addr),.rd_clk (rd_clk),.rd_en (SRAM_rd_en ),.rd_addr (rd_addr),.data_in (data_in),.data_out (data_out));
endmodule

SRAM模块

module   sram  #(parameter data_width = 8,addr_width = 6,depth = 64,almost_full_gap = 50,almost_empty_gap = 20)(input   wr_clk,input    wr_en,input   [addr_width-1:0] wr_addr,input   rd_clk,input   rd_en,input   [addr_width-1:0] rd_addr,input   [data_width-1:0] data_in,output reg [data_width-1:0] data_out);//存储阵列定义reg [data_width-1:0] SRAM_MEM [depth-1:0];//数据写入always @ (posedge wr_clk)if (wr_en)SRAM_MEM [wr_addr] <= data_in;elseSRAM_MEM [wr_addr] <= SRAM_MEM [wr_addr];//数据读出always @ (posedge rd_clk)if (rd_en)data_out <= SRAM_MEM [rd_addr];elsedata_out <= 'b0;
endmodule

testbench文件


`timescale 1ns / 1psmodule sim_async_FIFO_01;parameter          data_width = 8,addr_width = 6,depth = 64,almost_full_gap = 50,almost_empty_gap = 10;reg rst_n;reg wr_clk;reg wr_en;reg [data_width-1:0] data_in;reg rd_clk;reg rd_en;wire [data_width-1:0] data_out;wire full;wire empty;wire almost_empty;wire almost_full;async_FIFO_01 x1( .rst_n(rst_n),.wr_clk(wr_clk),.wr_en(wr_en),.data_in(data_in),.rd_clk(rd_clk),.rd_en(rd_en),.data_out(data_out),.full(full),.empty(empty),.almost_full(almost_full),.almost_empty(almost_empty));initialbeginwr_clk = 1'b0;rst_n = 1'b0;wr_en = 1'b0;rd_clk = 1'b0;rd_en = 1'b0;data_in = 8'b1111_1111;#40 rst_n = 1'b1;#40 wr_en = 1'b1;#20 data_in = 8'b1001_1011;#20 data_in = 8'b0010_1011;#20 data_in = 8'b1001_0000;#20 data_in = 8'b0000_1011;#20 data_in = 8'b1001_1101;#1200 rd_en = 1'b1;#500 wr_en = 1'b0;#20 data_in = 8'b1001_0000;#20 data_in = 8'b0000_1011;#20 data_in = 8'b0000_0000;#20 data_in = 8'b0010_1011;#20 data_in = 8'b0000_1101;#3000 rd_en = 1'b0;endalways #10 wr_clk = ~wr_clk;always #20 rd_clk = ~rd_clk;endmodule

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异步FIFO代码（包含almost_full以及almost_empty信号），测试代码，功能仿真结果

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