`timescale 1ns / 1ps
//
// Company:
// Engineer:
//
// Create Date: 2017/03/10 11:08:45
// Design Name:
// Module Name: spi_core
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//module spi_core(input clk,//50Minput rst,input [7:0] din,  //要输出input s_valid,      //要输出input[1:0] readnum,//指示指令读取数据的长度 2’b00:0,2'b01:8,2'b10:256,2'b11:1664480(320*257*2)output spi_ready,output [23:0] dout,output m_valid,input cfg_finsih,input spi_miso,output spi_mosi,output spi_cs,output spi_clk,output empty);
/*
本模块只完成SPI协议所规定的时序，不涉及FLASH指令的编写
*/
parameter IDLE = 3'd0;
parameter S1   = 3'd1;
parameter S2   = 3'd2;
parameter S3   = 3'd3;
parameter S4   = 3'd4;
parameter S5   = 3'd5;
parameter S6   = 3'd6;
parameter Smid =3'd7;
reg [2:0] sta_spi;
reg spi_ready_r;
reg spi_clk_r;
reg spi_cs_r;
reg spi_mosi_r;wire wr_en;
reg rd_en;
wire dout_fifo;
//wire empty;
wire full;
wire[14:0] rd_count;assign spi_clk  = spi_clk_r;
assign spi_cs   = spi_cs_r;
assign spi_mosi = dout_fifo;//spi_mosi_r;
assign spi_ready = spi_ready_r;
assign wr_en = s_valid;
//fifo_generator_0 fifo_generator_0 (
//.rst(~rst),        // input wire rst
//.wr_clk(clk),  // input wire wr_clk
//.rd_clk(clk),  // input wire rd_clk
//.din(din),        // input wire [7 : 0] din
//.wr_en(wr_en),    // input wire wr_en
//.rd_en(rd_en),    // input wire rd_en
//.dout(dout_fifo),      // output wire [0 : 0] dout
//.full(full),      // output wire full
//.empty(empty),    // output wire empty
//.rd_data_count(rd_count)
//);
fifo_generator_0 fifo_generator_0 (.clk(clk),                      // input wire clk.srst(~rst),                    // input wire srst.din(din),                      // input wire [7 : 0] din.wr_en(wr_en),                  // input wire wr_en.rd_en(rd_en),                  // input wire rd_en.dout(dout_fifo),                    // output wire [0 : 0] dout.full(full),                    // output wire full.empty(empty)                 // output wire empty
//  .rd_data_count(rd_count)  // output wire [15 : 0] rd_data_count
);
reg recv_reg;
reg recv_ok;
reg [20:0] recv_num;
reg [20:0] NUM;
always @(posedge clk)
beginif(~rst)beginsta_spi <= IDLE;spi_clk_r <= 1'b1;spi_cs_r <= 1'b1;spi_mosi_r <=1'b0;rd_en <= 1'b0;recv_reg <= 1'b0;recv_ok <= 1'b0;spi_ready_r <= 1'b0;recv_num <= 21'd0;endelse begincase(sta_spi)IDLE:begin recv_ok <= 1'b0;recv_num <= 21'd0;spi_clk_r <= 1'b1;                if(~empty)beginrd_en <= 1'b1;sta_spi <= S1;spi_ready_r <= 1'b0;endelsespi_ready_r <= 1'b1;endS1:beginrd_en <= 1'b0;spi_clk_r <= 1'b0;spi_cs_r <= 1'b0;spi_mosi_r <= dout_fifo;sta_spi <= S2;endS2:beginspi_clk_r <= 1'b1;
//                sta_spi <= S3;if(~empty)beginrd_en <= 1'b1;sta_spi <= S1;                    end
//                else if(empty)
//                spi_cs_r<=1'b1;   else if(readnum!=2'b00)  //就是要读数的意思sta_spi <= S4;elsesta_spi <= S3;         endS3:beginsta_spi <= IDLE;spi_clk_r <= 1'b0;spi_cs_r <= 1'b1;endS4:beginspi_clk_r <= 1'b0;recv_ok <= 1'b0;sta_spi <= S5;endS5:beginspi_clk_r <= 1'b1;recv_num <= recv_num +1'b1;recv_reg <= spi_miso;recv_ok <= 1'b1;            if(recv_num!=NUM)sta_spi <= S4;else beginsta_spi <= IDLE;spi_cs_r <= 1'b1;endendendcaseend
endalways @(posedge clk)
beginif(~rst)NUM <= 21'd0;else begincase(readnum)2'b00:NUM <= 21'd0;2'b01:NUM <= 21'd7;2'b11:NUM <= 21'd23;endcaseend
end
reg [23:0] dout_r;
reg m_valid_r;
reg [3:0] cnt_bit;
always @(posedge clk)
beginif(~rst)begindout_r <= 16'd0;m_valid_r <= 1'b0;cnt_bit <= 4'd0;endelse if(recv_ok)begin//m_valid_r <= 1'b0;dout_r <= {dout_r[22:0],recv_reg};cnt_bit <= cnt_bit + 1'b1;if(cnt_bit==4'd15)m_valid_r <= 1'b1;elsem_valid_r <= 1'b0;endelsem_valid_r <= 1'b0;
end
assign dout = dout_r;
assign m_valid = m_valid_r;/*********************************/
endmodule