ADI官网 hdl代码及sdk工程编译过程

以AD9371为例：

E:\>which git
/cygdrive/d/Program Files/Git/cmd/git

E:\>path
PATH=C:\Keil_v5\ARM\Segger\;D:\MentorGraphics\9.5PADS\SDD_HOME\common\win32\bin;
D:\MentorGraphics\9.5PADS\SDD_HOME\common\win32\lib;D:\MentorGraphics\9.5PADS\MG
C_HOME.ixn\bin;D:\MentorGraphics\9.5PADS\MGC_HOME.ixn\lib;C:\Program Files (x86)
\STMicroelectronics\st_toolset\asm;C:\Windows\system32;C:\Windows;C:\Windows\Sys
tem32\Wbem;C:\Windows\System32\WindowsPowerShell\v1.0\;C:\Program Files\Tortoise
Hg\;C:\Program Files\Java\jdk1.8.0_121\jre\bin;C:\Program Files\Java\jdk1.8.0_12
1\bin;C:\ProgramData\Oracle\Java\javapath;C:\Program Files\TortoiseSVN\bin;C:\Pr
ogram Files (x86)\Windows Kits\8.1\Windows Performance Toolkit\;C:\Program Files
\Microsoft SQL Server\110\Tools\Binn\;%NDK——ROOT%;C;\Emgu\emgucv-windesktop 3.
3.0.2824\bin;C:\Emgu\emgucv-windesktop 3.3.0.2824\bin\x64;C:\Program Files (x86)
\Agilent\IO Libraries Suite\bin;C:\Program Files\Agilent\IO Libraries Suite\bin;
C:\Program Files (x86)\IVI Foundation\VISA\WinNT\agvisa;C:\Program Files\IVI Fou
ndation\VISA\Win64\agvisa;C:\Program Files\IVI Foundation\VISA\Win64\Bin\;C:\Pro
gram Files (x86)\IVI Foundation\VISA\WinNT\Bin\;D:\MentorGraphics\9.5PADS\SDD_HO
ME\CAMCAD;C:\Program Files\Intel\WiFi\bin\;C:\Program Files\Common Files\Intel\W
irelessCommon\;C:\Program Files (x86)\scala\bin;D:\software\gradle-4.10.2-bin\gr
adle-4.10.2\bin;E:\Program Files\MATLAB\R2017a\runtime\win64;E:\Program Files\MA
TLAB\R2017a\bin;E:\tmp\morescodetotal\googleAPM\cmake-3.13.2-win64-x64\bin;C:\Pr
ogram Files\Keysight\IO Libraries Suite\bin;C:\Program Files\IVI Foundation\VISA
\Win64\ktvisa;C:\Program Files (x86)\Keysight\IO Libraries Suite\bin;C:\Program
Files (x86)\IVI Foundation\VISA\WinNT\ktvisa;C:\Program Files (x86)\IVI Foundati
on\IVI\bin;C:\Program Files\IVI Foundation\IVI\bin;C:\Program Files\MySQL\MySQL
Utilities 1.6\;D:\Program Files\Git\cmd;D:\gnumake\;E:\cygwin64\bin;C:\Program F
iles\Intel\WiFi\bin\;C:\Program Files\Common Files\Intel\WirelessCommon\;D:\Prog
ram Files\IntelliJ IDEA 2018.3.1\bin;;D:\BaiduNetdiskDownload\fpga\iStyle_window
s_x86_64

E:\>export PATH=$PATH:/wygdrive/f/Xilinx/Vivado/2017.4/bin
'export' 不是内部或外部命令，也不是可运行的程序
或批处理文件。

E:\>f:\Xilinx\Vivado\2017.4\.settings64-Vivado.bat

E:\>path
PATH=F:\Xilinx\Vivado\2017.4\bin;F:\Xilinx\Vivado\2017.4\lib\win64.o;C:\Keil_v5\
ARM\Segger\;D:\MentorGraphics\9.5PADS\SDD_HOME\common\win32\bin;D:\MentorGraphic
s\9.5PADS\SDD_HOME\common\win32\lib;D:\MentorGraphics\9.5PADS\MGC_HOME.ixn\bin;D
:\MentorGraphics\9.5PADS\MGC_HOME.ixn\lib;C:\Program Files (x86)\STMicroelectron
ics\st_toolset\asm;C:\Windows\system32;C:\Windows;C:\Windows\System32\Wbem;C:\Wi
ndows\System32\WindowsPowerShell\v1.0\;C:\Program Files\TortoiseHg\;C:\Program F
iles\Java\jdk1.8.0_121\jre\bin;C:\Program Files\Java\jdk1.8.0_121\bin;C:\Program
Data\Oracle\Java\javapath;C:\Program Files\TortoiseSVN\bin;C:\Program Files (x86
)\Windows Kits\8.1\Windows Performance Toolkit\;C:\Program Files\Microsoft SQL S
erver\110\Tools\Binn\;%NDK——ROOT%;C;\Emgu\emgucv-windesktop 3.3.0.2824\bin;C:\
Emgu\emgucv-windesktop 3.3.0.2824\bin\x64;C:\Program Files (x86)\Agilent\IO Libr
aries Suite\bin;C:\Program Files\Agilent\IO Libraries Suite\bin;C:\Program Files
(x86)\IVI Foundation\VISA\WinNT\agvisa;C:\Program Files\IVI Foundation\VISA\Win
64\agvisa;C:\Program Files\IVI Foundation\VISA\Win64\Bin\;C:\Program Files (x86)
\IVI Foundation\VISA\WinNT\Bin\;D:\MentorGraphics\9.5PADS\SDD_HOME\CAMCAD;C:\Pro
gram Files\Intel\WiFi\bin\;C:\Program Files\Common Files\Intel\WirelessCommon\;C
:\Program Files (x86)\scala\bin;D:\software\gradle-4.10.2-bin\gradle-4.10.2\bin;
E:\Program Files\MATLAB\R2017a\runtime\win64;E:\Program Files\MATLAB\R2017a\bin;
E:\tmp\morescodetotal\googleAPM\cmake-3.13.2-win64-x64\bin;C:\Program Files\Keys
ight\IO Libraries Suite\bin;C:\Program Files\IVI Foundation\VISA\Win64\ktvisa;C:
\Program Files (x86)\Keysight\IO Libraries Suite\bin;C:\Program Files (x86)\IVI
Foundation\VISA\WinNT\ktvisa;C:\Program Files (x86)\IVI Foundation\IVI\bin;C:\Pr
ogram Files\IVI Foundation\IVI\bin;C:\Program Files\MySQL\MySQL Utilities 1.6\;D
:\Program Files\Git\cmd;D:\gnumake\;E:\cygwin64\bin;C:\Program Files\Intel\WiFi\
bin\;C:\Program Files\Common Files\Intel\WirelessCommon\;D:\Program Files\Intell
iJ IDEA 2018.3.1\bin;;D:\BaiduNetdiskDownload\fpga\iStyle_windows_x86_64

E:\>which vivado
/cygdrive/f/Xilinx/Vivado/2017.4/bin/vivado

E:\>alias xmd=xmd.bat
'alias' 不是内部或外部命令，也不是可运行的程序
或批处理文件。

E:\>e:\cygwin64\Cygwin.bat
Copying skeleton files.
These files are for the users to personalise their cygwin experience.

They will never be overwritten nor automatically updated.

'./.bashrc' -> '/home/joe//.bashrc'
'./.bash_profile' -> '/home/joe//.bash_profile'
'./.inputrc' -> '/home/joe//.inputrc'
'./.profile' -> '/home/joe//.profile'

joe@joe-PC ~
$ which vivado
/cygdrive/f/Xilinx/Vivado/2017.4/bin/vivado
(在我的电脑上，因为cygwin64安装在e:\cygwin64目录下，所以当我再启动一个cmd执行e:\cygwin64目录下的Cygwin.bat之后，执行：
$ which vivado
/cygdrive/D/Xilinx/vivado/Vivado/2018.1/bin/vivado
这是因为我的电脑上安装有从个版本的vivado的原因，我目前想用的是2017.4版本，所以不能在cygwin64目录下执行这个bat命令之后再做其它设置命令，只能按我前面的操作使用which vivado的值为/cygdrive/f/Xilinx/Vivado/2017.4/bin/vivado)
再根据网页https://wiki.analog.com/resources/fpga/docs/build上所说：
joe@joe-PC ~
$ alias xmd=xmd.bat

joe@joe-PC ~
$ alias xsct=xsct.bat

joe@joe-PC ~
$ alias xsdb=xsdb.bat

joe@joe-PC ~
$ ls /cygdrive
c d e f g h

joe@joe-PC ~
$ cd /cygdrive/e

joe@joe-PC /cygdrive/e
$ cd tmp/AD9371total/hdl

joe@joe-PC /cygdrive/e/tmp/AD9371total/hdl
$ git branch -a
* hdl_2016_r2
master
remotes/origin/HEAD -> origin/master
remotes/origin/ad7768_pack
remotes/origin/ad9656_eval_proj_dev
remotes/origin/add_adin1100_rmii_support
remotes/origin/add_adin1100_support
remotes/origin/add_adv7513_de10nano
remotes/origin/adrv9009_zcu102_2_tx_lanes
remotes/origin/adrv9009_zu11eg_multisom_sync_2019
remotes/origin/adrv9009zu11eg_mutisom_sync_master
remotes/origin/adrv9009zu11eg_som_sfp_10g
remotes/origin/adrv936x_production
remotes/origin/axi_ad9361_iodelayctrl
remotes/origin/axi_spi_engine_revert_pulse_period
remotes/origin/cn0540_coraz7s_xadc
remotes/origin/daq2_det_latency_test
remotes/origin/data_offload
remotes/origin/de10nano_cn0540
remotes/origin/de10nano_cn0540_syncspi
remotes/origin/de10nano_cn0540_video
remotes/origin/debug_adrv9009
remotes/origin/dev_ad_mux
remotes/origin/dev_adc_trigger_window

joe@joe-PC /cygdrive/e/tmp/AD9371total/hdl
$ git fetch
Username for 'https://gitee.com':
Password for 'https://whoisliang@gitee.com':

joe@joe-PC /cygdrive/e/tmp/AD9371total/hdl
$ git rebase origin/hdl_2016_r2
当前分支 hdl_2016_r2 是最新的。
joe@joe-PC /cygdrive/e/tmp/AD9371total/hdl
$ cd projects/adrv9371x/zc706

joe@joe-PC /cygdrive/e/tmp/AD9371total/hdl/projects/adrv9371x/zc706
$ make
make -C ../../../library/axi_ad9371
make[1]: 进入目录“/cygdrive/e/tmp/AD9371total/hdl/library/axi_ad9371”
rm -rf *.cache *.data *.xpr *.log component.xml *.jou xgui *.ip_user_files *.src
s *.hw *.sim .Xil
vivado -mode batch -source axi_ad9371_ip.tcl >> axi_ad9371_ip.log 2>&1
make[1]: *** [Makefile:70：axi_ad9371.xpr] 错误 1
make[1]: 离开目录“/cygdrive/e/tmp/AD9371total/hdl/library/axi_ad9371”
make: *** [Makefile:80：lib] 错误 2

查看axi_ad9371_ip.log文件发现是因为vivado版本不正确，library\scriptes\adi_ip.tcl代码中：
if {![info exists REQUIRED_VIVADO_VERSION]} {
set REQUIRED_VIVADO_VERSION "2016.2"
}
我将代码改为：
if {![info exists REQUIRED_VIVADO_VERSION]} {
set REQUIRED_VIVADO_VERSION "2017.4"
}
然后再次make

$ make
make -C ../../../library/axi_ad9371
make[1]: 进入目录“/cygdrive/e/tmp/AD9371total/hdl/library/axi_ad9371”
rm -rf *.cache *.data *.xpr *.log component.xml *.jou xgui *.ip_user_files *.src
s *.hw *.sim .Xil
vivado -mode batch -source axi_ad9371_ip.tcl >> axi_ad9371_ip.log 2>&1
make[1]: 离开目录“/cygdrive/e/tmp/AD9371total/hdl/library/axi_ad9371”
make -C ../../../library/xilinx/axi_adxcvr
make[1]: 进入目录“/cygdrive/e/tmp/AD9371total/hdl/library/xilinx/axi_adxcvr”
make -C ../../interfaces
make[2]: 进入目录“/cygdrive/e/tmp/AD9371total/hdl/library/interfaces”
vivado -mode batch -source interfaces_ip.tcl >> interfaces_ip.log 2>&1
make[2]: 离开目录“/cygdrive/e/tmp/AD9371total/hdl/library/interfaces”
rm -rf *.cache *.data *.xpr *.log component.xml *.jou xgui *.ip_user_files *.src
s *.hw *.sim .Xil
vivado -mode batch -source axi_adxcvr_ip.tcl >> axi_adxcvr_ip.log 2>&1
make[1]: 离开目录“/cygdrive/e/tmp/AD9371total/hdl/library/xilinx/axi_adxcvr”
make -C ../../../library/axi_clkgen
make[1]: 进入目录“/cygdrive/e/tmp/AD9371total/hdl/library/axi_clkgen”
rm -rf *.cache *.data *.xpr *.log component.xml *.jou xgui *.ip_user_files *.src
s *.hw *.sim .Xil
vivado -mode batch -source axi_clkgen_ip.tcl >> axi_clkgen_ip.log 2>&1
make[1]: *** [Makefile:48：axi_clkgen.xpr] 错误 139
make[1]: 离开目录“/cygdrive/e/tmp/AD9371total/hdl/library/axi_clkgen”
make: *** [Makefile:82：lib] 错误 2

查看：axi_clkgen_ip.log:
# adi_ip_properties axi_clkgen
INFO: [IP_Flow 19-459] IP file 'E:/tmp/AD9371total/hdl/library/xilinx/common/ad_mmcm_drp.v' appears to be outside of the project area 'e:/tmp/AD9371total/hdl/library/axi_clkgen'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
INFO: [IP_Flow 19-459] IP file 'E:/tmp/AD9371total/hdl/library/common/ad_rst.v' appears to be outside of the project area 'e:/tmp/AD9371total/hdl/library/axi_clkgen'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
INFO: [IP_Flow 19-459] IP file 'E:/tmp/AD9371total/hdl/library/common/up_axi.v' appears to be outside of the project area 'e:/tmp/AD9371total/hdl/library/axi_clkgen'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
INFO: [IP_Flow 19-459] IP file 'E:/tmp/AD9371total/hdl/library/common/up_clkgen.v' appears to be outside of the project area 'e:/tmp/AD9371total/hdl/library/axi_clkgen'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
INFO: [IP_Flow 19-459] IP file 'E:/tmp/AD9371total/hdl/library/xilinx/common/ad_mmcm_drp.v' appears to be outside of the project area 'e:/tmp/AD9371total/hdl/library/axi_clkgen'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
INFO: [IP_Flow 19-459] IP file 'E:/tmp/AD9371total/hdl/library/common/ad_rst.v' appears to be outside of the project area 'e:/tmp/AD9371total/hdl/library/axi_clkgen'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
INFO: [IP_Flow 19-459] IP file 'E:/tmp/AD9371total/hdl/library/common/up_axi.v' appears to be outside of the project area 'e:/tmp/AD9371total/hdl/library/axi_clkgen'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
INFO: [IP_Flow 19-459] IP file 'E:/tmp/AD9371total/hdl/library/common/up_clkgen.v' appears to be outside of the project area 'e:/tmp/AD9371total/hdl/library/axi_clkgen'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi' of definition 'ADI:user:if_xcvr_ch:1.0' (from User Repositories).
INFO: [IP_Flow 19-4753] Inferred signal 'reset' from port 's_axi_aresetn' as interface 's_axi_aresetn'.
INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'.
INFO: [IP_Flow 19-4753] Inferred signal 'clock' from port 's_axi_aclk' as interface 's_axi_aclk'.
INFO: [IP_Flow 19-4753] Inferred signal 'clock' from port 'clk' as interface 'clk'.
INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 's_axi_aresetn'.
INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files.
INFO: [IP_Flow 19-4623] Unrecognized family azynquplus. Please verify spelling and reissue command to set the supported files.
INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files.
INFO: [IP_Flow 19-4623] Unrecognized family qkintexu. Please verify spelling and reissue command to set the supported files.
INFO: [IP_Flow 19-4623] Unrecognized family virtexupluses1. Please verify spelling and reissue command to set the supported files.
INFO: [IP_Flow 19-4623] Unrecognized family virtexupluses1. Please verify spelling and reissue command to set the supported files.
INFO: [IP_Flow 19-4623] Unrecognized family zynqupluses2. Please verify spelling and reissue command to set the supported files.
INFO: [IP_Flow 19-4623] Unrecognized family zynqupluses2. Please verify spelling and reissue command to set the supported files.
INFO: [IP_Flow 19-4753] Inferred signal 'clock' from port 's_axi_aclk' as interface 's_axi_aclk'.
INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 's_axi'.
INFO: [IP_Flow 19-4753] Inferred signal 'reset' from port 's_axi_aresetn' as interface 's_axi_aresetn'.
INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'.
INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 's_axi_aresetn'.
# ipx::remove_bus_interface {clk} [ipx::current_core]
Abnormal program termination (EXCEPTION_ACCESS_VIOLATION)
Please check 'E:/tmp/AD9371total/hdl/library/axi_clkgen/hs_err_pid5068.log' for details
/cygdrive/f/Xilinx/Vivado/2017.4/bin/loader: 行 54: 1907 Segmentation fault "$RDI_BINROOT/loader.bat" "$@"

查看hs_err_pid5068.log内容：
#
# An unexpected error has occurred (EXCEPTION_ACCESS_VIOLATION)
#
Stack:
no stack trace available, please use hs_err_<pid>.dmp instead.

joe@joe-PC /cygdrive/e/tmp/AD9371total/hdl
$ git branch
* hdl_2016_r2
master

joe@joe-PC /cygdrive/e/tmp/AD9371total/hdl
$ git branch hdl_2018_r1

joe@joe-PC /cygdrive/e/tmp/AD9371total/hdl
$ git branch
* hdl_2016_r2
hdl_2018_r1
master

joe@joe-PC /cygdrive/e/tmp/AD9371total/hdl
$ git fetch
Username for 'https://gitee.com':
Password for 'https://whoisliang@gitee.com':

joe@joe-PC /cygdrive/e/tmp/AD9371total/hdl
$ git rebase origin/hdl_2018_r1
error: 不能变基：您有未暂存的变更。
error: 请提交或贮藏修改。
（说明：这是因为我将adi_ip.tcl中源代码set REQUIRED_VIVADO_VERSION "2016.2"改为了2017.4）改为原值再执行下面命令：

joe@joe-PC /cygdrive/e/tmp/AD9371total/hdl
$ git rebase origin/hdl_2018_r1
自动合并 library/axi_hdmi_tx/axi_hdmi_tx_ip.tcl
冲突（内容）：合并冲突于 library/axi_hdmi_tx/axi_hdmi_tx_ip.tcl
自动合并 library/axi_hdmi_rx/axi_hdmi_rx_ip.tcl
冲突（内容）：合并冲突于 library/axi_hdmi_rx/axi_hdmi_rx_ip.tcl
自动合并 library/axi_ad9963/axi_ad9963_ip.tcl
冲突（内容）：合并冲突于 library/axi_ad9963/axi_ad9963_ip.tcl
自动合并 library/axi_ad9739a/axi_ad9739a_ip.tcl
冲突（内容）：合并冲突于 library/axi_ad9739a/axi_ad9739a_ip.tcl
自动合并 library/axi_ad9684/axi_ad9684_ip.tcl
冲突（内容）：合并冲突于 library/axi_ad9684/axi_ad9684_ip.tcl
自动合并 library/axi_ad9680/axi_ad9680_ip.tcl
冲突（内容）：合并冲突于 library/axi_ad9680/axi_ad9680_ip.tcl
自动合并 library/axi_ad9671/axi_ad9671_ip.tcl
冲突（内容）：合并冲突于 library/axi_ad9671/axi_ad9671_ip.tcl
冲突（修改/删除）：library/axi_ad9652/axi_ad9652_ip.tcl 在 HEAD 中被删除，在 2ad
f76f6... library: Update scripts with new constraints 中被修改。library/axi_ad9
652/axi_ad9652_ip.tcl 的 2adf76f6... library: Update scripts with new constraint
s 版本被保留。
冲突（修改/删除）：library/axi_ad9643/axi_ad9643_ip.tcl 在 HEAD 中被删除，在 2ad
f76f6... library: Update scripts with new constraints 中被修改。library/axi_ad9
643/axi_ad9643_ip.tcl 的 2adf76f6... library: Update scripts with new constraint
s 版本被保留。
自动合并 library/axi_ad9625/axi_ad9625_ip.tcl
冲突（内容）：合并冲突于 library/axi_ad9625/axi_ad9625_ip.tcl
自动合并 library/axi_ad9467/axi_ad9467_ip.tcl
冲突（内容）：合并冲突于 library/axi_ad9467/axi_ad9467_ip.tcl
自动合并 library/axi_ad9434/axi_ad9434_ip.tcl
冲突（内容）：合并冲突于 library/axi_ad9434/axi_ad9434_ip.tcl
自动合并 library/axi_ad9371/axi_ad9371_ip.tcl
冲突（内容）：合并冲突于 library/axi_ad9371/axi_ad9371_ip.tcl
自动合并 library/axi_ad9361/axi_ad9361_ip.tcl
冲突（内容）：合并冲突于 library/axi_ad9361/axi_ad9361_ip.tcl
自动合并 library/axi_ad9265/axi_ad9265_ip.tcl
冲突（内容）：合并冲突于 library/axi_ad9265/axi_ad9265_ip.tcl
自动合并 library/axi_ad9250/axi_ad9250_ip.tcl
冲突（内容）：合并冲突于 library/axi_ad9250/axi_ad9250_ip.tcl
自动合并 library/axi_ad9162/axi_ad9162_ip.tcl
冲突（内容）：合并冲突于 library/axi_ad9162/axi_ad9162_ip.tcl
自动合并 library/axi_ad9152/axi_ad9152_ip.tcl
冲突（内容）：合并冲突于 library/axi_ad9152/axi_ad9152_ip.tcl
自动合并 library/axi_ad9144/axi_ad9144_ip.tcl
冲突（内容）：合并冲突于 library/axi_ad9144/axi_ad9144_ip.tcl
自动合并 library/axi_ad9122/axi_ad9122_ip.tcl
冲突（内容）：合并冲突于 library/axi_ad9122/axi_ad9122_ip.tcl
自动合并 library/axi_ad6676/axi_ad6676_ip.tcl
冲突（内容）：合并冲突于 library/axi_ad6676/axi_ad6676_ip.tcl
error: 不能应用 2adf76f6... library: Update scripts with new constraints
Resolve all conflicts manually, mark them as resolved with
"git add/rm <conflicted_files>", then run "git rebase --continue".
You can instead skip this commit: run "git rebase --skip".
To abort and get back to the state before "git rebase", run "git rebase --abort"
.
不能应用 2adf76f6... library: Update scripts with new constraints

最后，重新git clone https://github.com/analogdevicesinc/hdl.git
git checkout hdl_2018_r1 (为什么选这个分支，是因为我在此cmd中的vivado变量是2017.4，官网说用这个2018_r1版），进入projects\scripts目录，将adi_project.tcl中vivado版本由2017.4.1改为2017.4，另外，进入library\scripts\adi_ip.tcl中也将vivado版本改为2017.4，然后重新make:

joe@joe-PC /cygdrive/e/tmp/AD9371total/hdl/projects/adrv9371x/zc706
$ make
Building axi_ad9371 library [/cygdrive/e/tmp/AD9371total/hdl/library/axi_ad9371/
axi_ad9371_ip.log] ... OK
Building axi_clkgen library [/cygdrive/e/tmp/AD9371total/hdl/library/axi_clkgen/
axi_clkgen_ip.log] ... OK
Building util_cdc library [/cygdrive/e/tmp/AD9371total/hdl/library/util_cdc/util
_cdc_ip.log] ... OK
Building util_axis_fifo library [/cygdrive/e/tmp/AD9371total/hdl/library/util_ax
is_fifo/util_axis_fifo_ip.log] ... OK
Building util_axis_resize library [/cygdrive/e/tmp/AD9371total/hdl/library/util_
axis_resize/util_axis_resize_ip.log] ... OK
Building axi_dmac library [/cygdrive/e/tmp/AD9371total/hdl/library/axi_dmac/axi_
dmac_ip.log] ... OK
Building axi_hdmi_tx library [/cygdrive/e/tmp/AD9371total/hdl/library/axi_hdmi_t
x/axi_hdmi_tx_ip.log] ... OK
Building axi_spdif_tx library [/cygdrive/e/tmp/AD9371total/hdl/library/axi_spdif
_tx/axi_spdif_tx_ip.log] ... OK
Building axi_jesd204_common library [/cygdrive/e/tmp/AD9371total/hdl/library/jes
d204/axi_jesd204_common/axi_jesd204_common_ip.log] ... OK
Building axi_jesd204_rx library [/cygdrive/e/tmp/AD9371total/hdl/library/jesd204
/axi_jesd204_rx/axi_jesd204_rx_ip.log] ... OK
Building axi_jesd204_tx library [/cygdrive/e/tmp/AD9371total/hdl/library/jesd204
/axi_jesd204_tx/axi_jesd204_tx_ip.log] ... OK
Building jesd204_common library [/cygdrive/e/tmp/AD9371total/hdl/library/jesd204
/jesd204_common/jesd204_common_ip.log] ... OK
Building jesd204_rx library [/cygdrive/e/tmp/AD9371total/hdl/library/jesd204/jes
d204_rx/jesd204_rx_ip.log] ... OK
Building jesd204_tx library [/cygdrive/e/tmp/AD9371total/hdl/library/jesd204/jes
d204_tx/jesd204_tx_ip.log] ... OK
Building util_cpack library [/cygdrive/e/tmp/AD9371total/hdl/library/util_cpack/
util_cpack_ip.log] ... OK
Building util_upack library [/cygdrive/e/tmp/AD9371total/hdl/library/util_upack/
util_upack_ip.log] ... OK
Building interface definitions [/cygdrive/e/tmp/AD9371total/hdl/library/interfac
es/interfaces_ip.log] ... OK
Building axi_adxcvr library [/cygdrive/e/tmp/AD9371total/hdl/library/xilinx/axi_
adxcvr/axi_adxcvr_ip.log] ... OK
Building axi_dacfifo library [/cygdrive/e/tmp/AD9371total/hdl/library/xilinx/axi
_dacfifo/axi_dacfifo_ip.log] ... OK
Building util_adxcvr library [/cygdrive/e/tmp/AD9371total/hdl/library/xilinx/uti
l_adxcvr/util_adxcvr_ip.log] ... OK
Building adrv9371x_zc706 project [/cygdrive/e/tmp/AD9371total/hdl/projects/adrv9
371x/zc706/adrv9371x_zc706_vivado.log] ... OK

当我用vivado2017.4打开hdl\projects\adrv9371x\zc706\adrv9371x_zc706.xpr项目时不会出现类似9371 ip找不到,ad_iobuf.v找不到等异常，导出sdk之后，新建APP项目，将KC705-AD9371\AD9371_SDK\src目录下的所有文件复制到项目中(KC705-AD9371\AD9371_SDK\src参考https://blog.csdn.net/qq_20785973/article/details/83278990)，编译之后也不再出现common.h找不到，9371xxx宏没有定义等异常。

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