AD9364 测试平台开发——第六篇,SPI配置内容解析
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AD9364 测试平台开发——第六篇,SPI配置内容解析
以下为个人的一些理解,有一些东西可能不一定理解透彻了,可能有错误,请指正和见谅。
第一段指令:
BlockWrite 2,6 // Set ADI FPGA SPI to 20Mhz
SPIWrite 3DF,01 // Required for proper operation
ReadPartNumber
SPIWrite 2A6,0E // Enable Master Bias
SPIWrite 2A8,0E // Set Bandgap Trim
REFCLK_Scale 40.000000,1,2 // Sets local variables in script engine, user can ignore
SPIWrite 292,08 // Set DCXO Coarse Tune[5:0]. Coarse and Fine nominal values used with eval system. Other nominal values may be needed in a customer system
SPIWrite 293,80 // Set DCXO Fine Tune [12:5]
SPIWrite 294,00 // Set DCXO Fine Tune [4:0]
SPIWrite 2AB,07 // Set RF PLL reflclk scale to REFCLK * 2
SPIWrite 2AC,FF // Set RF PLL reflclk scale to REFCLK * 2
SPIWrite 009,07 // Enable Clocks
WAIT 20 // waits 20 ms
3DF—必须设置为1
2A6—必须设置为E
2A8—必须设置为E
1、设置晶振的调整参数(DCXO REGISTERS)
0x292 粗调
0x293、0x294: 微调
上面可以微调晶振。如果发现输出的信号中心频率偏差很大,则可能是这里没有设置好,修改微调的值可以明显看到中心频率的改变。
2、设置参考时钟频率(RxREF、TxREF)
0x2AB
0x2AC
例如:(Tx SYNTH 和Rx SYNTH范围支持10MHz-80MHz,最佳性能为 35M-80M之间)
0x2AB: 设置为0x07,RxREF为2倍参考晶振输入频率,40M2 = 80M
0x2AC: 设置为0xff,TxREF为2倍参考晶振输入频率,40M2 = 80M
3、设置参考时钟来源,并使能BBPLL
0x009
选择参考时钟是内部晶振,还是外部输入。
内部晶振和参考输入的频率范围是不同的,需要等下补充。
内部晶振的频率为19MHz-50MHz中间,
使用外部振荡器,频率为10MHz到80MHz之间变化
第二段指令:
//************************************************************
// Set BBPLL Frequency: 1280.000000
//************************************************************
SPIWrite 045,00 // Set BBPLL reflclk scale to REFCLK /1
SPIWrite 046,05 // Set BBPLL Loop Filter Charge Pump current
SPIWrite 048,E8 // Set BBPLL Loop Filter C1, R1
SPIWrite 049,5B // Set BBPLL Loop Filter R2, C2, C1
SPIWrite 04A,35 // Set BBPLL Loop Filter C3,R2
SPIWrite 04B,E0 // Allow calibration to occur and set cal count to 1024 for max accuracy
SPIWrite 04E,10 // Set calibration clock to REFCLK/4 for more accuracy
SPIWrite 043,00 // BBPLL Freq Word (Fractional[7:0])
SPIWrite 042,00 // BBPLL Freq Word (Fractional[15:8])
SPIWrite 041,00 // BBPLL Freq Word (Fractional[23:16])
SPIWrite 044,20 // BBPLL Freq Word (Integer[7:0])
SPIWrite 03F,05 // Start BBPLL Calibration
SPIWrite 03F,01 // Clear BBPLL start calibration bit
SPIWrite 04C,86 // Increase BBPLL KV and phase margin
SPIWrite 04D,01 // Increase BBPLL KV and phase margin
SPIWrite 04D,05 // Increase BBPLL KV and phase margin
WAIT_CALDONE BBPLL,2000 // Wait for BBPLL to lock, Timeout 2sec, Max BBPLL VCO Cal Time: 345.600 us (Done when 0x05E[7]==1)SPIRead 05E // Check BBPLL locked status (0x05E[7]==1 is locked)
设置BBPLL参考时钟频率 0x045
例如设置为0x00,BBPLL参考时钟为1倍晶振频率,40MHz*1 = 40MHz
BBPLL最佳性能范围:35-70MHz之间,那支持的范围呢??(有待补充)
BBPLL为芯片内部的工作频率,是AD/DA数据的处理时钟,其由REF时钟倍频产生,工作频率必须在715M-1.430GHz之间
046/048/049/04A:BBPLL的环路参数,不动
04B——允许VCO校准
04E——固定数
4、设置BBPLL时钟频率(此为AD/DA处理参考频率,与LO,VCO频率无关)
0x043:设置BBPLLL频率字小数部分,fractional[7:0]
0x042:设置BBPLLL频率字小数部分,fractional[15:8]
0x041:设置BBPLLL频率字小数部分,fractional[23:16]
0x044:设置BBPLLL频率字小数部分,integer[7:0];
例如0x44设置为0x20,则表示BBPLL时钟为 40*32 = 1280Mhz
详细计算公式稍后补充。
03F——开始校准,然后清除开始校准标志
04C/04D——固定数和固定操作
05E——等待锁定标志(0x05E[7]==1 is locked)
第三段指令:
SPIWrite 002,5C // Setup Tx Digital Filters/ Channels
SPIWrite 003,5C // Setup Rx Digital Filters/ Channels
SPIWrite 004,03 // Select Rx input pin(A,B,C)/ Tx out pin (A,B)
SPIWrite 00A,33 // Set BBPLL post divide rate
5、设置发射接收链路 0x002:包括使能发射通道,THB3/THB2/THB1/TX FIR等 0x003:包括使能发射通道,RHB3/RHB2/RHB1/RX FIR等
6、选择输入输出端口(TX:A or B ,RX A,B,C)
0x004
发射信号链路有两个RF输出端口(A和B),( 两个有区别么?)
接收信号链路由三个内部LNA(低噪放),而且,接收器能够有balanced和unbalanced 运行模式。
这几个端口是不是是不是有频率选择的用处,有待确认
接收的B/C通道如果用于3GHz以上性能会下降
7、CLK_OUT使能,以及频率选择; BBPLL的分频选择生成ADC_CLK。以及DAC_CLK的时钟是否需要ADC_CLK/2,还是等于ADC_CLK
0x00A
第四段指令:
//************************************************************
// Setup the Parallel Port (Digital Data Interface)
//************************************************************
SPIWrite 010,C8 // I/O Config. Tx Swap IQ; Rx Swap IQ; Tx CH Swap, Rx CH Swap; Rx Frame Mode; 2R2T bit; Invert data bus; Invert DATA_CLK
SPIWrite 011,00 // I/O Config. Alt Word Order; -Rx1; -Rx2; -Tx1; -Tx2; Invert Rx Frame; Delay Rx Data
SPIWrite 012,10 // I/O Config. Rx=2*Tx; Swap Ports; SDR; LVDS; Half Duplex; Single Port; Full Port; Swap Bits
SPIWrite 006,00 // PPORT Rx Delay (adjusts Tco Dataclk->Data)
SPIWrite 007,0F // PPORT TX Delay (adjusts setup/hold FBCLK->Data)SPIWrite 03C,22 // CLK_OUT slew; LVDS: Rx Term; Bypass Bias R; Tx LO VCM; Bias[2:0]
SPIWrite 03D,00 // LVDS polarity invert
SPIWrite 03E,00 // LVDS polarity invert
8、接口参数,暂时只考虑LVDS
0X010
0X011
0X012
注意两个参数: RX frame pulse mode ;LVDS mode
9、设置端口延时
0x006:接收端口延迟
0x007:发射接口延迟
主要是为了满足采样的建立保持时间。
10、设置LVDS接口参数(保持关注)
0x03C
0x03D
0x03E
跟下面的设置有关
// Setup AuxDAC/AuxDAC
// Setup Control Outs
// Setup GPO
有待研究
// Setup RF PLL non-frequency-dependent registers
a、设置参数:
0x261:设置为0x00,设置Rx LO power mode,使用内部VCO;
0x2A1:设置为0x00,设置Tx LO power mode,使用内部VCO;
0x248:设置为0x0b,使能Rx VCO LDO,此寄存器必须设置为0x0b;
0x288:设置为0x0b,使能Tx VCO LDO,此寄存器必须设置为0x0b;
0x246:设置为0x02,此寄存器必须设置为0x02;
0x286:设置为0x02,此寄存器必须设置为0x02;
0x249:设置为0x8e,VCO cal length,设置Rx校准时钟长度;
0x289:设置为0x8e,VCO cal length,设置Tx校准时钟长度;
0x23B:设置为0x80,使能Rx VCO cal,设置charge pump current;
0x27B:设置为0x80,使能Tx VCO cal,设置charge pump current;
0x243:设置为0x0d,此寄存器必须设置为0x0d;
0x283:设置为0x0d,此寄存器必须设置为0x0d;
0x23D:设置为0x00,Clear Half VCO cal clock setting;
0x27D:设置为0x00,Clear Half VCO cal clock setting;
b、校准:
0x015:设置为0x04,Set Dual Synth mode bit;
0x014:设置为0x05,Set Force ALERT State bit;
0x013:设置为0x01,设置ENSM为FDD模式;
0x23D:设置为0x04,设置开始CP 校准;
延时1ms;
0x244:读取此寄存器值,判断是否校准完成(D[7]==1);
0x27D:设置为0x04,设置开始CP 校准;
延时1ms;
0x284:读取此寄存器值,判断是否校准完成(D[7]==1);
校准完成,设置校准寄存器:
0x23D:设置为0x00,停止CP 校准;
0x27D:设置为0x00,停止CP 校准。
设置接收VCO 合成器参数(ad9361_set_rx_synth.v)
此部分寄存器需要用到以下查找表,若不根据查找表来设置参数,VCO将无法锁住,其中备注的40MHz、60MHz和80MHz为参考时钟的频率,若频率大于等于某值,则按该值设置。
0x23A:设置为0x40 | SynthLUT_FDD[].VCO_Output_Level; (应该是笔误,为0x4A)
0x239:设置为0xc0 | SynthLUT_FDD[].VCO_Varactor;
0x242:设置为(SynthLUT_FDD[].VCO_Bias_Tcf << 3) | SynthLUT_FDD[].VCO_Bias_Ref;
0x238:设置为0x68,不使能Force VCO Tune;
0x245:设置为0x00,此寄存器必须设置为0x00;
0x251:设置为SynthLUT_FDD[].VCO_Varactor_Reference;
0x250:设置为0x70,此寄存器必须设置为0x70;
0x23B:设置为0x80 | SynthLUT_FDD[].Charge_Pump_Current;
0x23E:设置为(SynthLUT_FDD[].LF_C2 <<4) | SynthLUT_FDD[].LF_C1;
0x23F:设置为(SynthLUT_FDD[].LF_R1 <<4) | SynthLUT_FDD[].LF_C3;
0x240:设置为SynthLUT_FDD[].LF_R3;
struct SynthLUT {
unsigned int VCO_MHz;
unsigned char VCO_Output_Level;
unsigned char VCO_Varactor;
unsigned char VCO_Bias_Ref;
unsigned char VCO_Bias_Tcf;
unsigned char VCO_Cal_Offset;
unsigned char VCO_Varactor_Reference;
unsigned char Charge_Pump_Current;
unsigned char LF_C2;
unsigned char LF_C1;
unsigned char LF_R1;
unsigned char LF_C3;
unsigned char LF_R3;
};
static const struct SynthLUT SynthLUT_FDD[3][SYNTH_LUT_SIZE] = {
{
{ 12605, 10, 0, 4, 0, 15, 8, 8, 12, 3, 14, 15, 11 }, /* 40 MHz /
{ 12245, 10, 0, 4, 0, 15, 8, 9, 12, 3, 14, 15, 11 },
{ 11906, 10, 0, 4, 0, 15, 8, 9, 12, 3, 14, 15, 11 },
{ 11588, 10, 0, 4, 0, 15, 8, 10, 12, 3, 14, 15, 11 },
{ 11288, 10, 0, 4, 0, 15, 8, 11, 12, 3, 14, 15, 11 },
{ 11007, 10, 0, 4, 0, 15, 8, 11, 12, 3, 14, 15, 11 },
{ 10742, 10, 0, 4, 0, 14, 8, 12, 12, 3, 14, 15, 11 },
{ 10492, 10, 0, 5, 1, 14, 9, 13, 12, 3, 14, 15, 11 },
{ 10258, 10, 0, 5, 1, 14, 9, 13, 12, 3, 14, 15, 11 },
{ 10036, 10, 0, 5, 1, 14, 9, 14, 12, 3, 14, 15, 11 },
{ 9827, 10, 0, 5, 1, 14, 9, 15, 12, 3, 14, 15, 11 },
{ 9631, 10, 0, 5, 1, 14, 9, 15, 12, 3, 14, 15, 11 },
{ 9445, 10, 0, 5, 1, 14, 9, 16, 12, 3, 14, 15, 11 },
{ 9269, 10, 0, 5, 1, 14, 9, 17, 12, 3, 14, 15, 11 },
{ 9103, 10, 0, 5, 1, 14, 9, 17, 12, 3, 14, 15, 11 },
{ 8946, 10, 0, 5, 1, 14, 9, 18, 12, 3, 14, 15, 11 },
{ 8797, 10, 1, 6, 1, 15, 11, 13, 12, 3, 14, 15, 11 },
{ 8655, 10, 1, 6, 1, 15, 11, 14, 12, 3, 14, 15, 11 },
{ 8520, 10, 1, 6, 1, 15, 11, 14, 12, 3, 14, 15, 11 },
{ 8392, 10, 1, 6, 1, 15, 11, 15, 12, 3, 14, 15, 11 },
{ 8269, 10, 1, 6, 1, 15, 11, 15, 12, 3, 14, 15, 11 },
{ 8153, 10, 1, 6, 1, 15, 11, 16, 12, 3, 14, 15, 11 },
{ 8041, 10, 1, 6, 1, 15, 11, 16, 12, 3, 14, 15, 11 },
{ 7934, 10, 1, 6, 1, 15, 11, 17, 12, 3, 14, 15, 11 },
{ 7831, 10, 1, 6, 1, 15, 11, 17, 12, 3, 14, 15, 11 },
{ 7733, 10, 1, 6, 1, 15, 11, 17, 12, 3, 14, 15, 11 },
{ 7638, 10, 1, 6, 1, 15, 11, 18, 12, 3, 14, 15, 11 },
{ 7547, 10, 1, 6, 1, 15, 11, 18, 12, 3, 14, 15, 11 },
{ 7459, 10, 1, 6, 1, 15, 11, 19, 12, 3, 14, 15, 11 },
{ 7374, 10, 1, 7, 2, 15, 12, 19, 12, 3, 14, 15, 11 },
{ 7291, 10, 1, 7, 2, 15, 12, 20, 12, 3, 14, 15, 11 },
{ 7212, 10, 1, 7, 2, 15, 12, 20, 12, 3, 14, 15, 11 },
{ 7135, 10, 1, 7, 2, 15, 14, 21, 12, 3, 14, 15, 11 },
{ 7061, 10, 1, 7, 2, 15, 14, 21, 12, 3, 14, 15, 11 },
{ 6988, 10, 1, 7, 2, 15, 14, 22, 12, 3, 14, 15, 11 },
{ 6918, 10, 1, 7, 2, 15, 14, 22, 12, 3, 14, 15, 11 },
{ 6850, 10, 1, 7, 2, 15, 14, 23, 12, 3, 14, 15, 11 },
{ 6784, 10, 1, 7, 2, 15, 14, 23, 12, 3, 14, 15, 11 },
{ 6720, 10, 1, 7, 2, 15, 14, 24, 12, 3, 14, 15, 11 },
{ 6658, 10, 1, 7, 2, 15, 14, 24, 12, 3, 14, 15, 11 },
{ 6597, 10, 1, 7, 2, 15, 14, 25, 12, 3, 14, 15, 11 },
{ 6539, 10, 1, 7, 2, 15, 14, 25, 12, 3, 14, 15, 11 },
{ 6482, 10, 1, 7, 2, 15, 14, 26, 12, 3, 14, 15, 11 },
{ 6427, 10, 1, 7, 2, 15, 14, 26, 12, 3, 14, 15, 11 },
{ 6373, 10, 3, 7, 3, 15, 12, 17, 12, 3, 14, 15, 11 },
{ 6321, 10, 3, 7, 3, 15, 12, 17, 12, 3, 14, 15, 11 },
{ 6270, 10, 3, 7, 3, 15, 12, 17, 12, 3, 14, 15, 11 },
{ 6222, 10, 3, 7, 3, 15, 12, 18, 12, 3, 14, 15, 11 },
{ 6174, 10, 3, 7, 3, 15, 12, 18, 12, 3, 14, 15, 11 },
{ 6128, 10, 3, 7, 3, 15, 12, 18, 12, 3, 14, 15, 11 },
{ 6083, 10, 3, 7, 3, 15, 12, 18, 12, 3, 14, 15, 11 },
{ 6040, 10, 3, 7, 3, 15, 12, 19, 12, 3, 14, 15, 11 },
{ 5997, 10, 3, 7, 3, 15, 12, 19, 12, 3, 14, 15, 11 },
}, {
{ 12605, 10, 0, 4, 0, 15, 8, 10, 15, 4, 13, 15, 10 }, / 60 MHz /
{ 12245, 10, 0, 4, 0, 15, 8, 11, 15, 4, 13, 15, 10 },
{ 11906, 10, 0, 4, 0, 15, 8, 11, 15, 4, 13, 15, 10 },
{ 11588, 10, 0, 4, 0, 15, 8, 12, 15, 4, 13, 15, 10 },
{ 11288, 10, 0, 4, 0, 15, 8, 13, 15, 4, 13, 15, 10 },
{ 11007, 10, 0, 4, 0, 14, 8, 14, 15, 4, 13, 15, 10 },
{ 10742, 10, 0, 4, 0, 14, 8, 15, 15, 4, 13, 15, 10 },
{ 10492, 10, 0, 5, 1, 14, 9, 15, 15, 4, 13, 15, 10 },
{ 10258, 10, 0, 5, 1, 14, 9, 16, 15, 4, 13, 15, 10 },
{ 10036, 10, 0, 5, 1, 14, 9, 17, 15, 4, 13, 15, 10 },
{ 9827, 10, 0, 5, 1, 14, 9, 18, 15, 4, 13, 15, 10 },
{ 9631, 10, 0, 5, 1, 14, 9, 19, 15, 4, 13, 15, 10 },
{ 9445, 10, 0, 5, 1, 14, 9, 19, 15, 4, 13, 15, 10 },
{ 9269, 10, 0, 5, 1, 14, 9, 20, 15, 4, 13, 15, 10 },
{ 9103, 10, 0, 5, 1, 13, 9, 21, 15, 4, 13, 15, 10 },
{ 8946, 10, 0, 5, 1, 13, 9, 22, 15, 4, 13, 15, 10 },
{ 8797, 10, 1, 6, 1, 15, 11, 16, 15, 4, 13, 15, 10 },
{ 8655, 10, 1, 6, 1, 15, 11, 17, 15, 4, 13, 15, 10 },
{ 8520, 10, 1, 6, 1, 15, 11, 17, 15, 4, 13, 15, 10 },
{ 8392, 10, 1, 6, 1, 15, 11, 18, 15, 4, 13, 15, 10 },
{ 8269, 10, 1, 6, 1, 15, 11, 18, 15, 4, 13, 15, 10 },
{ 8153, 10, 1, 6, 1, 15, 11, 19, 15, 4, 13, 15, 10 },
{ 8041, 10, 1, 6, 1, 15, 11, 19, 15, 4, 13, 15, 10 },
{ 7934, 10, 1, 6, 1, 15, 11, 20, 15, 4, 13, 15, 10 },
{ 7831, 10, 1, 6, 1, 15, 11, 21, 15, 4, 13, 15, 10 },
{ 7733, 10, 1, 6, 1, 15, 11, 21, 15, 4, 13, 15, 10 },
{ 7638, 10, 1, 6, 1, 15, 11, 22, 15, 4, 13, 15, 10 },
{ 7547, 10, 1, 6, 1, 15, 11, 22, 15, 4, 13, 15, 10 },
{ 7459, 10, 1, 6, 1, 15, 11, 23, 15, 4, 13, 15, 10 },
{ 7374, 10, 1, 7, 2, 15, 12, 23, 15, 4, 13, 15, 10 },
{ 7291, 10, 1, 7, 2, 15, 12, 24, 15, 4, 13, 15, 10 },
{ 7212, 10, 1, 7, 2, 15, 12, 25, 15, 4, 13, 15, 10 },
{ 7135, 10, 1, 7, 2, 15, 14, 25, 15, 4, 13, 15, 10 },
{ 7061, 10, 1, 7, 2, 15, 14, 26, 15, 4, 13, 15, 10 },
{ 6988, 10, 1, 7, 2, 15, 14, 26, 15, 4, 13, 15, 10 },
{ 6918, 10, 1, 7, 2, 15, 14, 27, 15, 4, 13, 15, 10 },
{ 6850, 10, 1, 7, 2, 15, 14, 27, 15, 4, 13, 15, 10 },
{ 6784, 10, 1, 7, 2, 15, 14, 28, 15, 4, 13, 15, 10 },
{ 6720, 10, 1, 7, 2, 15, 14, 29, 15, 4, 13, 15, 10 },
{ 6658, 10, 1, 7, 2, 15, 14, 29, 15, 4, 13, 15, 10 },
{ 6597, 10, 1, 7, 2, 15, 14, 30, 15, 4, 13, 15, 10 },
{ 6539, 10, 1, 7, 2, 15, 14, 30, 15, 4, 13, 15, 10 },
{ 6482, 10, 1, 7, 2, 15, 14, 31, 15, 4, 13, 15, 10 },
{ 6427, 10, 1, 7, 2, 15, 14, 32, 15, 4, 13, 15, 10 },
{ 6373, 10, 3, 7, 3, 15, 12, 20, 15, 4, 13, 15, 10 },
{ 6321, 10, 3, 7, 3, 15, 12, 21, 15, 4, 13, 15, 10 },
{ 6270, 10, 3, 7, 3, 15, 12, 21, 15, 4, 13, 15, 10 },
{ 6222, 10, 3, 7, 3, 15, 12, 21, 15, 4, 13, 15, 10 },
{ 6174, 10, 3, 7, 3, 15, 12, 22, 15, 4, 13, 15, 10 },
{ 6128, 10, 3, 7, 3, 15, 12, 22, 15, 4, 13, 15, 10 },
{ 6083, 10, 3, 7, 3, 15, 12, 22, 15, 4, 13, 15, 10 },
{ 6040, 10, 3, 7, 3, 15, 12, 23, 15, 4, 13, 15, 10 },
{ 5997, 10, 3, 7, 3, 15, 12, 23, 15, 4, 13, 15, 10 },
}, {
{ 12605, 10, 0, 4, 0, 15, 8, 8, 13, 4, 13, 15, 9 }, / 80 MHz */
{ 12245, 10, 0, 4, 0, 15, 8, 9, 13, 4, 13, 15, 9 },
{ 11906, 10, 0, 4, 0, 15, 8, 10, 13, 4, 13, 15, 9 },
{ 11588, 10, 0, 4, 0, 15, 8, 11, 13, 4, 13, 15, 9 },
{ 11288, 10, 0, 4, 0, 15, 8, 11, 13, 4, 13, 15, 9 },
{ 11007, 10, 0, 4, 0, 14, 8, 12, 13, 4, 13, 15, 9 },
{ 10742, 10, 0, 4, 0, 14, 8, 13, 13, 4, 13, 15, 9 },
{ 10492, 10, 0, 5, 1, 14, 9, 13, 13, 4, 13, 15, 9 },
{ 10258, 10, 0, 5, 1, 14, 9, 14, 13, 4, 13, 15, 9 },
{ 10036, 10, 0, 5, 1, 14, 9, 15, 13, 4, 13, 15, 9 },
{ 9827, 10, 0, 5, 1, 14, 9, 15, 13, 4, 13, 15, 9 },
{ 9631, 10, 0, 5, 1, 13, 9, 16, 13, 4, 13, 15, 9 },
{ 9445, 10, 0, 5, 1, 13, 9, 17, 13, 4, 13, 15, 9 },
{ 9269, 10, 0, 5, 1, 13, 9, 18, 13, 4, 13, 15, 9 },
{ 9103, 10, 0, 5, 1, 13, 9, 18, 13, 4, 13, 15, 9 },
{ 8946, 10, 0, 5, 1, 13, 9, 19, 13, 4, 13, 15, 9 },
{ 8797, 10, 1, 6, 1, 15, 11, 14, 13, 4, 13, 15, 9 },
{ 8655, 10, 1, 6, 1, 15, 11, 14, 13, 4, 13, 15, 9 },
{ 8520, 10, 1, 6, 1, 15, 11, 15, 13, 4, 13, 15, 9 },
{ 8392, 10, 1, 6, 1, 15, 11, 15, 13, 4, 13, 15, 9 },
{ 8269, 10, 1, 6, 1, 15, 11, 16, 13, 4, 13, 15, 9 },
{ 8153, 10, 1, 6, 1, 15, 11, 16, 13, 4, 13, 15, 9 },
{ 8041, 10, 1, 6, 1, 15, 11, 17, 13, 4, 13, 15, 9 },
{ 7934, 10, 1, 6, 1, 15, 11, 17, 13, 4, 13, 15, 9 },
{ 7831, 10, 1, 6, 1, 15, 11, 18, 13, 4, 13, 15, 9 },
{ 7733, 10, 1, 6, 1, 15, 11, 18, 13, 4, 13, 15, 9 },
{ 7638, 10, 1, 6, 1, 15, 11, 19, 13, 4, 13, 15, 9 },
{ 7547, 10, 1, 6, 1, 15, 11, 19, 13, 4, 13, 15, 9 },
{ 7459, 10, 1, 6, 1, 15, 11, 20, 13, 4, 13, 15, 9 },
{ 7374, 10, 1, 7, 2, 15, 12, 20, 13, 4, 13, 15, 9 },
{ 7291, 10, 1, 7, 2, 15, 12, 21, 13, 4, 13, 15, 9 },
{ 7212, 10, 1, 7, 2, 15, 12, 21, 13, 4, 13, 15, 9 },
{ 7135, 10, 1, 7, 2, 15, 14, 22, 13, 4, 13, 15, 9 },
{ 7061, 10, 1, 7, 2, 15, 14, 22, 13, 4, 13, 15, 9 },
{ 6988, 10, 1, 7, 2, 15, 14, 23, 13, 4, 13, 15, 9 },
{ 6918, 10, 1, 7, 2, 15, 14, 23, 13, 4, 13, 15, 9 },
{ 6850, 10, 1, 7, 2, 15, 14, 24, 13, 4, 13, 15, 9 },
{ 6784, 10, 1, 7, 2, 15, 14, 24, 13, 4, 13, 15, 9 },
{ 6720, 10, 1, 7, 2, 15, 14, 25, 13, 4, 13, 15, 9 },
{ 6658, 10, 1, 7, 2, 15, 14, 25, 13, 4, 13, 15, 9 },
{ 6597, 10, 1, 7, 2, 15, 14, 26, 13, 4, 13, 15, 9 },
{ 6539, 10, 1, 7, 2, 15, 14, 26, 13, 4, 13, 15, 9 },
{ 6482, 10, 1, 7, 2, 15, 14, 27, 13, 4, 13, 15, 9 },
{ 6427, 10, 1, 7, 2, 15, 14, 27, 13, 4, 13, 15, 9 },
{ 6373, 10, 3, 7, 3, 15, 12, 18, 13, 4, 13, 15, 9 },
{ 6321, 10, 3, 7, 3, 15, 12, 18, 13, 4, 13, 15, 9 },
{ 6270, 10, 3, 7, 3, 15, 12, 18, 13, 4, 13, 15, 9 },
{ 6222, 10, 3, 7, 3, 15, 12, 19, 13, 4, 13, 15, 9 },
{ 6174, 10, 3, 7, 3, 15, 12, 19, 13, 4, 13, 15, 9 },
{ 6128, 10, 3, 7, 3, 15, 12, 19, 13, 4, 13, 15, 9 },
{ 6083, 10, 3, 7, 3, 15, 12, 19, 13, 4, 13, 15, 9 },
{ 6040, 10, 3, 7, 3, 15, 12, 20, 13, 4, 13, 15, 9 },
{ 5997, 10, 3, 7, 3, 15, 12, 20, 13, 4, 13, 15, 9 },
} };
11、设置发送VCO 合成器参数(ad9361_set_tx_synth.v)
此部分寄存器设置同10。
0x27A:设置为0x40 | SynthLUT_FDD[].VCO_Output_Level;
0x279:设置为0xc0 | SynthLUT_FDD[].VCO_Varactor;
0x282:设置为(SynthLUT_FDD[].VCO_Bias_Tcf << 3) | SynthLUT_FDD[].VCO_Bias_Ref;
0x278:设置为0x68,不使能Force VCO Tune;
0x285:设置为0x00,此寄存器必须设置为0x00;
0x291:设置为SynthLUT_FDD[].VCO_Varactor_Reference;
0x290:设置为0x70,此寄存器必须设置为0x70;
0x27B:设置为0x80 | SynthLUT_FDD[].Charge_Pump_Current;
0x27E:设置为(SynthLUT_FDD[].LF_C2 <<4) | SynthLUT_FDD[].LF_C1;
0x27F:设置为(SynthLUT_FDD[].LF_R1 <<4) | SynthLUT_FDD[].LF_C3;
0x280:设置为SynthLUT_FDD[].LF_R3;
12、设置接收/发送VCO频率参数(ad9361_set_trx_clk_rate.v)
接收/发送VCO必须工作在612GHz,其通过分频器(2的幂次分频:126)得到本振信号(lo)。其由参考信号(RxREF/TxREF)倍频得到,通过设置VCO与参考信号(RxREF/TxREF)的频率比值参数,可产生VCO信号。
先计算VCO频率,根据输入的接收/发送lo频率,通过迭代X2的方式,得到一个频率范围为6.0GHz~12.0GHz的VCO频率frfpll,其中迭代X2的次数为分频器控制字vco_divider;
接着根据得到的VCO的频率值frfpll,计算频率控制字。其中:
a、配置Rx频率控制字:
0x233:写频率控制字小数部分[7:0];
0x234:写频率控制字小数部分[15:8];
0x235:写频率控制字小数部分[23:16];
0x232:写频率控制字整数部分[10:8];
0x231:写频率控制字整数部分[7:0];
0x005:写分频器控制字vco_divider,(tx_vco_divider << 4) | rx_vco_divider;
b、配置Rx频率控制字:
0x273:写频率控制字小数部分[7:0];
0x274:写频率控制字小数部分[15:8];
0x275:写频率控制字小数部分[23:16];
0x272:写频率控制字整数部分[10:8];
0x271:写频率控制字整数部分[7:0];
0x005:写分频器控制字vco_divider,(tx_vco_divider << 4) | rx_vco_divider;
c、校准:
延时1ms;
0x247:读取此寄存器值,判断是否校准完成(D[1]==1);
延时1ms;
0x287:读取此寄存器值,判断是否校准完成(D[1]==1);
13、设置混频器增益表(ad9361_set_mixer_gm_table.v)
//Mixer GM Sub-table系数
static const unsigned char gm_st_gain[16] ={
0x78, 0x74, 0x70, 0x6C, 0x68, 0x64, 0x60, 0x5C,0x58, 0x54, 0x50, 0x4C, 0x48, 0x30, 0x18, 0x00};
static const unsigned char gm_st_ctrl[16] ={
0x00, 0x0D, 0x15, 0x1B, 0x21, 0x25, 0x29, 0x2C,0x2F, 0x31, 0x33, 0x34, 0x35, 0x3A, 0x3D, 0x3E};
0x13f:设置为0x02,写时钟使能,开始写表;
以下循环16次:
{
0x138:设置表地址,从0x0f开始,逐次递减;
0x139:设置增益系数;
0x13a:设置bias,为0x00;
0x13b:设置控制系数;
0x13f:设置为0x06,寄存器写有效;
0x13c:连续2次设置为0x00,用于延时2us;
}
0x13f:设置为0x00,写时钟不使能,写表结束;
14、设置AGC增益表(ad9361_set_rx_gain_table.v)
/* Rx Gain Tables /
#define FULL_TABLE_SIZE 90
#define RXGAIN_TBLS_END 3
static const unsigned char full_gain_table[RXGAIN_TBLS_END][FULL_TABLE_SIZE][3] =
{ { / 800 MHz /
{ 0x00, 0x00, 0x20 }, { 0x00, 0x00, 0x00 }, { 0x00, 0x00, 0x00 },
{ 0x00, 0x01, 0x00 }, { 0x00, 0x02, 0x00 }, { 0x00, 0x03, 0x00 },
{ 0x00, 0x04, 0x00 }, { 0x00, 0x05, 0x00 }, { 0x01, 0x03, 0x20 },
{ 0x01, 0x04, 0x00 }, { 0x01, 0x05, 0x00 }, { 0x01, 0x06, 0x00 },
{ 0x01, 0x07, 0x00 }, { 0x01, 0x08, 0x00 }, { 0x01, 0x09, 0x00 },
{ 0x01, 0x0A, 0x00 }, { 0x01, 0x0B, 0x00 }, { 0x01, 0x0C, 0x00 },
{ 0x01, 0x0D, 0x00 }, { 0x01, 0x0E, 0x00 }, { 0x02, 0x09, 0x20 },
{ 0x02, 0x0A, 0x00 }, { 0x02, 0x0B, 0x00 }, { 0x02, 0x0C, 0x00 },
{ 0x02, 0x0D, 0x00 }, { 0x02, 0x0E, 0x00 }, { 0x02, 0x0F, 0x00 },
{ 0x02, 0x10, 0x00 }, { 0x02, 0x2B, 0x20 }, { 0x02, 0x2C, 0x00 },
{ 0x04, 0x28, 0x20 }, { 0x04, 0x29, 0x00 }, { 0x04, 0x2A, 0x00 },
{ 0x04, 0x2B, 0x00 }, { 0x24, 0x20, 0x20 }, { 0x24, 0x21, 0x00 },
{ 0x44, 0x20, 0x20 }, { 0x44, 0x21, 0x00 }, { 0x44, 0x22, 0x00 },
{ 0x44, 0x23, 0x00 }, { 0x44, 0x24, 0x00 }, { 0x44, 0x25, 0x00 },
{ 0x44, 0x26, 0x00 }, { 0x44, 0x27, 0x00 }, { 0x44, 0x28, 0x00 },
{ 0x44, 0x29, 0x00 }, { 0x44, 0x2A, 0x00 }, { 0x44, 0x2B, 0x00 },
{ 0x44, 0x2C, 0x00 }, { 0x44, 0x2D, 0x00 }, { 0x44, 0x2E, 0x00 },
{ 0x44, 0x2F, 0x00 }, { 0x44, 0x30, 0x00 }, { 0x44, 0x31, 0x00 },
{ 0x44, 0x32, 0x00 }, { 0x64, 0x2E, 0x20 }, { 0x64, 0x2F, 0x00 },
{ 0x64, 0x30, 0x00 }, { 0x64, 0x31, 0x00 }, { 0x64, 0x32, 0x00 },
{ 0x64, 0x33, 0x00 }, { 0x64, 0x34, 0x00 }, { 0x64, 0x35, 0x00 },
{ 0x64, 0x36, 0x00 }, { 0x64, 0x37, 0x00 }, { 0x64, 0x38, 0x00 },
{ 0x65, 0x38, 0x20 }, { 0x66, 0x38, 0x20 }, { 0x67, 0x38, 0x20 },
{ 0x68, 0x38, 0x20 }, { 0x69, 0x38, 0x20 }, { 0x6A, 0x38, 0x20 },
{ 0x6B, 0x38, 0x20 }, { 0x6C, 0x38, 0x20 }, { 0x6D, 0x38, 0x20 },
{ 0x6E, 0x38, 0x20 }, { 0x6F, 0x38, 0x20 }, { 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00 }, { 0x00, 0x00, 0x00 }, { 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00 }, { 0x00, 0x00, 0x00 }, { 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00 }, { 0x00, 0x00, 0x00 }, { 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00 }, { 0x00, 0x00, 0x00 }, { 0x00, 0x00, 0x00 }
}, { / 2300 MHz /
{ 0x00, 0x00, 0x20 }, { 0x00, 0x00, 0x00 }, { 0x00, 0x00, 0x00 },
{ 0x00, 0x01, 0x00 }, { 0x00, 0x02, 0x00 }, { 0x00, 0x03, 0x00 },
{ 0x00, 0x04, 0x00 }, { 0x00, 0x05, 0x00 }, { 0x01, 0x03, 0x20 },
{ 0x01, 0x04, 0x00 }, { 0x01, 0x05, 0x00 }, { 0x01, 0x06, 0x00 },
{ 0x01, 0x07, 0x00 }, { 0x01, 0x08, 0x00 }, { 0x01, 0x09, 0x00 },
{ 0x01, 0x0A, 0x00 }, { 0x01, 0x0B, 0x00 }, { 0x01, 0x0C, 0x00 },
{ 0x01, 0x0D, 0x00 }, { 0x01, 0x0E, 0x00 }, { 0x02, 0x09, 0x20 },
{ 0x02, 0x0A, 0x00 }, { 0x02, 0x0B, 0x00 }, { 0x02, 0x0C, 0x00 },
{ 0x02, 0x0D, 0x00 }, { 0x02, 0x0E, 0x00 }, { 0x02, 0x0F, 0x00 },
{ 0x02, 0x10, 0x00 }, { 0x02, 0x2B, 0x20 }, { 0x02, 0x2C, 0x00 },
{ 0x04, 0x27, 0x20 }, { 0x04, 0x28, 0x00 }, { 0x04, 0x29, 0x00 },
{ 0x04, 0x2A, 0x00 }, { 0x04, 0x2B, 0x00 }, { 0x24, 0x21, 0x20 },
{ 0x24, 0x22, 0x00 }, { 0x44, 0x20, 0x20 }, { 0x44, 0x21, 0x00 },
{ 0x44, 0x22, 0x00 }, { 0x44, 0x23, 0x00 }, { 0x44, 0x24, 0x00 },
{ 0x44, 0x25, 0x00 }, { 0x44, 0x26, 0x00 }, { 0x44, 0x27, 0x00 },
{ 0x44, 0x28, 0x00 }, { 0x44, 0x29, 0x00 }, { 0x44, 0x2A, 0x00 },
{ 0x44, 0x2B, 0x00 }, { 0x44, 0x2C, 0x00 }, { 0x44, 0x2D, 0x00 },
{ 0x44, 0x2E, 0x00 }, { 0x44, 0x2F, 0x00 }, { 0x44, 0x30, 0x00 },
{ 0x44, 0x31, 0x00 }, { 0x64, 0x2E, 0x20 }, { 0x64, 0x2F, 0x00 },
{ 0x64, 0x30, 0x00 }, { 0x64, 0x31, 0x00 }, { 0x64, 0x32, 0x00 },
{ 0x64, 0x33, 0x00 }, { 0x64, 0x34, 0x00 }, { 0x64, 0x35, 0x00 },
{ 0x64, 0x36, 0x00 }, { 0x64, 0x37, 0x00 }, { 0x64, 0x38, 0x00 },
{ 0x65, 0x38, 0x20 }, { 0x66, 0x38, 0x20 }, { 0x67, 0x38, 0x20 },
{ 0x68, 0x38, 0x20 }, { 0x69, 0x38, 0x20 }, { 0x6A, 0x38, 0x20 },
{ 0x6B, 0x38, 0x20 }, { 0x6C, 0x38, 0x20 }, { 0x6D, 0x38, 0x20 },
{ 0x6E, 0x38, 0x20 }, { 0x6F, 0x38, 0x20 }, { 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00 }, { 0x00, 0x00, 0x00 }, { 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00 }, { 0x00, 0x00, 0x00 }, { 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00 }, { 0x00, 0x00, 0x00 }, { 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00 }, { 0x00, 0x00, 0x00 }, { 0x00, 0x00, 0x00 }
}, { / 5500 MHz */
{ 0x00, 0x00, 0x20 }, { 0x00, 0x00, 0x00 }, { 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00 }, { 0x00, 0x00, 0x00 }, { 0x00, 0x01, 0x00 },
{ 0x00, 0x02, 0x00 }, { 0x00, 0x03, 0x00 }, { 0x01, 0x01, 0x20 },
{ 0x01, 0x02, 0x00 }, { 0x01, 0x03, 0x00 }, { 0x01, 0x04, 0x20 },
{ 0x01, 0x05, 0x00 }, { 0x01, 0x06, 0x00 }, { 0x01, 0x07, 0x00 },
{ 0x01, 0x08, 0x00 }, { 0x01, 0x09, 0x00 }, { 0x01, 0x0A, 0x00 },
{ 0x01, 0x0B, 0x00 }, { 0x01, 0x0C, 0x00 }, { 0x02, 0x08, 0x20 },
{ 0x02, 0x09, 0x00 }, { 0x02, 0x0A, 0x00 }, { 0x02, 0x0B, 0x20 },
{ 0x02, 0x0C, 0x00 }, { 0x02, 0x0D, 0x00 }, { 0x02, 0x0E, 0x00 },
{ 0x02, 0x0F, 0x00 }, { 0x02, 0x2A, 0x20 }, { 0x02, 0x2B, 0x00 },
{ 0x04, 0x27, 0x20 }, { 0x04, 0x28, 0x00 }, { 0x04, 0x29, 0x00 },
{ 0x04, 0x2A, 0x00 }, { 0x04, 0x2B, 0x00 }, { 0x04, 0x2C, 0x00 },
{ 0x04, 0x2D, 0x00 }, { 0x24, 0x20, 0x20 }, { 0x24, 0x21, 0x00 },
{ 0x24, 0x22, 0x00 }, { 0x44, 0x20, 0x20 }, { 0x44, 0x21, 0x00 },
{ 0x44, 0x22, 0x00 }, { 0x44, 0x23, 0x00 }, { 0x44, 0x24, 0x00 },
{ 0x44, 0x25, 0x00 }, { 0x44, 0x26, 0x00 }, { 0x44, 0x27, 0x00 },
{ 0x44, 0x28, 0x00 }, { 0x44, 0x29, 0x00 }, { 0x44, 0x2A, 0x00 },
{ 0x44, 0x2B, 0x00 }, { 0x44, 0x2C, 0x00 }, { 0x44, 0x2D, 0x00 },
{ 0x44, 0x2E, 0x00 }, { 0x64, 0x2E, 0x20 }, { 0x64, 0x2F, 0x00 },
{ 0x64, 0x30, 0x00 }, { 0x64, 0x31, 0x00 }, { 0x64, 0x32, 0x00 },
{ 0x64, 0x33, 0x00 }, { 0x64, 0x34, 0x00 }, { 0x64, 0x35, 0x00 },
{ 0x64, 0x36, 0x00 }, { 0x64, 0x37, 0x00 }, { 0x64, 0x38, 0x00 },
{ 0x65, 0x38, 0x20 }, { 0x66, 0x38, 0x20 }, { 0x67, 0x38, 0x20 },
{ 0x68, 0x38, 0x20 }, { 0x69, 0x38, 0x20 }, { 0x6A, 0x38, 0x20 },
{ 0x6B, 0x38, 0x20 }, { 0x6C, 0x38, 0x20 }, { 0x6D, 0x38, 0x20 },
{ 0x6E, 0x38, 0x20 }, { 0x6F, 0x38, 0x20 }, { 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00 }, { 0x00, 0x00, 0x00 }, { 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00 }, { 0x00, 0x00, 0x00 }, { 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00 }, { 0x00, 0x00, 0x00 }, { 0x00, 0x00, 0x00 },
{ 0x00, 0x00, 0x00 }, { 0x00, 0x00, 0x00 }, { 0x00, 0x00, 0x00 }
} };
0x137:设置为0x1a,写时钟使能,开始写表;
以下循环90次:
{
0x131:设置增益系数0;
0x132:设置增益系数1;
0x133:设置增益系数1;
0x137:设置为0x1e,寄存器写有效;
0x134:连续2次设置为0x00,用于延时2us;
}
0x137:设置为0x00,写时钟不使能,写表结束;
15、设置Rx Manual增益(ad9361_set_rx_manu_gain.v)
0x0fa:Gain Control Mode Select,设置为0xe0;
0x0fb:Table, Digital Gain, Man Gain Ctrl,设置为0x08;
0x0fc:Incr Step Size, ADC Overrange Size,设置为0x23;
0x0fd:Max Full/LMT Gain Table Index,设置为0x4c;
0x0fe:Decr Step Size, Peak Overload Time,设置为0x44;
0x100:Max Digital Gain,设置为0x6f;
0x104:ADC Small Overload Threshold,设置为0x2f;
0x105:ADC Large Overload Threshold,设置为0x3a;
0x107:Small LMT Overload Threshold,设置为0x2b;
0x108:Large LMT Overload Threshold,设置为0x2b;
0x109:Rx1 Full/LMT Gain Index,设置为0x4c;
0x10a:Rx1 LPF Gain Index,设置为0x58;
0x10b:Rx1 Digital Gain Index,设置为0x00;
0x10c:Rx2 Full/LMT Gain Index,设置为0x4c;
0x10d:Rx2 LPF Gain Index,设置为0x18;
0x10e:Rx2 Digital Gain Index,设置为0x00;
0x114:Low Power Threshold,设置为0x30;
0x11a:Initial LMT Gain Limit,设置为0x27;
0x081:Tx Symbol Gain Control,设置为0x00;
16、设置接收基带滤波器参数(ad9361_set_rx_bb_filter_tune.v)
0x1fd:RX Freq Corner (MHz),设置为0x04;此处设置为BW:4.5MHz
0x1fc:RX Freq Corner (KHz),设置为0x40;
0x1f8:Rx BBF Tune Divider[7:0],设置为0x12;
0x1f8:Rx BBF Tune Divider[8],设置为0x1e;
0x1d5:Set Rx Mix LO CM,设置为0x3f;
0x1c0:Set GM common mode,设置为0x03;
0x1e2:Enable Rx1 Filter Tuner,设置为0x02;
0x1e3:Enable Rx2 Filter Tuner,设置为0x02;
0x016:Start RX Filter Tune,设置为0x80;
延时1ms;
0x016:读取此寄存器值,判断是否校准完成(D[7]==0);
0x1e2:disable Rx1 Filter Tuner,设置为0x03;
0x1e3:disable Rx2 Filter Tuner,设置为0x03;
17、设置发送基带滤波器参数(ad9361_set_tx_filter_tune.v)
0x0d6:Tx BBF Tune Divider[7:0],设置为0x12;
0x0d7:Tx BBF Tune Divider[8],设置为0x1e;
0x0ca:Enable Tx Filter Tuner,设置为0x22;
0x016:Start TX Filter Tune,设置为0x40;
延时1ms;
0x016:读取此寄存器值,判断是否校准完成(D[6]==0);
0x0ca:disable Tx Filter Tuner,设置为0x26;
18、设置RX tia参数(ad9361_rx_tia_setup.v)
0x1eb:读取此寄存器;
0x1ec:读取此寄存器;
0x1e6:读取此寄存器;
0x1db:Set TIA selcc[2:0],设置为0x60;
0x1dd:Set RX TIA1 C MSB[6:0],设置为0x0a;
0x1df:Set RX TIA2 C MSB[6:0],设置为0x0a;
0x1dc:Set RX TIA1 C LSB[5:0],设置为0x40;
0x1de:Set RX TIA2 C LSB[5:0],设置为0x40;
19、设置发送第二级滤波器参数(ad9361_set_tx_filter_tune.v)
0x0d2:TX Secondary Filter PDF Cap cal[5:0],设置为0x3b;
0x0d1:TX Secondary Filter PDF Res cal[3:0],设置为0x0c;
0x0d0:Pdampbias,设置为0x59;
20、设置ADC 模拟滤波器参数(ad9361_adc_analog_filter.v)
0x1eb:读取此寄存器;
0x1ec:读取此寄存器;
0x1e6:读取此寄存器;
写滤波器参数,从0x200地址开始,每次递增1,循环40次。
static const unsigned char adc_rx_analog_filter[40] ={
0x00, 0x00, 0x00, 0x24, 0x24, 0x00, 0x00, 0x7c,
0x53, 0x3c, 0x4b, 0x34, 0x4e, 0x32, 0x00, 0x7f,
0x7f, 0x7f, 0x49, 0x49, 0x49, 0x4c, 0x4c, 0x4c,
0x2e, 0x98, 0x1b, 0x13, 0x98, 0x1b, 0x13, 0x98,
0x1b, 0x27, 0x27, 0x40, 0x40, 0x2c, 0x00, 0x00
};
21、设置BB_DC_OFFSET校准(ad9361_bb_dc_offset_cal.v)
0x193:设置为0x3f,此寄存器必须设置为0x3f;
0x190:Set BBDC tracking shift M value, only applies when BB DC tracking enabled,设置为0x0f,
0x194:BB DC Attenuation Cal setting,设置为0x01;
0x016:Start BB DC offset cal,设置为0x01;
延时1ms;
0x016:读取此寄存器值,判断是否校准完成(D[0]==0);
22、设置RF_DC_OFFSET校准(ad9361_rf_dc_offset_cal.v)
0x185:Set RF DC offset Wait Count,设置为0x20;
0x186:Set RF DC Offset Count[7:0],设置为0x32;
0x187:设置为0x24;
0x18b:设置为0x83;
0x188:设置为0x05;
0x189:设置为0x30;
0x016:Start RF DC offset cal,设置为0x02;
延时1ms;
0x016:读取此寄存器值,判断是否校准完成(D[1]==0);
23、设置Tx Quadrature校准(ad9361_tx_quad_cal.v)
0x0a3:读取此寄存器;
0x0a0:Set TxQuadcal NCO frequency,设置为0x15;
0x0a3:Set TxQuadcal NCO frequency(Only update bits [7:6]),设置为0x00;
0x0a1:Tx Quad Cal Configuration, Phase and Gain Cal Enable,设置为0x7b;
0x0a9:设置为0xff,此寄存器必须设置为0xff;
0x0a2:设置为0x7f,此寄存器必须设置为0x7f;
0x0a5:Set Tx Quad Cal Magnitude Threshhold,设置为0x01;
0x0a6:Set Tx Quad Cal Magnitude Threshhold,设置为0x01;
0x0aa:Set Tx Quad Cal Gain Table index,设置为0x25;
0x0a4:设置为0xf0,此寄存器必须设置为0xf0;
0x0ae:Set Tx Quad Cal LPF Gain index incase Split table mode used,设置为0x00;
0x169:Disable Rx Quadrature Calibration before Running Tx Quadrature Calibration,
设置为0xc0;
0x016:Start RF DC offset cal,设置为0x10;
延时1ms;
0x016:读取此寄存器值,判断是否校准完成(D[4]==0);
0x16a:设置为0x75,此寄存器必须设置为0x75;
0x16b:设置为0x95,此寄存器必须设置为0x95;
0x169:Enable Rx Quadrature Calibration Tracking,设置为0xcf;
0x18b:Enable BB and RF DC Tracking Calibrations,设置为0xad;
0x012:Cals done, Set PPORT Config,设置为0x10;
0x013:Set ENSM FDD/TDD bit,设置为0x01;
0x015:Set Dual Synth Mode, FDD External Control bits properly,设置为0x04;
24、设置发送衰减系数(ad9361_set_tx_atten.v)
0x077:设置为0x40;
0x07c:设置为0x00;
0x073:Tx1 Atten[7:0],0.25 dB/LSB. Range is 0 to 359 (d);
0x074:Tx1 Atten[8];
0x075:Tx2 Atten[7:0],0.25 dB/LSB. Range is 0 to 359 (d);
0x076:Tx2 Atten[8];
25、设置RSSI and Power Measurement Duration(ad9361_setup_rssi.v)
0x150:RSSI Measurement Duration 0, 1,设置为0x0e;
0x151:RSSI Measurement Duration 2, 3,设置为0x00;
0x152:RSSI Weighted Multiplier 0,设置为0xff;
0x153:RSSI Weighted Multiplier 1,设置为0x00;
0x154:RSSI Weighted Multiplier 2,设置为0x00;
0x155:RSSI Weighted Multiplier 3,设置为0x00;
0x156:RSSI Delay,设置为0x00;
0x157:RSSI Wait,设置为0x00;
0x158:RSSI Mode Select,设置为0x0d;
0x15c:Power Measurement Duration,设置为0x67;
26、设置开始工作(ad9361_start_work.v)
0x015:设置为0x84,设置TXNRX,ENABLE控制芯片ENSM状态;
0x014:设置为0x20,设置芯片ENSM进入FDD状态。
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