本文发布于www.hackster.io，由东京理工大学的计算机学院开发，专用于教学与加速用(苏老师也一直认为这是RISC-V当前的主要方向)。

目前市场上开源的RISC-V内核已经很多，但很少有公开的RISC-V计算系统是非常轻型且能跑Linux系统的。

这一款RISC-V内核就可以运行在FPGA上，用Verilog编写的，需要很少硬件的资源就能跑起来，所以可以运行在一个低成本的FPGA上。

来看一下详细的技术介绍：

占用很少的FPGA资源

The resulting design, dubbed RVSoC, implements the 32-bit RV32IMAC instruction set architecture and offers a 12-stage pipeline with a memory management unit (MMU) - not strictly required for booting Linux, given the kernel's support for manual memory mapping in the event of no hardware MMU being available, but definitely a nice-to-have for all but the most basic of possible uses. Despite this, the design comes in at a mere 5,000 lines of Verilog HDL.

"We are planning to release the RTL code of the designed RVSoC as an open and royalty free RTL design," the team pledges. "Because RVSoC is a computer system that supports Linux and uses a small amount of hardware resources, it can be applied to various purposes. A feature of RISC-V is that it has a room for the extended instructions by computer system developers. The ability of extension can be the basic requirement for application-specific accelerators and it enables to implement more specialised instruction sets.

性能相当于i386和i486之间的处理器

"The resource-saving of RVSoC can be suitable for the implementation of various accelerators and special processor cores by adding unique instructions, and the development of related software.The number of lines in Verilog HDL code of RVSoC is about 5,000, and it is relatively easy to understand the entire implementation of the Linux capable computer system. Therefore, it is suitable to be used as a sample computer system of the education on computer science."

关于该处理器的详细技术文章介绍，点击左下角的“阅读原文”。

要了解更多的关于RISC V在FPGA上的移植和嵌入式应用，可以参考硬禾学堂联合清华大学出版社推出的“基于FPGA与RISC-V的嵌入式系统设计”教程，本书作者为RISCV基金会发起的Soft CPU 2019年度的冠军。