Exynos4412-itop4412 uboot移植

硬件：迅为4412全能板

u-boot:2017.11/2020.04

---

cp board/samsung/origen/ board/samsung/itop4412 -r

diff --git a/itop4412/Makefile b/itop4412/Makefile
index 1add9fe..9697620 100644
--- a/itop4412/Makefile
+++ b/itop4412/Makefile
@@ -8,7 +8,7 @@ ifdef CONFIG_SPL_BUILD# necessary to create built-in.oobj- := __dummy__.o-hostprogs-y := tools/mkorigenspl
+hostprogs-y := tools/mkitop4412splalways := $(hostprogs-y)# omit -O2 option to suppress
@@ -16,7 +16,7 @@ always := $(hostprogs-y)## TODO:# Fix the root cause in tools/mkitop4412spl.c and delete the following work-around
-$(obj)/tools/mkorigenspl: HOSTCFLAGS:=$(filter-out -O2,$(HOSTCFLAGS))
+$(obj)/tools/mkitop4412spl: HOSTCFLAGS:=$(filter-out -O2,$(HOSTCFLAGS))else
-obj-y  += origen.o
+obj-y  += itop4412.oendif

diff --git a/itop4412/Kconfig b/itop4412/Kconfig
index 63e3efe..8dfef9a 100644
--- a/itop4412/Kconfig
+++ b/itop4412/Kconfig
@@ -1,12 +1,12 @@
-if TARGET_ORIGEN
+if TARGET_ITOP4412config SYS_BOARD
-       default "origen"
+       default "itop4412"config SYS_VENDORdefault "samsung"config SYS_CONFIG_NAME
-       default "origen"
+       default "itop4412"endif

diff --git a/itop4412/MAINTAINERS b/itop4412/MAINTAINERS
index 8bf373e..ac7df9d 100644
--- a/itop4412/MAINTAINERS
+++ b/itop4412/MAINTAINERS
@@ -1,6 +1,6 @@
-ORIGEN BOARD
-M:     Chander Kashyap <k.chander@samsung.com>
+ITOP4412 BOARD
+M:      zwq <xx@xx>S:     Maintained
-F:     board/samsung/origen/
-F:     include/configs/origen.h
-F:     configs/origen_defconfig
+F:     board/samsung/itop4412/
+F:     include/configs/itop4412.h
+F:     configs/itop4412_defconfig

diff --git a/itop4412/tools/mkitop4412spl.c b/itop4412/tools/mkitop4412spl.c
index 7b5d93b..c174192 100644
--- a/itop4412/tools/mkitop4412spl.c
+++ b/itop4412/tools/mkitop4412spl.c
@@ -13,8 +13,8 @@#include <sys/stat.h>#define BUFSIZE                        (16*1024)
-#define IMG_SIZE               (16*1024)
-#define SPL_HEADER_SIZE                16
+#define IMG_SIZE               (14*1024)//(16*1024)
+#define SPL_HEADER_SIZE                0//16#define FILE_PERM              (S_IRUSR | S_IWUSR | S_IRGRP \| S_IWGRP | S_IROTH | S_IWOTH)#define SPL_HEADER             "S5PC210 HEADER  "
@@ -79,7 +79,7 @@ int main(int argc, char **argv)exit(EXIT_FAILURE);}
-
+#if 0for (i = 0; i < IMG_SIZE - SPL_HEADER_SIZE; i++)checksum += buffer[i+16];@@ -88,7 +88,11 @@ int main(int argc, char **argv)for (i = 1; i < SPL_HEADER_SIZE; i++)buffer[i] ^= buffer[i-1];
+#endif
+       for (i = 0; i < IMG_SIZE - 4; i++)
+               checksum += (unsigned char)buffer[i];+       *(unsigned int *)&buffer[i] = checksum;if (write(ofd, buffer, BUFSIZE) != BUFSIZE) {fprintf(stderr, "%s: Can't write %s: %s\n",argv[0], argv[2], strerror(errno));arch/arm/mach-exynos/Kconfig+config TARGET_ITOP4412
+    bool "Exynos4412 iTop-4412 board"
+    select SUPPORT_SPL+source "board/samsung/itop4412/Kconfig"

diff --git a/itop4412/tools/mkitop4412spl.c b/itop4412/tools/mkitop4412spl.c
index 7b5d93b..c174192 100644
--- a/itop4412/tools/mkitop4412spl.c
+++ b/itop4412/tools/mkitop4412spl.c
@@ -13,8 +13,8 @@#include <sys/stat.h>#define BUFSIZE                        (16*1024)
-#define IMG_SIZE               (16*1024)
-#define SPL_HEADER_SIZE                16
+#define IMG_SIZE               (14*1024)//(16*1024)
+#define SPL_HEADER_SIZE                0//16#define FILE_PERM              (S_IRUSR | S_IWUSR | S_IRGRP \| S_IWGRP | S_IROTH | S_IWOTH)#define SPL_HEADER             "S5PC210 HEADER  "
@@ -79,7 +79,7 @@ int main(int argc, char **argv)exit(EXIT_FAILURE);}
-
+#if 0for (i = 0; i < IMG_SIZE - SPL_HEADER_SIZE; i++)checksum += buffer[i+16];@@ -88,7 +88,11 @@ int main(int argc, char **argv)for (i = 1; i < SPL_HEADER_SIZE; i++)buffer[i] ^= buffer[i-1];
+#endif
+       for (i = 0; i < IMG_SIZE - 4; i++)
+               checksum += (unsigned char)buffer[i];+       *(unsigned int *)&buffer[i] = checksum;if (write(ofd, buffer, BUFSIZE) != BUFSIZE) {fprintf(stderr, "%s: Can't write %s: %s\n",argv[0], argv[2], strerror(errno));

arch/arm/mach-exynos/Kconfig
```
+config TARGET_ITOP4412
+    bool "Exynos4412 iTop-4412 board"
+    select SUPPORT_SPL+source "board/samsung/itop4412/Kconfig"

最顶层Makefile

CROSS_COMPILE ?=/etc/local/arm/gcc-arm-none-eabi-10-2020-q4-major/bin/arm-none-eabi-

configs/itop4412_defconfig

#
# Automatically generated file; DO NOT EDIT.
# U-Boot 2020.07 Configuration
#
CONFIG_CREATE_ARCH_SYMLINK=y
# CONFIG_ARC is not set
CONFIG_ARM=y
# CONFIG_M68K is not set
# CONFIG_MICROBLAZE is not set
# CONFIG_MIPS is not set
# CONFIG_NDS32 is not set
# CONFIG_NIOS2 is not set
# CONFIG_PPC is not set
# CONFIG_RISCV is not set
# CONFIG_SANDBOX is not set
# CONFIG_SH is not set
# CONFIG_X86 is not set
# CONFIG_XTENSA is not set
CONFIG_SYS_ARCH="arm"
CONFIG_SYS_CPU="armv7"
CONFIG_SYS_SOC="exynos"
CONFIG_SYS_VENDOR="samsung"
CONFIG_SYS_BOARD="zwq4412"
CONFIG_SYS_CONFIG_NAME="zwq4412"
# CONFIG_SYS_ICACHE_OFF is not set
# CONFIG_SPL_SYS_ICACHE_OFF is not set
# CONFIG_SYS_DCACHE_OFF is not set
# CONFIG_SPL_SYS_DCACHE_OFF is not set#
# ARM architecture
#
# CONFIG_GIC_V3_ITS is not set
CONFIG_HAS_VBAR=y
CONFIG_HAS_THUMB2=y
CONFIG_ARM_ASM_UNIFIED=y
CONFIG_SYS_ARM_CACHE_CP15=y
CONFIG_SYS_ARM_MMU=y
# CONFIG_SYS_ARM_MPU is not set
CONFIG_CPU_V7A=y
CONFIG_SYS_ARM_ARCH=7
CONFIG_SYS_CACHE_SHIFT_6=y
CONFIG_SYS_CACHELINE_SIZE=64
CONFIG_SYS_ARM_CACHE_WRITEBACK=y
# CONFIG_SYS_ARM_CACHE_WRITETHROUGH is not set
# CONFIG_SYS_ARM_CACHE_WRITEALLOC is not set
CONFIG_ARCH_CPU_INIT=y
# CONFIG_SYS_ARCH_TIMER is not set
# CONFIG_ARM_SMCCC is not set
# CONFIG_SEMIHOSTING is not set
CONFIG_SYS_THUMB_BUILD=y
# CONFIG_SPL_SYS_THUMB_BUILD is not set
# CONFIG_SYS_L2CACHE_OFF is not set
# CONFIG_ENABLE_ARM_SOC_BOOT0_HOOK is not set
CONFIG_USE_ARCH_MEMCPY=y
CONFIG_SPL_USE_ARCH_MEMCPY=y
CONFIG_USE_ARCH_MEMSET=y
CONFIG_SPL_USE_ARCH_MEMSET=y
# CONFIG_SET_STACK_SIZE is not set
# CONFIG_ARCH_AT91 is not set
# CONFIG_TARGET_EDB93XX is not set
# CONFIG_TARGET_ASPENITE is not set
# CONFIG_TARGET_GPLUGD is not set
# CONFIG_ARCH_DAVINCI is not set
# CONFIG_ARCH_KIRKWOOD is not set
# CONFIG_ARCH_MVEBU is not set
# CONFIG_TARGET_APF27 is not set
# CONFIG_ARCH_ORION5X is not set
# CONFIG_TARGET_SPEAR300 is not set
# CONFIG_TARGET_SPEAR310 is not set
# CONFIG_TARGET_SPEAR320 is not set
# CONFIG_TARGET_SPEAR600 is not set
# CONFIG_TARGET_STV0991 is not set
# CONFIG_TARGET_X600 is not set
# CONFIG_TARGET_FLEA3 is not set
# CONFIG_TARGET_MX35PDK is not set
# CONFIG_ARCH_BCM283X is not set
# CONFIG_ARCH_BCM63158 is not set
# CONFIG_ARCH_BCM68360 is not set
# CONFIG_ARCH_BCM6858 is not set
# CONFIG_TARGET_VEXPRESS_CA15_TC2 is not set
# CONFIG_ARCH_BCMSTB is not set
# CONFIG_TARGET_VEXPRESS_CA5X2 is not set
# CONFIG_TARGET_VEXPRESS_CA9X4 is not set
# CONFIG_TARGET_BCM23550_W1D is not set
# CONFIG_TARGET_BCM28155_AP is not set
# CONFIG_TARGET_BCMCYGNUS is not set
# CONFIG_TARGET_BCMNSP is not set
# CONFIG_TARGET_BCMNS2 is not set
CONFIG_ARCH_EXYNOS=y
# CONFIG_ARCH_S5PC1XX is not set
# CONFIG_ARCH_HIGHBANK is not set
# CONFIG_ARCH_INTEGRATOR is not set
# CONFIG_ARCH_KEYSTONE is not set
# CONFIG_ARCH_K3 is not set
# CONFIG_ARCH_OMAP2PLUS is not set
# CONFIG_ARCH_MESON is not set
# CONFIG_ARCH_MEDIATEK is not set
# CONFIG_ARCH_LPC32XX is not set
# CONFIG_ARCH_IMX8 is not set
# CONFIG_ARCH_IMX8M is not set
# CONFIG_ARCH_IMXRT is not set
# CONFIG_ARCH_MX23 is not set
# CONFIG_ARCH_MX25 is not set
# CONFIG_ARCH_MX28 is not set
# CONFIG_ARCH_MX31 is not set
# CONFIG_ARCH_MX7ULP is not set
# CONFIG_ARCH_MX7 is not set
# CONFIG_ARCH_MX6 is not set
CONFIG_SPL_LDSCRIPT="board/samsung/common/exynos-uboot-spl.lds"
# CONFIG_ARCH_MX5 is not set
# CONFIG_ARCH_OWL is not set
# CONFIG_ARCH_QEMU is not set
# CONFIG_ARCH_RMOBILE is not set
# CONFIG_TARGET_S32V234EVB is not set
# CONFIG_ARCH_SNAPDRAGON is not set
# CONFIG_ARCH_SOCFPGA is not set
# CONFIG_ARCH_SUNXI is not set
# CONFIG_ARCH_U8500 is not set
# CONFIG_ARCH_VERSAL is not set
# CONFIG_ARCH_VF610 is not set
# CONFIG_ARCH_ZYNQ is not set
# CONFIG_ARCH_ZYNQMP_R5 is not set
# CONFIG_ARCH_ZYNQMP is not set
# CONFIG_ARCH_TEGRA is not set
# CONFIG_TARGET_VEXPRESS64_AEMV8A is not set
# CONFIG_TARGET_VEXPRESS64_BASE_FVP is not set
# CONFIG_TARGET_VEXPRESS64_JUNO is not set
# CONFIG_TARGET_LS2080A_EMU is not set
# CONFIG_TARGET_LS2080A_SIMU is not set
# CONFIG_TARGET_LS1088AQDS is not set
# CONFIG_TARGET_LS2080AQDS is not set
# CONFIG_TARGET_LS2080ARDB is not set
# CONFIG_TARGET_LS2081ARDB is not set
# CONFIG_TARGET_LX2160ARDB is not set
# CONFIG_TARGET_LX2160AQDS is not set
# CONFIG_TARGET_HIKEY is not set
# CONFIG_TARGET_HIKEY960 is not set
# CONFIG_TARGET_POPLAR is not set
# CONFIG_TARGET_LS1012AQDS is not set
# CONFIG_TARGET_LS1012ARDB is not set
# CONFIG_TARGET_LS1012A2G5RDB is not set
# CONFIG_TARGET_LS1012AFRWY is not set
# CONFIG_TARGET_LS1012AFRDM is not set
# CONFIG_TARGET_LS1028AQDS is not set
# CONFIG_TARGET_LS1028ARDB is not set
# CONFIG_TARGET_LS1088ARDB is not set
# CONFIG_TARGET_LS1021AQDS is not set
# CONFIG_TARGET_LS1021ATWR is not set
# CONFIG_TARGET_LS1021ATSN is not set
# CONFIG_TARGET_LS1021AIOT is not set
# CONFIG_TARGET_LS1043AQDS is not set
# CONFIG_TARGET_LS1043ARDB is not set
# CONFIG_TARGET_LS1046AQDS is not set
# CONFIG_TARGET_LS1046ARDB is not set
# CONFIG_TARGET_LS1046AFRWY is not set
# CONFIG_TARGET_COLIBRI_PXA270 is not set
# CONFIG_ARCH_UNIPHIER is not set
# CONFIG_ARCH_STM32 is not set
# CONFIG_ARCH_STI is not set
# CONFIG_ARCH_STM32MP is not set
# CONFIG_ARCH_ROCKCHIP is not set
# CONFIG_TARGET_THUNDERX_88XX is not set
# CONFIG_ARCH_ASPEED is not set
# CONFIG_TARGET_DURIAN is not set
# CONFIG_TARGET_PRESIDIO_ASIC is not set
CONFIG_SYS_TEXT_BASE=0x43e00000
CONFIG_ARCH_EXYNOS4=y
# CONFIG_ARCH_EXYNOS5 is not set
# CONFIG_ARCH_EXYNOS7 is not set
# CONFIG_TARGET_SMDKV310 is not set
# CONFIG_TARGET_TRATS is not set
# CONFIG_TARGET_S5PC210_UNIVERSAL is not set
# CONFIG_TARGET_ORIGEN is not set
CONFIG_TARGET_ZWQ4412=y
# CONFIG_TARGET_TRATS2 is not set
# CONFIG_TARGET_ODROID is not set
# CONFIG_SPL_GPIO_SUPPORT is not set
# CONFIG_SPL_LIBCOMMON_SUPPORT is not set
# CONFIG_SPL_LIBGENERIC_SUPPORT is not set
# CONFIG_UART_IRQ_ENABLE is not set
CONFIG_SYS_MALLOC_F_LEN=0x400
CONFIG_ENV_SIZE=0x8000
CONFIG_ENV_OFFSET=0x4200
CONFIG_DM_GPIO=y
CONFIG_SPL_TEXT_BASE=0x2023400
# CONFIG_SPL_MMC_SUPPORT is not set
# CONFIG_SPL_SERIAL_SUPPORT is not set
# CONFIG_SPL_DRIVERS_MISC_SUPPORT is not set
CONFIG_SPL_SYS_MALLOC_F_LEN=0x400
CONFIG_ERR_PTR_OFFSET=0x0
CONFIG_NR_DRAM_BANKS=4
CONFIG_SPL_SIZE_LIMIT=0
CONFIG_SPL=y
CONFIG_BOOTSTAGE_STASH_ADDR=0
CONFIG_IDENT_STRING="  for zwq4412"
# CONFIG_SPL_FS_FAT is not set
# CONFIG_SPL_LIBDISK_SUPPORT is not set
# CONFIG_SPL_SPI_SUPPORT is not set
# CONFIG_ARMV7_LPAE is not set
CONFIG_CSF_SIZE=0x2060
# CONFIG_CMD_DEKBLOB is not set
# CONFIG_CMD_HDMIDETECT is not set
CONFIG_IMX_DCD_ADDR=0x0#
# ARM debug
#
# CONFIG_DEBUG_LL is not set
CONFIG_SPL_PAYLOAD="u-boot.bin"
CONFIG_BUILD_TARGET=""
CONFIG_SMBIOS_PRODUCT_NAME="zwq4412"
# CONFIG_DEBUG_UART is not set
# CONFIG_AHCI is not set
# CONFIG_OF_BOARD_FIXUP is not set#
# General setup
#
CONFIG_LOCALVERSION=" - 20200924"
CONFIG_LOCALVERSION_AUTO=y
CONFIG_CC_OPTIMIZE_FOR_SIZE=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_ENV_VARS_UBOOT_CONFIG=y
# CONFIG_SYS_BOOT_GET_CMDLINE is not set
# CONFIG_SYS_BOOT_GET_KBD is not set
CONFIG_SYS_MALLOC_F=y
CONFIG_EXPERT=y
CONFIG_SYS_MALLOC_CLEAR_ON_INIT=y
# CONFIG_SYS_MALLOC_DEFAULT_TO_INIT is not set
# CONFIG_TOOLS_DEBUG is not set
# CONFIG_PHYS_64BIT is not set
CONFIG_SPL_IMAGE="spl/u-boot-spl.bin"
# CONFIG_SYS_CUSTOM_LDSCRIPT is not set
CONFIG_PLATFORM_ELFENTRY="_start"#
# zwq4412 Partition Info
#
CONFIG_PART_KERNEL_SIZE=16
CONFIG_PART_DTB_SIZE=64#
# Boot images
#
CONFIG_ANDROID_BOOT_IMAGE=y
# CONFIG_FIT is not set
CONFIG_LEGACY_IMAGE_FORMAT=y
# CONFIG_OF_BOARD_SETUP is not set
# CONFIG_OF_SYSTEM_SETUP is not set
# CONFIG_OF_STDOUT_VIA_ALIAS is not set
CONFIG_SYS_EXTRA_OPTIONS=""
CONFIG_HAVE_SYS_TEXT_BASE=y
CONFIG_ARCH_FIXUP_FDT_MEMORY=y#
# API
#
# CONFIG_API is not set#
# Boot timing
#
# CONFIG_BOOTSTAGE is not set
CONFIG_BOOTSTAGE_RECORD_COUNT=30
CONFIG_SPL_BOOTSTAGE_RECORD_COUNT=5
CONFIG_TPL_BOOTSTAGE_RECORD_COUNT=5
CONFIG_BOOTSTAGE_STASH_SIZE=0x1000
# CONFIG_SHOW_BOOT_PROGRESS is not set#
# Boot media
#
# CONFIG_NAND_BOOT is not set
# CONFIG_ONENAND_BOOT is not set
# CONFIG_QSPI_BOOT is not set
# CONFIG_SATA_BOOT is not set
CONFIG_SD_BOOT=y
# CONFIG_SPI_BOOT is not set
CONFIG_BOOTDELAY=1
# CONFIG_USE_BOOTARGS is not set
# CONFIG_USE_BOOTCOMMAND is not set
# CONFIG_USE_PREBOOT is not set#
# Console
#
CONFIG_MENU=y
# CONFIG_CONSOLE_RECORD is not set
# CONFIG_DISABLE_CONSOLE is not set
CONFIG_LOGLEVEL=4
CONFIG_SPL_LOGLEVEL=4
CONFIG_TPL_LOGLEVEL=4
# CONFIG_SILENT_CONSOLE is not set
# CONFIG_PRE_CONSOLE_BUFFER is not set
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
# CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE is not set
# CONFIG_SYS_CONSOLE_ENV_OVERWRITE is not set
CONFIG_SYS_CONSOLE_INFO_QUIET=y
# CONFIG_SYS_STDIO_DEREGISTER is not set#
# Logging
#
# CONFIG_LOG is not set
CONFIG_LOG_DEFAULT_LEVEL=6
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_DEFAULT_FDT_FILE=""
# CONFIG_MISC_INIT_R is not set
# CONFIG_VERSION_VARIABLE is not set
# CONFIG_BOARD_LATE_INIT is not set
CONFIG_DISPLAY_CPUINFO=y
CONFIG_DISPLAY_BOARDINFO=y
# CONFIG_DISPLAY_BOARDINFO_LATE is not set
CONFIG_BOUNCE_BUFFER=y
# CONFIG_BOARD_TYPES is not set#
# Start-up hooks
#
# CONFIG_ARCH_EARLY_INIT_R is not set
# CONFIG_ARCH_MISC_INIT is not set
CONFIG_BOARD_EARLY_INIT_F=y
# CONFIG_BOARD_EARLY_INIT_R is not set
# CONFIG_LAST_STAGE_INIT is not set#
# Security support
#
CONFIG_HASH=y#
# Update support
#
# CONFIG_ANDROID_AB is not set#
# Blob list
#
# CONFIG_BLOBLIST is not set#
# SPL / TPL
#
CONFIG_SUPPORT_SPL=y
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_SPL_SYS_STACK_F_CHECK_BYTE=0xaa
# CONFIG_SPL_SYS_REPORT_STACK_F_USAGE is not set#
# PowerPC and LayerScape SPL Boot options
#
# CONFIG_SPL_BOARD_INIT is not set
# CONFIG_SPL_BOOTROM_SUPPORT is not set
CONFIG_SPL_RAW_IMAGE_SUPPORT=y
CONFIG_SPL_LEGACY_IMAGE_SUPPORT=y
# CONFIG_SPL_LEGACY_IMAGE_CRC_CHECK is not set
# CONFIG_SPL_SYS_MALLOC_SIMPLE is not set
# CONFIG_SPL_STACK_R is not set
# CONFIG_SPL_SEPARATE_BSS is not set
CONFIG_SPL_BANNER_PRINT=y
# CONFIG_SPL_EARLY_BSS is not set
# CONFIG_SPL_DISPLAY_PRINT is not set
# CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set
# CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION is not set
# CONFIG_SUPPORT_EMMC_BOOT_OVERRIDE_PART_CONFIG is not set
CONFIG_SPL_CRC32_SUPPORT=y
# CONFIG_SPL_CACHE_SUPPORT is not set
# CONFIG_SPL_CPU_SUPPORT is not set
# CONFIG_SPL_CRYPTO_SUPPORT is not set
# CONFIG_SPL_HASH_SUPPORT is not set
# CONFIG_SPL_DMA is not set
# CONFIG_SPL_ENV_SUPPORT is not set
# CONFIG_SPL_FS_EXT4 is not set
# CONFIG_SPL_FAT_WRITE is not set
# CONFIG_SPL_FPGA_SUPPORT is not set
# CONFIG_SPL_I2C_SUPPORT is not set
# CONFIG_SPL_DM_MAILBOX is not set
# CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT is not set
# CONFIG_SPL_MTD_SUPPORT is not set
# CONFIG_SPL_MUSB_NEW_SUPPORT is not set
# CONFIG_SPL_NAND_SUPPORT is not set
# CONFIG_SPL_UBI is not set
# CONFIG_SPL_NET_SUPPORT is not set
# CONFIG_SPL_NO_CPU_SUPPORT is not set
# CONFIG_SPL_NOR_SUPPORT is not set
# CONFIG_SPL_XIP_SUPPORT is not set
# CONFIG_SPL_ONENAND_SUPPORT is not set
# CONFIG_SPL_OS_BOOT is not set
# CONFIG_SPL_PCI is not set
# CONFIG_SPL_PCH_SUPPORT is not set
# CONFIG_SPL_POST_MEM_SUPPORT is not set
# CONFIG_SPL_DM_RESET is not set
# CONFIG_SPL_POWER_SUPPORT is not set
# CONFIG_SPL_POWER_DOMAIN is not set
# CONFIG_SPL_RAM_SUPPORT is not set
# CONFIG_SPL_REMOTEPROC is not set
# CONFIG_SPL_RTC_SUPPORT is not set
# CONFIG_SPL_SATA_SUPPORT is not set
# CONFIG_SPL_THERMAL is not set
# CONFIG_SPL_USB_HOST_SUPPORT is not set
# CONFIG_SPL_USB_GADGET is not set
# CONFIG_SPL_WATCHDOG_SUPPORT is not set
# CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC is not set
# CONFIG_SPL_OPTEE is not set#
# Command line interface
#
CONFIG_CMDLINE=y
CONFIG_HUSH_PARSER=y
CONFIG_CMDLINE_EDITING=y
CONFIG_AUTO_COMPLETE=y
CONFIG_SYS_LONGHELP=y
CONFIG_SYS_PROMPT="zwq4412 # "
CONFIG_SYS_XTRACE="y"#
# Autoboot options
#
CONFIG_AUTOBOOT=y
# CONFIG_AUTOBOOT_KEYED is not set
# CONFIG_AUTOBOOT_USE_MENUKEY is not set#
# Commands
##
# Info commands
#
# CONFIG_CMD_ACPI is not set
CONFIG_CMD_BDI=y
# CONFIG_CMD_CONFIG is not set
CONFIG_CMD_CONSOLE=y
# CONFIG_CMD_CPU is not set
# CONFIG_CMD_LICENSE is not set
# CONFIG_CMD_PMC is not set#
# Boot commands
#
CONFIG_CMD_BOOTD=y
CONFIG_CMD_BOOTM=y
CONFIG_CMD_BOOTZ=y
CONFIG_BOOTM_LINUX=y
CONFIG_BOOTM_NETBSD=y
# CONFIG_BOOTM_OPENRTOS is not set
# CONFIG_BOOTM_OSE is not set
CONFIG_BOOTM_PLAN9=y
CONFIG_BOOTM_RTEMS=y
CONFIG_BOOTM_VXWORKS=y
CONFIG_CMD_BOOTEFI=y
CONFIG_CMD_BOOTEFI_HELLO_COMPILE=y
# CONFIG_CMD_BOOTEFI_HELLO is not set
# CONFIG_CMD_BOOTEFI_SELFTEST is not set
# CONFIG_CMD_BOOTMENU is not set
# CONFIG_CMD_ADTIMG is not set
# CONFIG_CMD_ABOOTIMG is not set
CONFIG_CMD_ELF=y
CONFIG_CMD_FDT=y
CONFIG_CMD_GO=y
CONFIG_CMD_RUN=y
CONFIG_CMD_IMI=y
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_XIMG is not set
# CONFIG_CMD_SPL is not set
CONFIG_CMD_THOR_DOWNLOAD=y
# CONFIG_CMD_ZBOOT is not set#
# Environment commands
#
# CONFIG_CMD_ASKENV is not set
CONFIG_CMD_EXPORTENV=y
CONFIG_CMD_IMPORTENV=y
CONFIG_CMD_EDITENV=y
# CONFIG_CMD_GREPENV is not set
CONFIG_CMD_SAVEENV=y
# CONFIG_CMD_ERASEENV is not set
CONFIG_CMD_ENV_EXISTS=y
# CONFIG_CMD_ENV_CALLBACK is not set
# CONFIG_CMD_ENV_FLAGS is not set
# CONFIG_CMD_NVEDIT_EFI is not set
# CONFIG_CMD_NVEDIT_INFO is not set#
# Memory commands
#
# CONFIG_CMD_BINOP is not set
CONFIG_CMD_CRC32=y
# CONFIG_CRC32_VERIFY is not set
# CONFIG_CMD_EEPROM is not set
# CONFIG_LOOPW is not set
# CONFIG_CMD_MD5SUM is not set
# CONFIG_CMD_MEMINFO is not set
CONFIG_CMD_MEMORY=y
# CONFIG_CMD_MX_CYCLIC is not set
CONFIG_CMD_RANDOM=y
# CONFIG_CMD_MEMTEST is not set
# CONFIG_CMD_SHA1SUM is not set
# CONFIG_CMD_STRINGS is not set#
# Compression commands
#
# CONFIG_CMD_LZMADEC is not set
# CONFIG_CMD_UNLZ4 is not set
# CONFIG_CMD_UNZIP is not set
# CONFIG_CMD_ZIP is not set#
# Device access commands
#
# CONFIG_CMD_ARMFLASH is not set
# CONFIG_CMD_ADC is not set
# CONFIG_CMD_BCB is not set
# CONFIG_CMD_BIND is not set
# CONFIG_CMD_CLK is not set
# CONFIG_CMD_DEMO is not set
CONFIG_CMD_DFU=y
CONFIG_CMD_DM=y
CONFIG_CMD_FASTBOOT=y
CONFIG_CMD_FLASH=y
# CONFIG_CMD_FPGAD is not set
# CONFIG_CMD_FUSE is not set
# CONFIG_CMD_GPIO is not set
CONFIG_CMD_GPT=y
CONFIG_RANDOM_UUID=y
# CONFIG_CMD_GPT_RENAME is not set
# CONFIG_CMD_IDE is not set
# CONFIG_CMD_IO is not set
# CONFIG_CMD_IOTRACE is not set
# CONFIG_CMD_I2C is not set
CONFIG_CMD_LOADB=y
CONFIG_CMD_LOADS=y
CONFIG_CMD_MMC=y
# CONFIG_CMD_BKOPS_ENABLE is not set
# CONFIG_CMD_MMC_SWRITE is not set
# CONFIG_CMD_MTD is not set
# CONFIG_CMD_ONENAND is not set
# CONFIG_CMD_OSD is not set
CONFIG_CMD_PART=y
# CONFIG_CMD_PCI is not set
# CONFIG_CMD_PINMUX is not set
# CONFIG_CMD_POWEROFF is not set
# CONFIG_CMD_READ is not set
# CONFIG_CMD_SATA is not set
# CONFIG_CMD_SAVES is not set
# CONFIG_CMD_SCSI is not set
# CONFIG_CMD_SDRAM is not set
CONFIG_CMD_SF=y
# CONFIG_CMD_SF_TEST is not set
# CONFIG_CMD_SPI is not set
# CONFIG_CMD_TSI148 is not set
# CONFIG_CMD_UNIVERSE is not set
CONFIG_CMD_USB=y
# CONFIG_CMD_USB_SDP is not set
CONFIG_CMD_USB_MASS_STORAGE=y#
# Shell scripting commands
#
CONFIG_CMD_ECHO=y
CONFIG_CMD_ITEST=y
CONFIG_CMD_SOURCE=y
CONFIG_CMD_SETEXPR=y#
# Android support commands
#
CONFIG_CMD_NET=y
CONFIG_CMD_BOOTP=y
CONFIG_CMD_DHCP=y
CONFIG_BOOTP_BOOTPATH=y
CONFIG_BOOTP_DNS=y
# CONFIG_BOOTP_DNS2 is not set
CONFIG_BOOTP_GATEWAY=y
CONFIG_BOOTP_HOSTNAME=y
# CONFIG_BOOTP_PREFER_SERVERIP is not set
CONFIG_BOOTP_SUBNETMASK=y
# CONFIG_BOOTP_NTPSERVER is not set
# CONFIG_CMD_PCAP is not set
CONFIG_BOOTP_PXE=y
CONFIG_BOOTP_PXE_CLIENTARCH=0x15
CONFIG_BOOTP_VCI_STRING="U-Boot.armv7"
CONFIG_CMD_TFTPBOOT=y
# CONFIG_CMD_TFTPPUT is not set
# CONFIG_CMD_TFTPSRV is not set
CONFIG_NET_TFTP_VARS=y
# CONFIG_CMD_RARP is not set
CONFIG_CMD_NFS=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
# CONFIG_CMD_CDP is not set
# CONFIG_CMD_SNTP is not set
# CONFIG_CMD_DNS is not set
# CONFIG_CMD_LINK_LOCAL is not set
# CONFIG_CMD_ETHSW is not set
CONFIG_CMD_PXE=y
# CONFIG_CMD_WOL is not set#
# Misc commands
#
# CONFIG_CMD_BSP is not set
CONFIG_CMD_BLOCK_CACHE=y
CONFIG_CMD_CACHE=y
# CONFIG_CMD_CONITRACE is not set
# CONFIG_CMD_EFIDEBUG is not set
# CONFIG_CMD_EXCEPTION is not set
# CONFIG_CMD_DATE is not set
# CONFIG_CMD_TIME is not set
# CONFIG_CMD_GETTIME is not set
# CONFIG_CMD_MISC is not set
# CONFIG_MP is not set
# CONFIG_CMD_TIMER is not set
CONFIG_CMD_SYSBOOT=y
# CONFIG_CMD_QFW is not set
# CONFIG_CMD_TERMINAL is not set
# CONFIG_CMD_UUID is not set#
# TI specific command line interface
#
# CONFIG_CMD_DDR3 is not set#
# Power commands
##
# Security commands
#
# CONFIG_CMD_AES is not set
# CONFIG_CMD_BLOB is not set
# CONFIG_CMD_HASH is not set#
# Firmware commands
##
# Filesystem commands
#
# CONFIG_CMD_BTRFS is not set
CONFIG_CMD_EXT2=y
CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
# CONFIG_CMD_FS_UUID is not set
# CONFIG_CMD_JFFS2 is not set
# CONFIG_CMD_MTDPARTS is not set
CONFIG_MTDIDS_DEFAULT=""
CONFIG_MTDPARTS_DEFAULT=""
# CONFIG_CMD_REISER is not set
# CONFIG_CMD_ZFS is not set#
# Debug commands
#
# CONFIG_CMD_BEDBUG is not set
# CONFIG_CMD_DIAG is not set
# CONFIG_CMD_LOG is not set
# CONFIG_CMD_TRACE is not set
# CONFIG_CMD_UBI is not set#
# Partition Types
#
CONFIG_PARTITIONS=y
# CONFIG_MAC_PARTITION is not set
# CONFIG_SPL_MAC_PARTITION is not set
CONFIG_DOS_PARTITION=y
CONFIG_SPL_DOS_PARTITION=y
CONFIG_ISO_PARTITION=y
# CONFIG_SPL_ISO_PARTITION is not set
# CONFIG_AMIGA_PARTITION is not set
# CONFIG_SPL_AMIGA_PARTITION is not set
CONFIG_EFI_PARTITION=y
CONFIG_EFI_PARTITION_ENTRIES_NUMBERS=128
CONFIG_EFI_PARTITION_ENTRIES_OFF=0
CONFIG_SPL_EFI_PARTITION=y
CONFIG_PARTITION_UUIDS=y
CONFIG_SPL_PARTITION_UUIDS=y
# CONFIG_PARTITION_TYPE_GUID is not set
CONFIG_SUPPORT_OF_CONTROL=y
CONFIG_DTC=y#
# Device Tree Control
#
CONFIG_OF_CONTROL=y
# CONFIG_SPL_OF_CONTROL is not set
# CONFIG_OF_LIVE is not set
CONFIG_OF_SEPARATE=y
# CONFIG_OF_EMBED is not set
# CONFIG_OF_BOARD is not set
# CONFIG_OF_PRIOR_STAGE is not set
CONFIG_DEFAULT_DEVICE_TREE="zwq4412"
# CONFIG_MULTI_DTB_FIT is not set
# CONFIG_OF_DTB_PROPS_REMOVE is not set
CONFIG_MKIMAGE_DTC_PATH="dtc"#
# Environment
#
CONFIG_ENV_SUPPORT=y
CONFIG_SAVEENV=y
# CONFIG_ENV_IS_NOWHERE is not set
# CONFIG_ENV_IS_IN_EEPROM is not set
# CONFIG_ENV_IS_IN_FAT is not set
# CONFIG_ENV_IS_IN_EXT4 is not set
# CONFIG_ENV_IS_IN_FLASH is not set
CONFIG_ENV_IS_IN_MMC=y
# CONFIG_ENV_IS_IN_NAND is not set
# CONFIG_ENV_IS_IN_NVRAM is not set
# CONFIG_ENV_IS_IN_ONENAND is not set
# CONFIG_ENV_IS_IN_REMOTE is not set
# CONFIG_ENV_IS_IN_SPI_FLASH is not set
# CONFIG_SYS_REDUNDAND_ENVIRONMENT is not set
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
# CONFIG_USE_DEFAULT_ENV_FILE is not set
# CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG is not set
# CONFIG_ENV_ACCESS_IGNORE_FORCE is not set
CONFIG_NET=y
# CONFIG_NET_RANDOM_ETHADDR is not set
# CONFIG_NETCONSOLE is not set
# CONFIG_IP_DEFRAG is not set
CONFIG_TFTP_BLOCKSIZE=1468#
# Device Drivers
##
# Generic Driver Options
#
CONFIG_DM=y
# CONFIG_SPL_DM is not set
CONFIG_DM_WARN=y
# CONFIG_DM_DEBUG is not set
CONFIG_DM_DEVICE_REMOVE=y
CONFIG_DM_STDIO=y
CONFIG_DM_SEQ_ALIAS=y
# CONFIG_REGMAP is not set
# CONFIG_DEVRES is not set
CONFIG_SIMPLE_BUS=y
CONFIG_OF_TRANSLATE=y
# CONFIG_TRANSLATION_OFFSET is not set
CONFIG_DM_DEV_READ_INLINE=y
# CONFIG_ACPIGEN is not set
# CONFIG_ADC is not set
# CONFIG_ADC_EXYNOS is not set
# CONFIG_ADC_SANDBOX is not set
# CONFIG_SARADC_MESON is not set
# CONFIG_SARADC_ROCKCHIP is not set
# CONFIG_SATA is not set
# CONFIG_SCSI_AHCI is not set#
# SATA/SCSI device support
#
# CONFIG_DWC_AHSATA is not set
# CONFIG_FSL_SATA is not set
# CONFIG_MVSATA_IDE is not set
# CONFIG_SATA_MV is not set
# CONFIG_SATA_SIL is not set
# CONFIG_SATA_SIL3114 is not set
# CONFIG_AXI is not set
CONFIG_BLK=y
CONFIG_HAVE_BLOCK_DEVICE=y
CONFIG_BLOCK_CACHE=y
# CONFIG_IDE is not set
# CONFIG_BOOTCOUNT_LIMIT is not set#
# Cache Controller drivers
#
# CONFIG_CACHE is not set
# CONFIG_L2X0_CACHE is not set
# CONFIG_NCORE_CACHE is not set#
# Clock
#
# CONFIG_CLK is not set
# CONFIG_SPL_CLK_CCF is not set
# CONFIG_CLK_CCF is not set
# CONFIG_CPU is not set#
# Hardware crypto devices
#
# CONFIG_FSL_CAAM is not set
# CONFIG_SYS_FSL_SEC_BE is not set
# CONFIG_SYS_FSL_SEC_LE is not set#
# Demo for driver model
#
# CONFIG_DM_DEMO is not set
# CONFIG_BOARD is not set#
# DFU support
#
CONFIG_DFU=y
CONFIG_DFU_OVER_USB=y
# CONFIG_DFU_TFTP is not set
# CONFIG_DFU_TIMEOUT is not set
CONFIG_DFU_MMC=y
# CONFIG_DFU_RAM is not set
# CONFIG_DFU_SF is not set
# CONFIG_DFU_VIRT is not set
# CONFIG_SET_DFU_ALT_INFO is not set#
# DMA Support
#
# CONFIG_DMA is not set
# CONFIG_TI_EDMA3 is not set#
# Fastboot support
#
CONFIG_FASTBOOT=y
CONFIG_USB_FUNCTION_FASTBOOT=y
# CONFIG_UDP_FUNCTION_FASTBOOT is not set
CONFIG_FASTBOOT_BUF_ADDR=0x70000000
CONFIG_FASTBOOT_BUF_SIZE=0x4000000
CONFIG_FASTBOOT_USB_DEV=0
CONFIG_FASTBOOT_FLASH=y
CONFIG_FASTBOOT_FLASH_MMC=y
CONFIG_FASTBOOT_FLASH_MMC_DEV=0
CONFIG_FASTBOOT_GPT_NAME="gpt"
CONFIG_FASTBOOT_MBR_NAME="mbr"
# CONFIG_FASTBOOT_CMD_OEM_FORMAT is not set
# CONFIG_FIRMWARE is not set
# CONFIG_ZYNQMP_FIRMWARE is not set#
# FPGA support
#
# CONFIG_FPGA_ALTERA is not set
# CONFIG_FPGA_SOCFPGA is not set
# CONFIG_FPGA_XILINX is not set#
# GPIO Support
#
# CONFIG_GPIO_HOG is not set
# CONFIG_ALTERA_PIO is not set
# CONFIG_DWAPB_GPIO is not set
# CONFIG_AT91_GPIO is not set
# CONFIG_ATMEL_PIO4 is not set
# CONFIG_DA8XX_GPIO is not set
# CONFIG_INTEL_BROADWELL_GPIO is not set
# CONFIG_INTEL_GPIO is not set
# CONFIG_INTEL_ICH6_GPIO is not set
# CONFIG_IMX_RGPIO2P is not set
# CONFIG_HSDK_CREG_GPIO is not set
# CONFIG_LPC32XX_GPIO is not set
# CONFIG_MSM_GPIO is not set
# CONFIG_MXC_GPIO is not set
# CONFIG_MXS_GPIO is not set
# CONFIG_CMD_PCA953X is not set
# CONFIG_PCF8575_GPIO is not set
# CONFIG_ROCKCHIP_GPIO is not set
# CONFIG_XILINX_GPIO is not set
# CONFIG_CMD_TCA642X is not set
# CONFIG_TEGRA_GPIO is not set
# CONFIG_TEGRA186_GPIO is not set
# CONFIG_VYBRID_GPIO is not set
# CONFIG_SIFIVE_GPIO is not set
# CONFIG_DM_74X164 is not set
# CONFIG_DM_PCA953X is not set
# CONFIG_SPL_DM_PCA953X is not set
# CONFIG_MPC8XXX_GPIO is not set#
# Hardware Spinlock Support
#
# CONFIG_DM_HWSPINLOCK is not set#
# I2C support
#
CONFIG_DM_I2C=y
# CONFIG_I2C_SET_DEFAULT_BUS_NUM is not set
# CONFIG_DM_I2C_GPIO is not set
# CONFIG_SYS_I2C_IPROC is not set
# CONFIG_SYS_I2C_FSL is not set
# CONFIG_SYS_I2C_DW is not set
# CONFIG_SYS_I2C_INTEL is not set
# CONFIG_SYS_I2C_IMX_LPI2C is not set
# CONFIG_SYS_I2C_MXC is not set
# CONFIG_SYS_I2C_ROCKCHIP is not set
# CONFIG_SYS_I2C_S3C24X0 is not set
# CONFIG_SYS_I2C_MVTWSI is not set
# CONFIG_SYS_I2C_XILINX_XIIC is not set
# CONFIG_SYS_I2C_IHS is not set
# CONFIG_I2C_MUX is not set
CONFIG_INPUT=y
CONFIG_DM_KEYBOARD=y
# CONFIG_CROS_EC_KEYB is not set
# CONFIG_I8042_KEYB is not set
# CONFIG_TEGRA_KEYBOARD is not set
# CONFIG_TWL4030_INPUT is not set#
# LED Support
#
# CONFIG_LED is not set
# CONFIG_LED_STATUS is not set#
# Mailbox Controller Support
#
# CONFIG_DM_MAILBOX is not set#
# Memory Controller drivers
##
# Multifunction device drivers
#
# CONFIG_MISC is not set
# CONFIG_CROS_EC is not set
# CONFIG_SPL_CROS_EC is not set
# CONFIG_DS4510 is not set
# CONFIG_FSL_SEC_MON is not set
# CONFIG_NUVOTON_NCT6102D is not set
# CONFIG_PWRSEQ is not set
# CONFIG_PCA9551_LED is not set
# CONFIG_TWL4030_LED is not set
# CONFIG_WINBOND_W83627 is not set
CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET=0x0
# CONFIG_FS_LOADER is not set#
# MMC Host controller Support
#
CONFIG_MMC=y
CONFIG_MMC_WRITE=y
# CONFIG_MMC_BROKEN_CD is not set
CONFIG_DM_MMC=y
# CONFIG_MMC_SPI is not set
# CONFIG_ARM_PL180_MMCI is not set
CONFIG_MMC_QUIRKS=y
CONFIG_MMC_HW_PARTITIONING=y
# CONFIG_SUPPORT_EMMC_RPMB is not set
CONFIG_SUPPORT_EMMC_BOOT=y
# CONFIG_MMC_IO_VOLTAGE is not set
# CONFIG_SPL_MMC_IO_VOLTAGE is not set
# CONFIG_MMC_HS400_ES_SUPPORT is not set
# CONFIG_SPL_MMC_HS400_ES_SUPPORT is not set
# CONFIG_MMC_HS400_SUPPORT is not set
# CONFIG_SPL_MMC_HS400_SUPPORT is not set
# CONFIG_MMC_HS200_SUPPORT is not set
# CONFIG_SPL_MMC_HS200_SUPPORT is not set
CONFIG_MMC_VERBOSE=y
# CONFIG_MMC_TRACE is not set
CONFIG_MMC_DW=y
# CONFIG_MMC_DW_CORTINA is not set
CONFIG_MMC_DW_EXYNOS=y
# CONFIG_MMC_DW_K3 is not set
# CONFIG_MMC_DW_ROCKCHIP is not set
# CONFIG_MMC_MXC is not set
# CONFIG_MMC_PCI is not set
# CONFIG_MMC_OMAP_HS is not set
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_SDMA=y
# CONFIG_MMC_SDHCI_ADMA is not set
# CONFIG_SPL_MMC_SDHCI_ADMA is not set
# CONFIG_MMC_SDHCI_BCMSTB is not set
# CONFIG_MMC_SDHCI_CADENCE is not set
# CONFIG_MMC_SDHCI_IPROC is not set
# CONFIG_MMC_SDHCI_KONA is not set
# CONFIG_MMC_SDHCI_MSM is not set
CONFIG_MMC_SDHCI_S5P=y
# CONFIG_MMC_SDHCI_SPEAR is not set
# CONFIG_MMC_SDHCI_STI is not set
# CONFIG_MMC_SDHCI_XENON is not set
# CONFIG_MMC_SDHCI_TANGIER is not set
# CONFIG_STM32_SDMMC2 is not set
# CONFIG_FTSDC010 is not set
# CONFIG_FSL_ESDHC is not set
# CONFIG_FSL_ESDHC_IMX is not set#
# MTD Support
#
CONFIG_MTD=y
# CONFIG_DM_MTD is not set
# CONFIG_MTD_NOR_FLASH is not set
# CONFIG_SYS_MTDPARTS_RUNTIME is not set
# CONFIG_FLASH_CFI_DRIVER is not set
# CONFIG_MTD_RAW_NAND is not set#
# SPI Flash Support
#
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SF_DEFAULT_BUS=0
CONFIG_SF_DEFAULT_CS=0
CONFIG_SF_DEFAULT_MODE=3
CONFIG_SF_DEFAULT_SPEED=1000000
# CONFIG_SPI_FLASH_SFDP_SUPPORT is not set
# CONFIG_SPI_FLASH_BAR is not set
# CONFIG_SF_DUAL_FLASH is not set
# CONFIG_SPI_FLASH_ATMEL is not set
# CONFIG_SPI_FLASH_EON is not set
# CONFIG_SPI_FLASH_GIGADEVICE is not set
# CONFIG_SPI_FLASH_ISSI is not set
# CONFIG_SPI_FLASH_MACRONIX is not set
# CONFIG_SPI_FLASH_SPANSION is not set
# CONFIG_SPI_FLASH_STMICRO is not set
# CONFIG_SPI_FLASH_SST is not set
# CONFIG_SPI_FLASH_WINBOND is not set
# CONFIG_SPI_FLASH_XMC is not set
CONFIG_SPI_FLASH_USE_4K_SECTORS=y
# CONFIG_SPI_FLASH_DATAFLASH is not set
# CONFIG_SPI_FLASH_MTD is not set
# CONFIG_SPL_SPI_FLASH_MTD is not set#
# UBI support
#
# CONFIG_UBI_SILENCE_MSG is not set
# CONFIG_MTD_UBI is not set
# CONFIG_BITBANGMII is not set
# CONFIG_MV88E6352_SWITCH is not set
# CONFIG_PHYLIB is not set
# CONFIG_FSL_PFE is not set
CONFIG_DM_ETH=y
# CONFIG_DM_ETH_PHY is not set
CONFIG_NETDEVICES=y
# CONFIG_PHY_GIGE is not set
# CONFIG_ALTERA_TSE is not set
# CONFIG_BCM_SF2_ETH is not set
# CONFIG_BCMGENET is not set
# CONFIG_DWC_ETH_QOS is not set
# CONFIG_ETH_DESIGNWARE is not set
# CONFIG_ETHOC is not set
# CONFIG_FMAN_ENET is not set
# CONFIG_FTMAC100 is not set
# CONFIG_FTGMAC100 is not set
# CONFIG_MCFFEC is not set
# CONFIG_FSLDMAFEC is not set
# CONFIG_KS8851_MLL is not set
# CONFIG_MACB is not set
# CONFIG_RGMII is not set
# CONFIG_MII is not set
# CONFIG_RTL8139 is not set
# CONFIG_RTL8169 is not set
# CONFIG_SMC911X is not set
# CONFIG_SUN7I_GMAC is not set
# CONFIG_SUN4I_EMAC is not set
# CONFIG_SUN8I_EMAC is not set
# CONFIG_SH_ETHER is not set
# CONFIG_DRIVER_TI_CPSW is not set
# CONFIG_DRIVER_TI_EMAC is not set
# CONFIG_DRIVER_TI_KEYSTONE_NET is not set
# CONFIG_SYS_DPAA_QBMAN is not set
# CONFIG_TSEC_ENET is not set
# CONFIG_MEDIATEK_ETH is not set
# CONFIG_HIGMACV300_ETH is not set
# CONFIG_PCI is not set#
# PCI Endpoint
#
# CONFIG_PCI_ENDPOINT is not set
# CONFIG_X86_PCH7 is not set
# CONFIG_X86_PCH9 is not set#
# PHY Subsystem
#
# CONFIG_PHY is not set
# CONFIG_SPL_PHY is not set#
# Rockchip PHY driver
#
# CONFIG_MVEBU_COMPHY_SUPPORT is not set#
# Pin controllers
#
# CONFIG_PINCTRL is not set#
# Power
#
# CONFIG_ACPI_PMC is not set
# CONFIG_SPL_ACPI_PMC is not set
# CONFIG_TPL_ACPI_PMC is not set#
# Power Domain Support
#
# CONFIG_POWER_DOMAIN is not set
# CONFIG_DM_PMIC is not set
# CONFIG_PMIC_AS3722 is not set
# CONFIG_POWER_MC34VR500 is not set
# CONFIG_DM_REGULATOR is not set
# CONFIG_POWER_MT6323 is not set
# CONFIG_DM_PWM is not set
# CONFIG_PWM_IMX is not set
# CONFIG_PWM_SANDBOX is not set
# CONFIG_U_QE is not set
# CONFIG_RAM is not set#
# Remote Processor drivers
##
# Reset Controller Support
#
# CONFIG_DM_RESET is not set
# CONFIG_DM_RNG is not set#
# Real Time Clock
#
# CONFIG_DM_RTC is not set
# CONFIG_RTC_ENABLE_32KHZ_OUTPUT is not set
# CONFIG_RTC_RX8025 is not set
# CONFIG_RTC_PL031 is not set
# CONFIG_RTC_S35392A is not set
# CONFIG_RTC_MC146818 is not set
# CONFIG_RTC_M41T62 is not set
# CONFIG_SCSI is not set
# CONFIG_DM_SCSI is not set#
# Serial drivers
#
CONFIG_BAUDRATE=115200
CONFIG_REQUIRE_SERIAL_CONSOLE=y
CONFIG_SPECIFY_CONSOLE_INDEX=y
CONFIG_SERIAL_PRESENT=y
# CONFIG_SPL_SERIAL_PRESENT is not set
CONFIG_CONS_INDEX=1
CONFIG_DM_SERIAL=y
# CONFIG_SERIAL_RX_BUFFER is not set
# CONFIG_SERIAL_SEARCH_ALL is not set
# CONFIG_ALTERA_JTAG_UART is not set
# CONFIG_ALTERA_UART is not set
# CONFIG_ARC_SERIAL is not set
# CONFIG_ARM_DCC is not set
# CONFIG_ATMEL_USART is not set
# CONFIG_BCM6345_SERIAL is not set
# CONFIG_COREBOOT_SERIAL is not set
# CONFIG_CORTINA_UART is not set
# CONFIG_FSL_LINFLEXUART is not set
# CONFIG_FSL_LPUART is not set
# CONFIG_MVEBU_A3700_UART is not set
# CONFIG_MCFUART is not set
# CONFIG_NULLDEV_SERIAL is not set
# CONFIG_SYS_NS16550 is not set
# CONFIG_NS16550_DYNAMIC is not set
# CONFIG_PL01X_SERIAL is not set
# CONFIG_MSM_SERIAL is not set
# CONFIG_OMAP_SERIAL is not set
# CONFIG_PXA_SERIAL is not set
# CONFIG_SIFIVE_SERIAL is not set
# CONFIG_MTK_SERIAL is not set
# CONFIG_SMEM is not set#
# Sound support
#
# CONFIG_SOUND is not set#
# SOC (System On Chip) specific Drivers
#
# CONFIG_SOC_TI is not set
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_SPI_MEM=y
# CONFIG_ALTERA_SPI is not set
# CONFIG_ATCSPI200_SPI is not set
# CONFIG_ATMEL_SPI is not set
# CONFIG_BCMSTB_SPI is not set
# CONFIG_CADENCE_QSPI is not set
# CONFIG_CF_SPI is not set
# CONFIG_DESIGNWARE_SPI is not set
# CONFIG_EXYNOS_SPI is not set
# CONFIG_FSL_DSPI is not set
# CONFIG_FSL_QSPI is not set
# CONFIG_ICH_SPI is not set
# CONFIG_MPC8XXX_SPI is not set
# CONFIG_MTK_SNFI_SPI is not set
# CONFIG_MVEBU_A3700_SPI is not set
# CONFIG_MXS_SPI is not set
# CONFIG_NXP_FSPI is not set
# CONFIG_PL022_SPI is not set
# CONFIG_ROCKCHIP_SPI is not set
# CONFIG_SPI_SIFIVE is not set
# CONFIG_SOFT_SPI is not set
# CONFIG_SPI_SUNXI is not set
# CONFIG_TEGRA114_SPI is not set
# CONFIG_TEGRA20_SFLASH is not set
# CONFIG_TEGRA20_SLINK is not set
# CONFIG_TEGRA210_QSPI is not set
# CONFIG_TI_QSPI is not set
# CONFIG_XILINX_SPI is not set
# CONFIG_FSL_ESPI is not set
# CONFIG_SH_QSPI is not set
# CONFIG_KIRKWOOD_SPI is not set
# CONFIG_MXC_SPI is not set
# CONFIG_OMAP3_SPI is not set#
# SPMI support
#
# CONFIG_SPMI is not set#
# System reset device drivers
#
# CONFIG_SYSRESET is not set
# CONFIG_SYSRESET_SYSCON is not set
# CONFIG_SYSRESET_WATCHDOG is not set
# CONFIG_SYSRESET_RESETCTL is not set
# CONFIG_SYSRESET_MPC83XX is not set
# CONFIG_TEE is not set
# CONFIG_OPTEE is not set
# CONFIG_DM_THERMAL is not set#
# Timer Support
#
# CONFIG_TIMER is not set#
# TPM support
#
CONFIG_USB=y
CONFIG_DM_USB=y
# CONFIG_DM_USB_GADGET is not set#
# USB Host Controller Drivers
#
CONFIG_USB_HOST=y
# CONFIG_USB_XHCI_HCD is not set
CONFIG_USB_EHCI_HCD=y
# CONFIG_USB_EHCI_MSM is not set
# CONFIG_USB_EHCI_PCI is not set
CONFIG_USB_EHCI_GENERIC=y
# CONFIG_USB_EHCI_FSL is not set
# CONFIG_USB_OHCI_HCD is not set
# CONFIG_USB_OHCI_PCI is not set
# CONFIG_USB_UHCI_HCD is not set
# CONFIG_USB_DWC2 is not set
# CONFIG_USB_R8A66597_HCD is not set
# CONFIG_USB_CDNS3 is not set
# CONFIG_USB_DWC3 is not set#
# Legacy MUSB Support
#
# CONFIG_USB_MUSB_HCD is not set
# CONFIG_USB_MUSB_UDC is not set#
# MUSB Controller Driver
#
# CONFIG_USB_MUSB_HOST is not set
# CONFIG_USB_MUSB_GADGET is not set
# CONFIG_USB_MUSB_DA8XX is not set
# CONFIG_USB_MUSB_TI is not set
# CONFIG_USB_MUSB_AM35X is not set
# CONFIG_USB_MUSB_DSPS is not set
# CONFIG_USB_MUSB_PIO_ONLY is not set#
# USB Phy
#
# CONFIG_TWL4030_USB is not set
# CONFIG_OMAP_USB_PHY is not set
# CONFIG_ROCKCHIP_USB2_PHY is not set#
# ULPI drivers
##
# USB peripherals
#
CONFIG_USB_STORAGE=y
# CONFIG_USB_KEYBOARD is not set
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="Samsung"
CONFIG_USB_GADGET_VENDOR_NUM=0x18d1
CONFIG_USB_GADGET_PRODUCT_NUM=0x4e30
# CONFIG_USB_GADGET_ATMEL_USBA is not set
# CONFIG_USB_GADGET_BCM_UDC_OTG_PHY is not set
CONFIG_USB_GADGET_DWC2_OTG=y
# CONFIG_USB_GADGET_DWC2_OTG_PHY_BUS_WIDTH_8 is not set
# CONFIG_CI_UDC is not set
CONFIG_USB_GADGET_VBUS_DRAW=2
CONFIG_SDP_LOADADDR=0
CONFIG_USB_GADGET_DUALSPEED=y
CONFIG_USB_GADGET_DOWNLOAD=y
CONFIG_USB_FUNCTION_MASS_STORAGE=y
# CONFIG_USB_FUNCTION_ROCKUSB is not set
# CONFIG_USB_FUNCTION_SDP is not set
CONFIG_USB_FUNCTION_THOR=y
# CONFIG_USB_ETHER is not set
CONFIG_USB_HOST_ETHER=y
# CONFIG_USB_ETHER_ASIX is not set
# CONFIG_USB_ETHER_ASIX88179 is not set
# CONFIG_USB_ETHER_MCS7830 is not set
# CONFIG_USB_ETHER_RTL8152 is not set
# CONFIG_USB_ETHER_SMSC95XX is not set#
# UFS Host Controller Support
#
# CONFIG_TI_J721E_UFS is not set#
# Graphics support
#
# CONFIG_DM_VIDEO is not set
CONFIG_SYS_WHITE_ON_BLACK=y
# CONFIG_NO_FB_CLEAR is not set#
# TrueType Fonts
#
# CONFIG_VIDEO_VESA is not set
# CONFIG_VIDEO_LCD_ANX9804 is not set
# CONFIG_VIDEO_LCD_SSD2828 is not set
# CONFIG_VIDEO_MVEBU is not set
# CONFIG_I2C_EDID is not set
# CONFIG_DISPLAY is not set
# CONFIG_VIDEO_TEGRA20 is not set
# CONFIG_VIDEO_BRIDGE is not set
# CONFIG_VIDEO is not set
# CONFIG_LCD is not set
# CONFIG_VIDEO_SIMPLE is not set
# CONFIG_VIDEO_DT_SIMPLEFB is not set
# CONFIG_OSD is not set#
# VirtIO Drivers
#
# CONFIG_VIRTIO_MMIO is not set#
# 1-Wire support
#
# CONFIG_W1 is not set#
# 1-wire EEPROM support
#
# CONFIG_W1_EEPROM is not set#
# Watchdog Timer Support
#
# CONFIG_WATCHDOG is not set
CONFIG_WATCHDOG_TIMEOUT_MSECS=60000
# CONFIG_WATCHDOG_RESET_DISABLE is not set
# CONFIG_IMX_WATCHDOG is not set
# CONFIG_ULP_WATCHDOG is not set
# CONFIG_DESIGNWARE_WATCHDOG is not set
# CONFIG_WDT is not set
#
# File systems
#
# CONFIG_FS_BTRFS is not set
# CONFIG_FS_CBFS is not set
# CONFIG_SPL_FS_CBFS is not set
CONFIG_FS_EXT4=y
CONFIG_EXT4_WRITE=y
CONFIG_FS_FAT=y
CONFIG_FAT_WRITE=y
CONFIG_FS_FAT_MAX_CLUSTSIZE=65536
# CONFIG_FS_JFFS2 is not set
# CONFIG_UBIFS_SILENCE_MSG is not set
# CONFIG_FS_CRAMFS is not set
# CONFIG_YAFFS2 is not set#
# Library routines
#
# CONFIG_BCH is not set
# CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED is not set
# CONFIG_DYNAMIC_CRC_TABLE is not set
CONFIG_HAVE_PRIVATE_LIBGCC=y
CONFIG_LIB_UUID=y
CONFIG_PRINTF=y
CONFIG_SPRINTF=y
CONFIG_SPL_SPRINTF=y
CONFIG_STRTO=y
CONFIG_SPL_STRTO=y
CONFIG_IMAGE_SPARSE=y
CONFIG_IMAGE_SPARSE_FILLBUF_SIZE=0x80000
CONFIG_USE_PRIVATE_LIBGCC=y
CONFIG_SYS_HZ=1000
CONFIG_SPL_USE_TINY_PRINTF=y
# CONFIG_PANIC_HANG is not set
CONFIG_REGEX=y
CONFIG_LIB_RAND=y
# CONFIG_LIB_HW_RAND is not set
# CONFIG_SPL_TINY_MEMSET is not set
# CONFIG_TPL_TINY_MEMSET is not set
# CONFIG_BITREVERSE is not set
# CONFIG_TRACE is not set
# CONFIG_CMD_DHRYSTONE is not set#
# Security support
#
# CONFIG_AES is not set
# CONFIG_RSA is not set
# CONFIG_ASYMMETRIC_KEY_TYPE is not set
# CONFIG_TPM is not set#
# Android Verified Boot
#
# CONFIG_LIBAVB is not set#
# Hashing Support
#
# CONFIG_SHA1 is not set
# CONFIG_SHA256 is not set
# CONFIG_SHA_HW_ACCEL is not set
# CONFIG_MD5 is not set
# CONFIG_SPL_MD5 is not set#
# Compression Support
#
# CONFIG_LZ4 is not set
# CONFIG_LZMA is not set
# CONFIG_LZO is not set
CONFIG_GZIP=y
# CONFIG_BZIP2 is not set
CONFIG_ZLIB=y
# CONFIG_ZSTD is not set
# CONFIG_SPL_LZ4 is not set
# CONFIG_SPL_LZMA is not set
# CONFIG_SPL_LZO is not set
# CONFIG_SPL_GZIP is not set
# CONFIG_SPL_ZSTD is not set
# CONFIG_ERRNO_STR is not set
# CONFIG_HEXDUMP is not set
CONFIG_OF_LIBFDT=y
CONFIG_OF_LIBFDT_ASSUME_MASK=0
# CONFIG_OF_LIBFDT_OVERLAY is not set
# CONFIG_SPL_OF_LIBFDT is not set
# CONFIG_TPL_OF_LIBFDT is not set#
# System tables
#
CONFIG_GENERATE_SMBIOS_TABLE=y
CONFIG_SMBIOS_MANUFACTURER="samsung"
CONFIG_EFI_LOADER=y
CONFIG_EFI_DEVICE_PATH_TO_TEXT=y
CONFIG_EFI_LOADER_HII=y
CONFIG_EFI_UNICODE_COLLATION_PROTOCOL2=y
CONFIG_EFI_UNICODE_CAPITALIZATION=y
# CONFIG_EFI_UNICODE_COLLATION_PROTOCOL is not set
CONFIG_EFI_PLATFORM_LANG_CODES="en-US"
CONFIG_EFI_GRUB_ARM32_WORKAROUND=y
# CONFIG_EFI_LOAD_FILE2_INITRD is not set
# CONFIG_EFI_SECURE_BOOT is not set
# CONFIG_TEST_FDTDEC is not set
CONFIG_LIB_ELF=y
# CONFIG_UNIT_TEST is not set

arch/arm/mach-exynos/itop4412_setup.h

#ifndef _ITOP4412_SETUP_H
#define _ITOP4412_SETUP_H#include <config.h>
#include <asm/arch/cpu.h>#ifdef CONFIG_CLK_800_330_165
#define DRAM_CLK_330
#endif
#ifdef CONFIG_CLK_1000_200_200
#define DRAM_CLK_200
#endif
#ifdef CONFIG_CLK_1000_330_165
#define DRAM_CLK_330
#endif
#ifdef CONFIG_CLK_1000_400_200
#define DRAM_CLK_400
#endif/* this state is changing for register */
#define MUX_STAT_CHANGING       0x100
#define DIV_STAT_CHANGING       0x1/* A/M/EV PLL_CON0 */
#define SDIV(x)                 ((x) & 0x7)
#define PDIV(x)                 (((x) & 0x3f) << 8)
#define MDIV(x)                 (((x) & 0x3ff) << 16)
#define FSEL(x)                 (((x) & 0x1) << 27)
#define PLL_LOCKED_BIT          (0x1 << 29)
#define PLL_ENABLE(x)           (((x) & 0x1) << 31)/* A/M PLL_CON1 */
#define AFC(x)                  ((x) & 0x1f)
#define LOCK_CON_DLY(x)         (((x) & 0x1f) << 8)
#define LOCK_CON_IN(x)          (((x) & 0x3) << 12)
#define LOCK_CON_OUT(x)         (((x) & 0x3) << 14)
#define FEED_EN(x)              (((x) & 0x1) << 16)
#define AFC_ENB(x)              (((x) & 0x1) << 20)
#define DCC_ENB(x)              (((x) & 0x1) << 21)
#define BYPASS(x)               (((x) & 0x1) << 22)
#define RESV0(x)                (((x) & 0x1) << 23)
#define RESV1(x)                (((x) & 0x1) << 24)/* E/V PLL_CON1 */
#define K(x)                    ((x) & 0xffff)
#define MFR(x)                  (((x) & 0xff) << 16)
#define MRR(x)                  (((x) & 0x1f) << 24)
#define SEL_PF(x)               (((x) & 0x3) << 29)/* E/V PLL_CON2 */
#define ICP_BOOST(x)            ((x) & 0x3)
#define EV_FSEL(x)              (((x) & 0x1) << 2)
#define FVCO_EN(x)              (((x) & 0x1) << 3)
#define EV_BYPASS(x)            (((x) & 0x1) << 4)
#define SSCG_EN(x)              (((x) & 0x1) << 5)
#define EV_AFC_ENB(x)           (((x) & 0x1) << 6)
#define EV_DCC_ENB(x)              (((x) & 0x1) << 7)
#define EXTAFC(x)               (((x) & 0x1f) << 8)/* CLK_SRC_CPU */
#define MUX_APLL_SEL(x)         ((x) & 0x1)
#define MUX_CORE_SEL(x)         (((x) & 0x1) << 16)
#define MUX_HPM_SEL(x)          (((x) & 0x1) << 20)
#define MUX_MPLL_USER_SEL_C(x)  (((x) & 0x1) << 24)/* CLK_MUX_STAT_CPU */
#define APLL_SEL(x)             ((x) & 0x7)
#define CORE_SEL(x)             (((x) & 0x7) << 16)
#define HPM_SEL(x)              (((x) & 0x7) << 20)
#define MPLL_USER_SEL_C(x)      (((x) & 0x7) << 24)
#define MUX_STAT_CPU_CHANGING   (APLL_SEL(MUX_STAT_CHANGING) | \CORE_SEL(MUX_STAT_CHANGING) | \HPM_SEL(MUX_STAT_CHANGING) | \MPLL_USER_SEL_C(MUX_STAT_CHANGING))/* A/M/E/V PLL_LOCK */
#define PLL_LOCKTIME(x)         ((x) & 0xffff)/* CLK_DIV_CPU0 */
#define CORE_RATIO(x)           ((x) & 0x7)
#define COREM0_RATIO(x)         (((x) & 0x7) << 4)
#define COREM1_RATIO(x)         (((x) & 0x7) << 8)
#define PERIPH_RATIO(x)         (((x) & 0x7) << 12)
#define ATB_RATIO(x)            (((x) & 0x7) << 16)
#define PCLK_DBG_RATIO(x)       (((x) & 0x7) << 20)
#define APLL_RATIO(x)           (((x) & 0x7) << 24)
#define CORE2_RATIO(x)          (((x) & 0x7) << 28)/* CLK_DIV_CPU1 */
#define COPY_RATIO(x)           ((x) & 0x7)
#define HPM_RATIO(x)            (((x) & 0x7) << 4)
#define CORES_RATIO(x)          (((x) & 0x7) << 8)/* CLK_DIV_STAT_CPU0 */
#define DIV_CORE(x)             ((x) & 0x1)
#define DIV_COREM0(x)           (((x) & 0x1) << 4)
#define DIV_COREM1(x)           (((x) & 0x1) << 8)
#define DIV_PERIPH(x)           (((x) & 0x1) << 12)
#define DIV_ATB(x)              (((x) & 0x1) << 16)
#define DIV_PCLK_DBG(x)         (((x) & 0x1) << 20)
#define DIV_APLL(x)             (((x) & 0x1) << 24)
#define DIV_CORE2(x)            (((x) & 0x1) << 28)#define DIV_STAT_CPU0_CHANGING  (DIV_CORE(DIV_STAT_CHANGING) | \DIV_COREM0(DIV_STAT_CHANGING) | \DIV_COREM1(DIV_STAT_CHANGING) | \DIV_PERIPH(DIV_STAT_CHANGING) | \DIV_ATB(DIV_STAT_CHANGING) | \DIV_PCLK_DBG(DIV_STAT_CHANGING) | \DIV_APLL(DIV_STAT_CHANGING) | \DIV_CORE2(DIV_STAT_CHANGING))/* CLK_DIV_STAT_CPU1 */
#define DIV_COPY(x)             ((x) & 0x1)
#define DIV_HPM(x)              (((x) & 0x1) << 4)
#define DIV_CORES(x)            (((x) & 0x1) << 8)#define DIV_STAT_CPU1_CHANGING  (DIV_COPY(DIV_STAT_CHANGING) | \DIV_HPM(DIV_STAT_CHANGING) | \DIV_CORES(DIV_STAT_CHANGING))/* CLK_SRC_DMC */
#define MUX_C2C_SEL(x)      ((x) & 0x1)
#define MUX_DMC_BUS_SEL(x)  (((x) & 0x1) << 4)
#define MUX_DPHY_SEL(x)     (((x) & 0x1) << 8)
#define MUX_MPLL_SEL(x)     (((x) & 0x1) << 12)
#define MUX_PWI_SEL(x)      (((x) & 0xf) << 16)
#define MUX_G2D_ACP0_SEL(x) (((x) & 0x1) << 20)
#define MUX_G2D_ACP1_SEL(x) (((x) & 0x1) << 24)
#define MUX_G2D_ACP_SEL(x)  (((x) & 0x1) << 28)/* CLK_MUX_STAT_DMC */
#define C2C_SEL(x)          ((x) & 0x7)
#define DMC_BUS_SEL(x)      (((x) & 0x7) << 4)
#define DPHY_SEL(x)         (((x) & 0x7) << 8)
#define MPLL_SEL(x)         (((x) & 0x7) << 12)
#define G2D_ACP0_SEL(x)     (((x) & 0x7) << 20)
#define G2D_ACP1_SEL(x)     (((x) & 0x7) << 24)
#define G2D_ACP_SEL(x)      (((x) & 0x7) << 28)#define MUX_STAT_DMC_CHANGING   (C2C_SEL(MUX_STAT_CHANGING) | \DMC_BUS_SEL(MUX_STAT_CHANGING) | \DPHY_SEL(MUX_STAT_CHANGING) | \MPLL_SEL(MUX_STAT_CHANGING) |\G2D_ACP0_SEL(MUX_STAT_CHANGING) | \G2D_ACP1_SEL(MUX_STAT_CHANGING) | \G2D_ACP_SEL(MUX_STAT_CHANGING))/* CLK_DIV_DMC0 */
#define ACP_RATIO(x)        ((x) & 0x7)
#define ACP_PCLK_RATIO(x)   (((x) & 0x7) << 4)
#define DPHY_RATIO(x)       (((x) & 0x7) << 8)
#define DMC_RATIO(x)        (((x) & 0x7) << 12)
#define DMCD_RATIO(x)       (((x) & 0x7) << 16)
#define DMCP_RATIO(x)       (((x) & 0x7) << 20)/* CLK_DIV_DMC1 */
#define G2D_ACP_RATIO(x)    ((x) & 0xf)
#define C2C_RATIO(x)        (((x) & 0x7) << 4)
#define PWI_RATIO(x)        (((x) & 0xf) << 8)
#define C2C_ACLK_RATIO(x)   (((x) & 0x7) << 12)
#define DVSEM_RATIO(x)      (((x) & 0x7f) << 16)
#define DPM_RATIO(x)        (((x) & 0x7f) << 24)/* CLK_DIV_STAT_DMC0 */
#define DIV_ACP(x)          ((x) & 0x1)
#define DIV_ACP_PCLK(x)     (((x) & 0x1) << 4)
#define DIV_DPHY(x)         (((x) & 0x1) << 8)
#define DIV_DMC(x)          (((x) & 0x1) << 12)
#define DIV_DMCD(x)         (((x) & 0x1) << 16)
#define DIV_DMCP(x)         (((x) & 0x1) << 20)#define DIV_STAT_DMC0_CHANGING  (DIV_ACP(DIV_STAT_CHANGING) | \DIV_ACP_PCLK(DIV_STAT_CHANGING) | \DIV_DPHY(DIV_STAT_CHANGING) | \DIV_DMC(DIV_STAT_CHANGING) | \DIV_DMCD(DIV_STAT_CHANGING) | \DIV_DMCP(DIV_STAT_CHANGING))/* CLK_DIV_STAT_DMC1 */
#define DIV_G2D_ACP(x)       ((x) & 0x1)
#define DIV_C2C(x)           (((x) & 0x1) << 4)
#define DIV_PWI(x)           (((x) & 0x1) << 8)
#define DIV_C2C_ACLK(x)      (((x) & 0x1) << 12)
#define DIV_DVSEM(x)         (((x) & 0x1) << 16)
#define DIV_DPM(x)           (((x) & 0x1) << 24)#define DIV_STAT_DMC1_CHANGING  (DIV_G2D_ACP(DIV_STAT_CHANGING) | \DIV_C2C(DIV_STAT_CHANGING) | \DIV_PWI(DIV_STAT_CHANGING) | \DIV_C2C_ACLK(DIV_STAT_CHANGING) | \DIV_DVSEM(DIV_STAT_CHANGING) | \DIV_DPM(DIV_STAT_CHANGING))/* CLK_SRC_TOP0 */
#define MUX_ONENAND_1_SEL(x)    ((x) & 0x1)
#define MUX_EPLL_SEL(x)         (((x) & 0x1) << 4)
#define MUX_VPLL_SEL(x)         (((x) & 0x1) << 8)
#define MUX_ACLK_200_SEL(x)     (((x) & 0x1) << 12)
#define MUX_ACLK_100_SEL(x)     (((x) & 0x1) << 16)
#define MUX_ACLK_160_SEL(x)     (((x) & 0x1) << 20)
#define MUX_ACLK_133_SEL(x)     (((x) & 0x1) << 24)
#define MUX_ONENAND_SEL(x)      (((x) & 0x1) << 28)/* CLK_MUX_STAT_TOP */
#define ONENAND_1_SEL(x)    ((x) & 0x3)
#define EPLL_SEL(x)         (((x) & 0x3) << 4)
#define VPLL_SEL(x)         (((x) & 0x3) << 8)
#define ACLK_200_SEL(x)     (((x) & 0x3) << 12)
#define ACLK_100_SEL(x)     (((x) & 0x3) << 16)
#define ACLK_160_SEL(x)     (((x) & 0x3) << 20)
#define ACLK_133_SEL(x)     (((x) & 0x3) << 24)
#define ONENAND_SEL(x)      (((x) & 0x3) << 28)#define MUX_STAT_TOP0_CHANGING  (ONENAND_1_SEL(MUX_STAT_CHANGING) | \EPLL_SEL(MUX_STAT_CHANGING) | \EPLL_SEL(MUX_STAT_CHANGING) | \VPLL_SEL(MUX_STAT_CHANGING) | \ACLK_200_SEL(MUX_STAT_CHANGING) | \ACLK_100_SEL(MUX_STAT_CHANGING) | \ACLK_160_SEL(MUX_STAT_CHANGING) | \ACLK_133_SEL(MUX_STAT_CHANGING) | \ONENAND_SEL(MUX_STAT_CHANGING))/* CLK_SRC_TOP1 */
#define MUX_ACLK_266_GPS_SEL(x)        (((x) & 0x1) << 4)
#define MUX_ACLK_400_MCUISP_SEL(x)     (((x) & 0x1) << 8)
#define MUX_MPLL_USER_SEL_T(x)         (((x) & 0x1) << 12)
#define MUX_ACLK_266_GPS_SUB_SEL(x)    (((x) & 0x1) << 16)
#define MUX_ACLK_200_SUB_SEL(x)        (((x) & 0x1) << 20)
#define MUX_ACLK_400_MCUISP_SUB_SEL(x) (((x) & 0x1) << 24)/* CLK_MUX_STAT_TOP1 */
#define ACLK_266_GPS_SEL(x)        (((x) & 0x3) << 4)
#define ACLK_400_MCUISP_SEL(x)     (((x) & 0x3) << 8)
#define MPLL_USER_SEL_T(x)         (((x) & 0x3) << 12)
#define ACLK_266_GPS_SUB_SEL(x)    (((x) & 0x3) << 16)
#define ACLK_200_SUB_SEL(x)        (((x) & 0x3) << 20)
#define ACLK_400_MCUISP_SUB_SEL(x) (((x) & 0x3) << 24)#define MUX_STAT_TOP1_CHANGING  (MUX_ACLK_266_GPS_SEL(MUX_STAT_CHANGING) | \ACLK_400_MCUISP_SEL(MUX_STAT_CHANGING) | \MPLL_USER_SEL_T(MUX_STAT_CHANGING) | \ACLK_266_GPS_SUB_SEL(MUX_STAT_CHANGING) | \ACLK_200_SUB_SEL(MUX_STAT_CHANGING) | \ACLK_400_MCUISP_SUB_SEL(MUX_STAT_CHANGING))/* CLK_DIV_TOP */
#define ACLK_200_RATIO(x)        ((x) & 0x7)
#define ACLK_100_RATIO(x)        (((x) & 0xf) << 4)
#define ACLK_160_RATIO(x)        (((x) & 0x7) << 8)
#define ACLK_133_RATIO(x)        (((x) & 0x7) << 12)
#define ONENAND_RATIO(x)         (((x) & 0x7) << 16)
#define ACLK_266_GPS_RATIO(x)    (((x) & 0x7) << 20)
#define ACLK_400_MCUISP_RATIO(x) (((x) & 0x7) << 24)#define DIV_STAT_TOP_CHANGING    (ACLK_400_MCUISP_RATIO(DIV_STAT_CHANGING) | \ACLK_266_GPS_RATIO(DIV_STAT_CHANGING) | \ONENAND_RATIO(DIV_STAT_CHANGING) | \ACLK_133_RATIO(DIV_STAT_CHANGING) | \ACLK_160_RATIO(DIV_STAT_CHANGING) | \ACLK_100_RATIO(DIV_STAT_CHANGING) | \ACLK_200_RATIO(DIV_STAT_CHANGING))/* CLK_SRC_LEFTBUS */
#define MUX_GDL_SEL(x)         ((x) & 0x1)
#define MUX_MPLL_USER_SEL_L(x) (((x) & 0x1) << 4)/* CLK_MUX_STAT_LEFTBUS */
#define GDL_SEL(x)             ((x) & 0x7)
#define MPLL_USER_SEL_L(x)     (((x) & 0x7) << 4)#define MUX_STAT_LEFTBUS_CHANGING    (GDL_SEL(MUX_STAT_CHANGING) | \MPLL_USER_SEL_L(MUX_STAT_CHANGING))/* CLK_DIV_LEFTBUS */
#define GDL_RATIO(x)        ((x) & 0x7)
#define GPL_RATIO(x)        (((x) & 0x7) << 4)/* CLK_DIV_STAT_LEFTBUS */
#define DIV_GDL(x)          ((x) & 0x1)
#define DIV_GPL(x)          (((x) & 0x1) << 4)#define DIV_STAT_LEFTBUS_CHANGING    (DIV_GDL(DIV_STAT_CHANGING) | \DIV_GPL(DIV_STAT_CHANGING))/* CLK_SRC_RIGHTBUS */
#define MUX_GDR_SEL(x)            ((x) & 0x1)
#define MUX_MPLL_USER_SEL_R(x)    (((x) & 0x1) << 4)/* CLK_MUX_STAT_RIGHTBUS */
#define GDR_SEL(x)                ((x) & 0x7)
#define MPLL_USER_SEL_R(x)        (((x) & 0x7) << 4)#define MUX_STAT_RIGHTBUS_CHANGING    (GDR_SEL(MUX_STAT_CHANGING) | \MPLL_USER_SEL_R(MUX_STAT_CHANGING))/* CLK_DIV_RIGHTBUS */
#define GPR_RATIO(x)         ((x) & 0x7)
#define GDR_RATIO(x)         (((x) & 0x7) << 4)/* CLK_DIV_STAT_RIGHTBUS */
#define DIV_GDR(x)           ((x) & 0x1)
#define DIV_GPR(x)           ((x) & 0x1)#define DIV_STAT_RIGHTBUS_CHANGING    (DIV_GDR(DIV_STAT_CHANGING) | \DIV_GPR(DIV_STAT_CHANGING))/* CLK_SRC_PERIL0 */
#define UART0_SEL(x)        ((x) & 0xf)
#define UART1_SEL(x)        (((x) & 0xf) << 4)
#define UART2_SEL(x)        (((x) & 0xf) << 8)
#define UART3_SEL(x)        (((x) & 0xf) << 12)
#define UART4_SEL(x)        (((x) & 0xf) << 16)/* CLK_DIV_PERIL0 */
#define UART0_RATIO(x)      ((x) & 0xf)
#define UART1_RATIO(x)      (((x) & 0xf) << 4)
#define UART2_RATIO(x)      (((x) & 0xf) << 8)
#define UART3_RATIO(x)      (((x) & 0xf) << 12)
#define UART4_RATIO(x)      (((x) & 0xf) << 16)/* CLK_DIV_STAT_PERIL0 */
#define DIV_UART0(x)        ((x) & 0x1)
#define DIV_UART1(x)        (((x) & 0x1) << 4)
#define DIV_UART2(x)        (((x) & 0x1) << 8)
#define DIV_UART3(x)        (((x) & 0x1) << 12)
#define DIV_UART4(x)        (((x) & 0x1) << 16)#define DIV_STAT_PERIL0_CHANGING    (DIV_UART4(DIV_STAT_CHANGING) | \DIV_UART3(DIV_STAT_CHANGING) | \DIV_UART2(DIV_STAT_CHANGING) | \DIV_UART1(DIV_STAT_CHANGING) | \DIV_UART0(DIV_STAT_CHANGING))/* CLK_SRC_FSYS */
#define MMC1_SEL(x)         (((x) & 0xf) << 4)
#define MMC2_SEL(x)         (((x) & 0xf) << 8)
#define MMC3_SEL(x)         (((x) & 0xf) << 12)
#define MMC4_SEL(x)         (((x) & 0xf) << 16)
#define MIPIHSI_SEL(x)      (((x) & 0x1) << 24)/* CLK_DIV_FSYS0 */
#define MIPIHSI_RATIO(x)    (((x) & 0xf) << 20)/* CLK_DIV_STAT_FSYS0 */
#define DIV_MIPIHSI(x)    (((x) & 0x1) << 20)#define DIV_STAT_FSYS0_CHANGING    (DIV_MIPIHSI(DIV_STAT_CHANGING))/* CLK_DIV_FSYS1 */
#define MMC0_RATIO(x)       ((x) & 0xf)
#define MMC0_PRE_RATIO(x)   (((x) & 0xff) << 8)
#define MMC1_RATIO(x)       (((x) & 0xf) << 16)
#define MMC1_PRE_RATIO(x)   (((x) & 0xff) << 24)/* CLK_DIV_STAT_FSYS1 */
#define DIV_MMC0(x)         ((x) & 1)
#define DIV_MMC0_PRE(x)     (((x) & 1) << 8)
#define DIV_MMC1(x)         (((x) & 1) << 16)
#define DIV_MMC1_PRE(x)     (((x) & 1) << 24)#define DIV_STAT_FSYS1_CHANGING    (DIV_MMC0(DIV_STAT_CHANGING) | \DIV_MMC0_PRE(DIV_STAT_CHANGING) | \DIV_MMC1(DIV_STAT_CHANGING) | \DIV_MMC1_PRE(DIV_STAT_CHANGING))/* CLK_DIV_FSYS2 */
#define MMC2_RATIO(x)       ((x) & 0xf)
#define MMC2_PRE_RATIO(x)   (((x) & 0xff) << 8)
#define MMC3_RATIO(x)       (((x) & 0xf) << 16)
#define MMC3_PRE_RATIO(x)   (((x) & 0xff) << 24)/* CLK_DIV_STAT_FSYS2 */
#define DIV_MMC2(x)         ((x) & 0x1)
#define DIV_MMC2_PRE(x)     (((x) & 0x1) << 8)
#define DIV_MMC3(x)         (((x) & 0x1) << 16)
#define DIV_MMC3_PRE(x)     (((x) & 0x1) << 24)#define DIV_STAT_FSYS2_CHANGING    (DIV_MMC2(DIV_STAT_CHANGING) | \DIV_MMC2_PRE(DIV_STAT_CHANGING) | \DIV_MMC3(DIV_STAT_CHANGING) | \DIV_MMC3_PRE(DIV_STAT_CHANGING))/* CLK_DIV_FSYS3 */
#define MMC4_RATIO(x)       ((x) & 0x7)
#define MMC4_PRE_RATIO(x)   (((x) & 0xff) << 8)/* CLK_DIV_STAT_FSYS3 */
#define DIV_MMC4(x)         ((x) & 0x1)
#define DIV_MMC4_PRE(x)     (((x) & 0x1) << 8)#define DIV_STAT_FSYS3_CHANGING    (DIV_MMC4(DIV_STAT_CHANGING) | \DIV_MMC4_PRE(DIV_STAT_CHANGING))/* DMC */
#ifdef CONFIG_CLK_800_330_165
#define DRAM_CLK_330
#endif
#ifdef CONFIG_CLK_1000_200_200
#define DRAM_CLK_200
#endif
#ifdef CONFIG_CLK_1000_330_165
#define DRAM_CLK_330
#endif
#ifdef CONFIG_CLK_1000_400_200
#define DRAM_CLK_400
#endif/* Bus Configuration Register Address */
#define ASYNC_CONFIG        0x10010350#define DIRECT_CMD_NOP  0x07000000
#define DIRECT_CMD_ZQ   0x0a000000
#define DIRECT_CMD_CHIP1_SHIFT  (1 << 20)
#define MEM_TIMINGS_MSR_COUNT   4
#define CTRL_START  (1 << 0)
#define CTRL_DLL_ON (1 << 1)
#define AREF_EN     (1 << 5)
#define DRV_TYPE    (1 << 6)struct mem_timings {unsigned direct_cmd_msr[MEM_TIMINGS_MSR_COUNT];unsigned timingref;unsigned timingrow;unsigned timingdata;unsigned timingpower;unsigned zqcontrol;unsigned control0;unsigned control1;unsigned control2;unsigned concontrol;unsigned prechconfig;unsigned memcontrol;unsigned memconfig0;unsigned memconfig1;unsigned dll_resync;unsigned dll_on;
};/* MIU */
/* MIU Config Register Offsets*/
#define APB_SFR_INTERLEAVE_CONF_OFFSET  0x400
#define APB_SFR_ARBRITATION_CONF_OFFSET 0xC00
#define ABP_SFR_SLV_ADDRMAP_CONF_OFFSET 0x800
#define ABP_SFR_INTERLEAVE_ADDRMAP_START_OFFSET 0x808
#define ABP_SFR_INTERLEAVE_ADDRMAP_END_OFFSET   0x810
#define ABP_SFR_SLV0_SINGLE_ADDRMAP_START_OFFSET    0x818
#define ABP_SFR_SLV0_SINGLE_ADDRMAP_END_OFFSET  0x820
#define ABP_SFR_SLV1_SINGLE_ADDRMAP_START_OFFSET    0x828
#define ABP_SFR_SLV1_SINGLE_ADDRMAP_END_OFFSET  0x830#if (defined CONFIG_ORIGEN) || (defined CONFIG_ITOP4412)
/* Interleave: 2Bit, Interleave_bit1: 0x15, Interleave_bit0: 0x7 */
#define APB_SFR_INTERLEAVE_CONF_VAL 0x20001507
#define APB_SFR_ARBRITATION_CONF_VAL    0x00000001
#endif#define INTERLEAVE_ADDR_MAP_START_ADDR  0x40000000
#define INTERLEAVE_ADDR_MAP_END_ADDR    0xbfffffff
#define INTERLEAVE_ADDR_MAP_EN      0x00000001#ifdef CONFIG_MIU_1BIT_INTERLEAVED
/* Interleave_bit0: 0xC*/
#define APB_SFR_INTERLEAVE_CONF_VAL 0x0000000c
#endif
#ifdef CONFIG_MIU_2BIT_INTERLEAVED
/* Interleave: 2Bit, Interleave_bit1: 0x15, Interleave_bit0: 0xc */
#define APB_SFR_INTERLEAVE_CONF_VAL 0x2000150c
#endif
#define SLAVE0_SINGLE_ADDR_MAP_START_ADDR   0x40000000
#define SLAVE0_SINGLE_ADDR_MAP_END_ADDR     0x7fffffff
#define SLAVE1_SINGLE_ADDR_MAP_START_ADDR   0x80000000
#define SLAVE1_SINGLE_ADDR_MAP_END_ADDR     0xbfffffff
/* Enable SME0 and SME1*/
#define APB_SFR_SLV_ADDR_MAP_CONF_VAL       0x00000006#define FORCE_DLL_RESYNC    3
#define DLL_CONTROL_ON      1#define DIRECT_CMD1 0x00020000
#define DIRECT_CMD2 0x00030000
#define DIRECT_CMD3 0x00010002
#define DIRECT_CMD4 0x00000328#define CTRL_ZQ_MODE_NOTERM (0x1 << 0)
#define CTRL_ZQ_START       (0x1 << 1)
#define CTRL_ZQ_DIV     (0 << 4)
#define CTRL_ZQ_MODE_DDS    (0x7 << 8)
#define CTRL_ZQ_MODE_TERM   (0x2 << 11)
#define CTRL_ZQ_FORCE_IMPN  (0x5 << 14)
#define CTRL_ZQ_FORCE_IMPP  (0x6 << 17)
#define CTRL_DCC        (0xE38 << 20)
#define ZQ_CONTROL_VAL      (CTRL_ZQ_MODE_NOTERM | CTRL_ZQ_START\| CTRL_ZQ_DIV | CTRL_ZQ_MODE_DDS\| CTRL_ZQ_MODE_TERM | CTRL_ZQ_FORCE_IMPN\| CTRL_ZQ_FORCE_IMPP | CTRL_DCC)#define ASYNC           (0 << 0)
#define CLK_RATIO       (1 << 1)
#define DIV_PIPE        (1 << 3)
#define AWR_ON          (1 << 4)
#define AREF_DISABLE        (0 << 5)
#define DRV_TYPE_DISABLE    (0 << 6)
#define CHIP0_NOT_EMPTY     (0 << 8)
#define CHIP1_NOT_EMPTY     (0 << 9)
#define DQ_SWAP_DISABLE     (0 << 10)
#define QOS_FAST_DISABLE    (0 << 11)
#define RD_FETCH        (0x3 << 12)
#define TIMEOUT_LEVEL0      (0xFFF << 16)
#define CONCONTROL_VAL      (ASYNC | CLK_RATIO | DIV_PIPE | AWR_ON\| AREF_DISABLE | DRV_TYPE_DISABLE\| CHIP0_NOT_EMPTY | CHIP1_NOT_EMPTY\| DQ_SWAP_DISABLE | QOS_FAST_DISABLE\| RD_FETCH | TIMEOUT_LEVEL0)#define CLK_STOP_DISABLE    (0 << 1)
#define DPWRDN_DISABLE      (0 << 2)
#define DPWRDN_TYPE     (0 << 3)
#define TP_DISABLE      (0 << 4)
#define DSREF_DIABLE        (0 << 5)
#define ADD_LAT_PALL        (1 << 6)
#define MEM_TYPE_DDR3       (0x6 << 8)
#define MEM_WIDTH_32        (0x2 << 12)
#define NUM_CHIP_2      (0 << 16)
#define BL_8            (0x3 << 20)
#define MEMCONTROL_VAL      (CLK_STOP_DISABLE | DPWRDN_DISABLE\| DPWRDN_TYPE | TP_DISABLE | DSREF_DIABLE\| ADD_LAT_PALL | MEM_TYPE_DDR3 | MEM_WIDTH_32\| NUM_CHIP_2 | BL_8)#define CHIP_BANK_8     (0x3 << 0)
#define CHIP_ROW_14     (0x3 << 4)
#define CHIP_COL_10     (0x3 << 8)
#define CHIP_MAP_INTERLEAVED    (1 << 12)
#define CHIP_MASK       (0xC0 << 16)
#ifdef CONFIG_MIU_LINEAR
#define CHIP0_BASE      (0x40 << 24)
#define CHIP1_BASE      (0x60 << 24)
#else
#define CHIP0_BASE      (0x40 << 24)
#define CHIP1_BASE      (0x80 << 24)
#endif
#define MEMCONFIG0_VAL      (CHIP_BANK_8 | CHIP_ROW_14 | CHIP_COL_10\| CHIP_MAP_INTERLEAVED | CHIP_MASK | CHIP0_BASE)
#define MEMCONFIG1_VAL      (CHIP_BANK_8 | CHIP_ROW_14 | CHIP_COL_10\| CHIP_MAP_INTERLEAVED | CHIP_MASK | CHIP1_BASE)#define TP_CNT          (0xff << 24)
#define PRECHCONFIG     TP_CNT#define CTRL_OFF        (0 << 0)
#define CTRL_DLL_OFF        (0 << 1)
#define CTRL_HALF       (0 << 2)
#define CTRL_DFDQS      (1 << 3)
#define DQS_DELAY       (0 << 4)
#define CTRL_START_POINT    (0x10 << 8)
#define CTRL_INC        (0x10 << 16)
#define CTRL_FORCE      (0x71 << 24)
#define CONTROL0_VAL        (CTRL_OFF | CTRL_DLL_OFF | CTRL_HALF\| CTRL_DFDQS | DQS_DELAY | CTRL_START_POINT\| CTRL_INC | CTRL_FORCE)#define CTRL_SHIFTC     (0x6 << 0)
#define CTRL_REF        (8 << 4)
#define CTRL_SHGATE     (1 << 29)
#define TERM_READ_EN        (1 << 30)
#define TERM_WRITE_EN       (1 << 31)
#define CONTROL1_VAL        (CTRL_SHIFTC | CTRL_REF | CTRL_SHGATE\| TERM_READ_EN | TERM_WRITE_EN)#define CONTROL2_VAL        0x00000000#ifdef CONFIG_ITOP4412
#define TIMINGREF_VAL       0x000000BB
#define TIMINGROW_VAL       0x4046654f
#define TIMINGDATA_VAL      0x46400506
#define TIMINGPOWER_VAL     0x52000A3C
#else
#define TIMINGREF_VAL       0x000000BC
#ifdef DRAM_CLK_330
#define TIMINGROW_VAL       0x3545548d
#define TIMINGDATA_VAL      0x45430506
#define TIMINGPOWER_VAL     0x4439033c
#endif
#ifdef DRAM_CLK_400
#define TIMINGROW_VAL       0x45430506
#define TIMINGDATA_VAL      0x56500506
#define TIMINGPOWER_VAL     0x5444033d
#endif
#endif#ifdef CONFIG_BOARD_TYPES
extern void sdelay(unsigned long);
#endif
#endif

arch/arm/mach-exynos/clock.c

1.exynos4_get_mmc_clk(int dev_index)--->#ifdef CONFIG_ITOP4412struct exynos4x12_clock *clk =(struct exynos4x12_clock *)samsung_get_base_clock();
#elsestruct exynos4_clock *clk =(struct exynos4_clock *)samsung_get_base_clock();
#endif
2.exynos4_set_mmc_clk(int dev_index, unsigned int div)---->#ifdef CONFIG_ITOP4412struct exynos4x12_clock *clk =(struct exynos4x12_clock *)samsung_get_base_clock();
#elsestruct exynos4_clock *clk =(struct exynos4_clock *)samsung_get_base_clock();
#endif3.exynos4_get_lcd_clk(void)--->#ifdef CONFIG_ITOP4412struct exynos4x12_clock *clk =(struct exynos4x12_clock *)samsung_get_base_clock();
#elsestruct exynos4_clock *clk =(struct exynos4_clock *)samsung_get_base_clock();
#endif#ifdef CONFIG_ITOP4412sel = readl(&clk->src_lcd);
#elsesel = readl(&clk->src_lcd0);
#endif#ifdef CONFIG_ITOP4412ratio = readl(&clk->div_lcd);
#elseratio = readl(&clk->div_lcd0);
#endif4.exynos4_set_lcd_clk(void)---->#ifdef CONFIG_ITOP4412struct exynos4x12_clock *clk =(struct exynos4x12_clock *)samsung_get_base_clock();
#elsestruct exynos4_clock *clk =(struct exynos4_clock *)samsung_get_base_clock();
#endif#ifdef CONFIG_ITOP4412clrsetbits_le32(&clk->src_lcd, 0xf, 0x6);
#elseclrsetbits_le32(&clk->src_lcd0, 0xf, 0x6);
#endif#ifdef CONFIG_ITOP4412setbits_le32(&clk->gate_ip_lcd, 1 << 0);
#elsesetbits_le32(&clk->gate_ip_lcd0, 1 << 0);
#endif#ifdef CONFIG_ITOP4412clrsetbits_le32(&clk->div_lcd, 0xf, 0x1);
#elseclrsetbits_le32(&clk->div_lcd0, 0xf, 0x1);
#endif

diff --git a/lowlevel_init.c b/lowlevel_init.c
index 1e090fd..658ea01 100755
--- a/lowlevel_init.c
+++ b/lowlevel_init.c
@@ -218,12 +218,18 @@ int do_lowlevel_init(void)#ifdef CONFIG_DEBUG_UART#if (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_SERIAL_SUPPORT)) || \!defined(CONFIG_SPL_BUILD)
+#ifdef CONFIG_ITOP4412
+               exynos_pinmux_config(PERIPH_ID_UART2, PINMUX_FLAG_NONE);
+#elseexynos_pinmux_config(PERIPH_ID_UART3, PINMUX_FLAG_NONE);
+#endifdebug_uart_init();#endif#endifmem_ctrl_init(actions & DO_MEM_RESET);
+#ifndef CONFIG_ITOP4412tzpc_init();
+#endif}return actions & DO_WAKEUP;

diff --git a/power.c b/power.c
index c923460..2879410 100755
--- a/power.c
+++ b/power.c
@@ -153,6 +153,25 @@ void exynos_dp_phy_ctrl(unsigned int enable)exynos5_dp_phy_control(enable);}+static void exynos4x12_set_ps_hold_ctrl(void)
+{
+    struct exynos4x12_power *power =
+        (struct exynos4x12_power *)samsung_get_base_power();
+
+    /* value: 1000000000B */
+    setbits_le32(&power->ps_hold_control, EXYNOS_PS_HOLD_CONTROL_DATA_HIGH);
+
+    /**
+     * GPX0PUD register
+     *
+     * 0x0 = Disables Pull-up/Pull-down
+     * 0x1 = Enables Pull-down
+     * 0x2 = Reserved
+     * 0x3 = Enables Pull-up
+     */
+    writel(0x3, (unsigned int *)0x11000c08);
+}
+static void exynos5_set_ps_hold_ctrl(void){struct exynos5_power *power =
@@ -173,6 +192,10 @@ void set_ps_hold_ctrl(void){if (cpu_is_exynos5())exynos5_set_ps_hold_ctrl();
+#ifdef CONFIG_ITOP4412
+    else if (cpu_is_exynos4())
+        exynos4x12_set_ps_hold_ctrl();
+#endif}

diff --git a/include/mach/power.h b/include/mach/power.h
index 88f70d9..d6e4dd8 100755
--- a/include/mach/power.h
+++ b/include/mach/power.h
@@ -210,6 +210,214 @@ struct exynos4_power {unsigned int    gps_alive_option;};+struct exynos4x12_power {
+    unsigned int    om_stat;
+    unsigned char   res1[0xc];
+    unsigned int    rtc_clko_sel;
+    unsigned int    gnss_rtc_out_ctrl;
+    unsigned int    lpi_denial_mask0;
+    unsigned int    lpi_denial_mask1;
+    unsigned int    lpi_denial_mask2;
+    unsigned int    c2c_ctrl;
+    unsigned char   res2[0x1d8];
+    unsigned int    central_seq_config;
+    unsigned int    res3;
+    unsigned int    central_seq_option;
+    unsigned char   res4[0x1f4];
+    unsigned int    swreset;
+    unsigned int    rst_stat;
+    unsigned int    auto_wdt_reset_disable;
+    unsigned int    mask_wdt_reset_request;
+    unsigned char   res5[0x1f0];
+    unsigned int    wakeup_stat;
+    unsigned int    eint_wakeup_mask;
+    unsigned int    wakeup_mask;
+    unsigned char   res6[0xf4];
+    unsigned int    hdmi_phy_control;
+    unsigned int    usbdevice_phy_control;
+    unsigned int    hsic_1_phy_control;
+    unsigned int    hsic_2_phy_control;
+    unsigned int    mipi_phy0_control;
+    unsigned int    mipi_phy1_control;
+    unsigned int    adc_phy_control;
+    unsigned char   res7[0x64];
+    unsigned int    body_bias_con0;
+    unsigned int    body_bias_con1;
+    unsigned int    body_bias_con2;
+    unsigned int    body_bias_con3;
+    unsigned char   res8[0x70];
+    unsigned int    inform0;
+    unsigned int    inform1;
+    unsigned int    inform2;
+    unsigned int    inform3;
+    unsigned int    inform4;
+    unsigned int    inform5;
+    unsigned int    inform6;
+    unsigned int    inform7;
+    unsigned char   res9[0x1e0];
+    unsigned int    pmu_debug;
+    unsigned char   res10[0x5fc];
+    unsigned int    arm_core0_sys_pwr_reg;
+    unsigned char   res11[0xc];
+    unsigned int    arm_core1_sys_pwr_reg;
+    unsigned char   res12[0x6c];
+    unsigned int    arm_common_sys_pwr_reg;
+    unsigned char   res13[0x3c];
+    unsigned int    arm_cpu_l2_0_sys_pwr_reg;
+    unsigned int    arm_cpu_l2_1_sys_pwr_reg;
+    unsigned char   res14[0x38];
+    unsigned int    cmu_aclkstop_sys_pwr_reg;
+    unsigned int    cmu_sclkstop_sys_pwr_reg;
+    unsigned char   res15[0x4];
+    unsigned int    cmu_reset_sys_pwr_reg;
+    unsigned char   res16[0x10];
+    unsigned int    apll_sysclk_sys_pwr_reg;
+    unsigned int    mpll_sysclk_sys_pwr_reg;
+    unsigned int    vpll_sysclk_sys_pwr_reg;
+    unsigned int    epll_sysclk_sys_pwr_reg;
+    unsigned char   res17[0x8];
+    unsigned int    cmu_clkstop_gps_alive_sys_pwr_reg;
+    unsigned int    cmu_reset_gps_alive_sys_pwr_reg;
+    unsigned int    cmu_clkstop_cam_sys_pwr_reg;
+    unsigned int    cmu_clkstop_tv_sys_pwr_reg;
+    unsigned int    cmu_clkstop_mfc_sys_pwr_reg;
+    unsigned int    cmu_clkstop_g3d_sys_pwr_reg;
+    unsigned int    cmu_clkstop_lcd0_sys_pwr_reg;
+    unsigned int    cmu_clkstop_isp_sys_pwr_reg;
+    unsigned int    cmu_clkstop_maudio_sys_pwr_reg;
+    unsigned int    cmu_clkstop_gps_sys_pwr_reg;
+    unsigned int    cmu_reset_cam_sys_pwr_reg;
+    unsigned int    cmu_reset_tv_sys_pwr_reg;
+    unsigned int    cmu_reset_mfc_sys_pwr_reg;
+    unsigned int    cmu_reset_g3d_sys_pwr_reg;
+    unsigned int    cmu_reset_lcd0_sys_pwr_reg;
+    unsigned int    cmu_reset_isp_sys_pwr_reg;
+    unsigned int    cmu_reset_maudio_sys_pwr_reg;
+    unsigned int    cmu_reset_gps_sys_pwr_reg;
+    unsigned int    top_bus_sys_pwr_reg;
+    unsigned int    top_retention_sys_pwr_reg;
+    unsigned int    top_pwr_sys_pwr_reg;
+    unsigned char   res18[0x14];
+    unsigned int    logic_reset_sys_pwr_reg;
+    unsigned char   res19[0x1c];
+    unsigned int    onenandxl_mem_sys_pwr_reg;
+    unsigned int    hsi_mem_sys_pwr_reg;
+    unsigned char   res20[0x4];
+    unsigned int    usbotg_mem_sys_pwr_reg;
+    unsigned int    sdmmc_mem_sys_pwr_reg;
+    unsigned int    cssys_mem_sys_pwr_reg;
+    unsigned int    secss_mem_sys_pwr_reg;
+    unsigned int    potator_mem_sys_pwr_reg;
+    unsigned char   res21[0x20];
+    unsigned int    pad_retention_dram_sys_pwr_reg;
+    unsigned int    pad_retention_maudio_sys_pwr_reg;
+    unsigned char   res22[0x18];
+    unsigned int    pad_retention_gpio_sys_pwr_reg;
+    unsigned int    pad_retention_uart_sys_pwr_reg;
+    unsigned int    pad_retention_mmca_sys_pwr_reg;
+    unsigned int    pad_retention_mmcb_sys_pwr_reg;
+    unsigned int    pad_retention_ebia_sys_pwr_reg;
+    unsigned int    pad_retention_ebib_sys_pwr_reg;
+    unsigned char   res23[0x8];
+    unsigned int    pad_isolation_sys_pwr_reg;
+    unsigned char   res24[0x1c];
+    unsigned int    pad_alv_sel_sys_pwr_reg;
+    unsigned char   res25[0x1c];
+    unsigned int    xusbxti_sys_pwr_reg;
+    unsigned int    xxti_sys_pwr_reg;
+    unsigned char   res26[0x38];
+    unsigned int    ext_regulator_sys_pwr_reg;
+    unsigned char   res27[0x3c];
+    unsigned int    gpio_mode_sys_pwr_reg;
+    unsigned char   res28[0x3c];
+    unsigned int    gpio_mode_maudio_sys_pwr_reg;
+    unsigned char   res29[0x3c];
+    unsigned int    cam_sys_pwr_reg;
+    unsigned int    tv_sys_pwr_reg;
+    unsigned int    mfc_sys_pwr_reg;
+    unsigned int    g3d_sys_pwr_reg;
+    unsigned int    lcd0_sys_pwr_reg;
+    unsigned int    isp_sys_pwr_reg;
+    unsigned int    maudio_sys_pwr_reg;
+    unsigned int    gps_sys_pwr_reg;
+    unsigned int    gps_alive_sys_pwr_reg;
+    unsigned char   res30[0xc5c];
+    unsigned int    arm_core0_configuration;
+    unsigned int    arm_core0_status;
+    unsigned int    arm_core0_option;
+    unsigned char   res31[0x74];
+    unsigned int    arm_core1_configuration;
+    unsigned int    arm_core1_status;
+    unsigned int    arm_core1_option;
+    unsigned char   res32[0x37c];
+    unsigned int    arm_common_option;
+    unsigned char   res33[0x1f4];
+    unsigned int    arm_cpu_l2_0_configuration;
+    unsigned int    arm_cpu_l2_0_status;
+    unsigned char   res34[0x18];
+    unsigned int    arm_cpu_l2_1_configuration;
+    unsigned int    arm_cpu_l2_1_status;
+    unsigned char   res35[0xa00];
+    unsigned int    pad_retention_maudio_option;
+    unsigned char   res36[0xdc];
+    unsigned int    pad_retention_gpio_option;
+    unsigned char   res37[0x1c];
+    unsigned int    pad_retention_uart_option;
+    unsigned char   res38[0x1c];
+    unsigned int    pad_retention_mmca_option;
+    unsigned char   res39[0x1c];
+    unsigned int    pad_retention_mmcb_option;
+    unsigned char   res40[0x1c];
+    unsigned int    pad_retention_ebia_option;
+    unsigned char   res41[0x1c];
+    unsigned int    pad_retention_ebib_option;
+    unsigned char   res42[0x160];
+    unsigned int    ps_hold_control;
+    unsigned char   res43[0xf0];
+    unsigned int    xusbxti_configuration;
+    unsigned int    xusbxti_status;
+    unsigned char   res44[0x14];
+    unsigned int    xusbxti_duration;
+    unsigned int    xxti_configuration;
+    unsigned int    xxti_status;
+    unsigned char   res45[0x14];
+    unsigned int    xxti_duration;
+    unsigned char   res46[0x1dc];
+    unsigned int    ext_regulator_duration;
+    unsigned char   res47[0x5e0];
+    unsigned int    cam_configuration;
+    unsigned int    cam_status;
+    unsigned int    cam_option;
+    unsigned char   res48[0x14];
+    unsigned int    tv_configuration;
+    unsigned int    tv_status;
+    unsigned int    tv_option;
+    unsigned char   res49[0x14];
+    unsigned int    mfc_configuration;
+    unsigned int    mfc_status;
+    unsigned int    mfc_option;
+    unsigned char   res50[0x14];
+    unsigned int    g3d_configuration;
+    unsigned int    g3d_status;
+    unsigned int    g3d_option;
+    unsigned char   res51[0x14];
+    unsigned int    lcd0_configuration;
+    unsigned int    lcd0_status;
+    unsigned int    lcd0_option;
+    unsigned char   res52[0x14];
+    unsigned int    isp_configuration;
+    unsigned int    isp_status;
+    unsigned int    isp_option;
+    unsigned char   res53[0x34];
+    unsigned int    gps_configuration;
+    unsigned int    gps_status;
+    unsigned int    gps_option;
+    unsigned char   res54[0x14];
+    unsigned int    gps_alive_configuration;
+    unsigned int    gps_alive_status;
+    unsigned int    gps_alive_option;
+};

arm/include/asm/mach-types.h
+#define MACH_TYPE_ITOP4412             5115

arch/arm/mach-exynos/dmc_init_exynos4.c

#ifdef CONFIG_ITOP4412
#include "itop4412_setup.h"
#else
#include "exynos4_setup.h"
#endif#if   defined(CONFIG_ORIGEN) || defined(CONFIG_ITOP4412)/* Interleave: 2Bit, Interleave_bit1: 0x15, Interleave_bit0: 0x7 */writel(APB_SFR_INTERLEAVE_CONF_VAL, EXYNOS4_MIU_BASE +APB_SFR_INTERLEAVE_CONF_OFFSET);/* Update MIU Configuration */writel(APB_SFR_ARBRITATION_CONF_VAL, EXYNOS4_MIU_BASE +APB_SFR_ARBRITATION_CONF_OFFSET);
#else

include/configs$ cp origen.h itop4412.h

itop4412.h

/** Copyright (C) 2011 Samsung Electronics** Configuration settings for the SAMSUNG ORIGEN (EXYNOS4210) board.** SPDX-License-Identifier:    GPL-2.0+*/#ifndef __CONFIG_ITOP4412_H
#define __CONFIG_ITOP4412_H#include <configs/exynos4-common.h>/* High Level Configuration Options */
#define CONFIG_EXYNOS4210       1   /* which is a EXYNOS4210 SoC */
#define CONFIG_ITOP4412         1   /* working with ITOP4412*/#define CONFIG_SYS_DCACHE_OFF     1/* ORIGEN has 4 bank of DRAM */
#define CONFIG_NR_DRAM_BANKS        4
#define CONFIG_SYS_SDRAM_BASE       0x40000000
#define PHYS_SDRAM_1            CONFIG_SYS_SDRAM_BASE
#define SDRAM_BANK_SIZE         (256 << 20)   /* 256 MB *//* memtest works on */
/*#define CONFIG_SYS_MEMTEST_START  CONFIG_SYS_SDRAM_BASE
#define CONFIG_SYS_MEMTEST_END      (CONFIG_SYS_SDRAM_BASE + 0x6000000)*/
#define CONFIG_SYS_LOAD_ADDR        (CONFIG_SYS_SDRAM_BASE + 0x3E00000)#define CONFIG_SYS_TEXT_BASE     0x43E00000#define CONFIG_MACH_TYPE      MACH_TYPE_ITOP4412/* select serial console configuration */
#define CONFIG_SERIAL2/* Console configuration */
#define CONFIG_DEFAULT_CONSOLE      "console=ttySAC1,115200n8\0"#define CONFIG_SYS_MEM_TOP_HIDE (1 << 20) /* ram console */#define CONFIG_SYS_MONITOR_BASE    0x00000000/* Power Down Modes */
#define S5P_CHECK_SLEEP         0x00000BAD
#define S5P_CHECK_DIDLE         0xBAD00000
#define S5P_CHECK_LPA           0xABAD0000#define CONFIG_SUPPORT_RAW_INITRD/* MMC SPL */
#define COPY_BL2_FNPTR_ADDR 0x02020030
#define CONFIG_SPL_TEXT_BASE    0x02023400  /* 0x02021410 */#define CONFIG_EXTRA_ENV_SETTINGS \"loadaddr=0x40007000\0" \"rdaddr=0x48000000\0" \"kerneladdr=0x40007000\0" \"dtbaddr=0x41000000\0" \"ramdiskaddr=0x48000000\0" \"fastbootbuf=" __stringify(CONFIG_FASTBOOT_BUF_ADDR) "\0" \"console=ttySAC2,115200n8\0" \"mmcdev=0\0" \"bootenv=uEnv.txt\0" \"loadbootenv=load mmc ${mmcdev} ${loadaddr} ${bootenv}\0" \"importbootenv=echo Importing environment from mmc ...; " \"env import -t $loadaddr $filesize\0" \"loadbootscript=load mmc ${mmcdev} ${loadaddr} boot.scr\0" \"bootscript=echo Running bootscript from mmc${mmcdev} ...; " \"source ${loadaddr}\0" \"find_defdtb=" \"if env exists defdtb; then true; " \"else setenv defdtb dtb; fi;\0" \"ipaddr=192.168.177.132\0" \"ethaddr=08:90:90:90:90:90\0" \"serverip=192.168.177.128\0" \"getuboot=nfs ${fastbootbuf} ${serverip}:${path_uboot}; mmcpart write bootloader ${fastbootbuf}\0" \"getdtb=nfs ${fastbootbuf} ${serverip}:${path_dtb}; run find_defdtb; mmcpart write ${defdtb} ${fastbootbuf}\0" \"getkernel=nfs ${fastbootbuf} ${serverip}:${path_kernel}; mmcpart write kernel ${fastbootbuf}\0" \"getsystem=nfs ${fastbootbuf} ${serverip}:${path_system}; mmcpart write system ${fastbootbuf}\0" \"usb=usb start; usb reset\0"
#define CONFIG_BOOTCOMMAND \"mmcpart read kernel ${kerneladdr}; run find_defdtb; " \"mmcpart read ${defdtb} ${dtbaddr}; bootm ${kerneladdr} - ${dtbaddr}"#define CONFIG_CLK_1000_400_200/* MIU (Memory Interleaving Unit) */
#define CONFIG_MIU_2BIT_21_7_INTERLEAVED#define CONFIG_SYS_MMC_ENV_DEV      0
#define CONFIG_ENV_SIZE         (8 << 10) /* 16 KB */
#define RESERVE_BLOCK_SIZE      (512)
#define BL1_SIZE            (8 << 10) /*16 K reserved for BL1*/
/*#define BL2_SIZE            (16 << 10)
#define CONFIG_ENV_OFFSET       (RESERVE_BLOCK_SIZE + BL1_SIZE + BL2_SIZE)*/
#define SPL_SIZE            (16 << 10) /*8 K reserved for SPL*/#define CONFIG_SPL_MAX_FOOTPRINT   (14 * 1024)#define CONFIG_SYS_INIT_SP_ADDR      0x02040000
/*#define UBOOT_SIZE                  (2 << 20)
#define CONFIG_SYS_INIT_SP_ADDR     (CONFIG_SYS_TEXT_BASE+UBOOT_SIZE-0x1000)*//* U-Boot copy size from boot Media to DRAM.*/
#define COPY_BL2_SIZE       0x80000
#define BL2_START_OFFSET    ((RESERVE_BLOCK_SIZE + BL1_SIZE + SPL_SIZE)/512)
#define BL2_SIZE_BLOC_COUNT (COPY_BL2_SIZE/512)#endif   /* __CONFIG_H */

spl_boot.c
#endifcase BOOT_MODE_SD:offset = BL2_START_OFFSET;size = BL2_SIZE_BLOC_COUNT;copy_bl2 = get_irom_func(MMC_INDEX);break;
+#ifdef CONFIG_SUPPORT_EMMC_BOOT
+        case BOOT_MODE_EMMC:
+#ifdef CONFIG_ITOP4412case BOOT_MODE_EMMC_SD:
#endif

Error: You must add new CONFIG options using Kconfig
The following new ad-hoc CONFIG options were detected:
CONFIG_ITOP4412scripts/config_whitelist.txt comm: file 2 is not in sorted ordercomm -23 --nocheck-order ${suspects} ${ok} >${new_adhoc}

参考：

移植 u-boot-2020.07 到 iTOP-4412（一）地址无关码点灯_u012849539的博客-CSDN博客

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