在上一篇中了解了 VGA 的时序（VGA 时序分析），这里可以使用 Verilog 写一个 VGA 的时序，那么需要控制:

HSYNC

VSYNC

RGB

信号首先查看原理图：

对应到芯片管脚的：

HSYNC---P123

VSYNC---P124

VGA_R---P26

VGA_G---P22

VGA_B---P23

所以管脚约束 ucf 文件为：

##########################################################
#Clock&Rst
NET "ext_clk_25m" LOC = P23;
NET "ext_clk_25m" IOSTANDARD = LVCMOS33;
NET "ext_rst_n" LOC = P24;
NET "ext_rst_n" IOSTANDARD = LVCMOS33;##########################################################
#VGA interface
NET "vga_r"           LOC=P26   | IOSTANDARD = LVCMOS33;
NET "vga_g"           LOC=P22   | IOSTANDARD = LVCMOS33;
NET "vga_b"           LOC=P21   | IOSTANDARD = LVCMOS33;
NET "vga_hsy"     LOC=P123   | IOSTANDARD = LVCMOS33;
NET "vga_vsy"     LOC=P124   | IOSTANDARD = LVCMOS33;

由于不同的 VGA 分辨率对应的本地时钟不一样，为了支持多个分辨率，那么需要配置 PLL 输出为多个不同的时钟，顶层文件负责连接 PLL 和 VGA 模块：

时钟信号通过 PLL 直接给到 vga 模块，同时 LOCKED 信号作为 VGA 模块的复位信号：

顶层文件的实现如上述所示：

module sp6(input ext_clk_25m,    //外部输入25MHz时钟信号input ext_rst_n, //外部输入复位信号，低电平有效output vga_r,    //VGA显示色彩Routput vga_g, //VGA显示色彩Goutput vga_b, //VGA显示色彩Boutput vga_hsy,   //VGA显示行同步信号output vga_vsy  //VGA显示场同步信号);                                                  //-------------------------------------
//PLL例化
wire clk_25m;   //PLL输出25MHz时钟
wire clk_50m;   //PLL输出50MHz时钟
wire clk_65m;   //PLL输出65MHz时钟
wire clk_108m;  //PLL输出108MHz时钟
wire clk_130m;  //PLL输出130MHz时钟
wire sys_rst_n; //PLL输出的locked信号，作为FPGA内部的复位信号，低电平复位，高电平正常工作pll_controller uut_pll_controller(// Clock in ports.CLK_IN1(ext_clk_25m),      // IN// Clock out ports.CLK_OUT1(clk_12m5),     // OUT.CLK_OUT2(clk_25m),     // OUT.CLK_OUT3(clk_50m),     // OUT.CLK_OUT4(clk_65m),     // OUT.CLK_OUT5(clk_108m),     // OUT.CLK_OUT6(clk_130m),     // OUT// Status and control signals.RESET(~ext_rst_n),// IN.LOCKED(sys_rst_n));      // OUT     //-------------------------------------
//VGA驱动时序产生，显示Color barvga_controller    uut_vga_controller(.clk_25m(clk_25m),.clk_50m(clk_50m),.clk_65m(clk_65m),.clk_108m(clk_108m),.clk_130m(clk_130m),.rst_n(sys_rst_n),.vga_r(vga_r),.vga_g(vga_g),.vga_b(vga_b),.vga_hsy(vga_hsy),.vga_vsy(vga_vsy));

vga_controller 的实现为：

module vga_controller(input clk_25m, //PLL输出25MHz时钟input clk_50m,    //PLL输出50MHz时钟input clk_65m,    //PLL输出65MHz时钟input clk_108m,   //PLL输出108MHz时钟input clk_130m,  //PLL输出130MHz时钟input rst_n, //复位信号，低电平有效output vga_r,    //VGA显示色彩Routput vga_g, //VGA显示色彩Goutput vga_b, //VGA显示色彩Boutput reg vga_hsy,   //VGA显示行同步信号output reg vga_vsy  //VGA显示场同步信号);//-----------------------------------------------------------
wire clk;//-----------------------------------------------------------
//`define VGA_640_480
//`define VGA_800_600
`define VGA_1024_768
//`define VGA_1280_960
//`define VGA_1280_1024
//`define VGA_1920_1080//-----------------------------------------------------------
`ifdef VGA_640_480//VGA Timing 640*480 & 25MHz & 60Hzassign clk = clk_25m;parameter VGA_HTT = 12'd800-12'd1;   //Hor Total Timeparameter VGA_HST = 12'd96;       //Hor Sync  Timeparameter VGA_HBP = 12'd48;//+12'd16;       //Hor Back Porchparameter VGA_HVT = 12'd640;  //Hor Valid Timeparameter VGA_HFP = 12'd16;       //Hor Front Porchparameter VGA_VTT = 12'd525-12'd1;  //Ver Total Timeparameter VGA_VST = 12'd2;        //Ver Sync Timeparameter VGA_VBP = 12'd33;//-12'd4;      //Ver Back Porchparameter VGA_VVT = 12'd480;  //Ver Valid Timeparameter VGA_VFP = 12'd10;       //Ver Front Porchparameter VGA_CORBER = 12'd80;   //8等分做Color bar显示
`endif`ifdef VGA_800_600//VGA Timing 800*600 & 50MHz & 72Hzassign clk = clk_50m;parameter VGA_HTT = 12'd1040-12'd1;   //Hor Total Timeparameter VGA_HST = 12'd120;      //Hor Sync  Timeparameter VGA_HBP = 12'd64;       //Hor Back Porchparameter VGA_HVT = 12'd800;  //Hor Valid Timeparameter VGA_HFP = 12'd56;       //Hor Front Porchparameter VGA_VTT = 12'd666-12'd1;  //Ver Total Timeparameter VGA_VST = 12'd6;        //Ver Sync Timeparameter VGA_VBP = 12'd23;        //Ver Back Porchparameter VGA_VVT = 12'd600;  //Ver Valid Timeparameter VGA_VFP = 12'd37;       //Ver Front Porchparameter VGA_CORBER = 12'd100;  //8等分做Color bar显示
`endif`ifdef VGA_1024_768//VGA Timing 1024*768 & 65MHz & 60Hzassign clk = clk_65m;parameter VGA_HTT = 12'd1344-12'd1; //Hor Total Timeparameter VGA_HST = 12'd136;      //Hor Sync  Timeparameter VGA_HBP = 12'd160;      //Hor Back Porchparameter VGA_HVT = 12'd1024; //Hor Valid Timeparameter VGA_HFP = 12'd24;       //Hor Front Porchparameter VGA_VTT = 12'd806-12'd1;  //Ver Total Timeparameter VGA_VST = 12'd6;        //Ver Sync Timeparameter VGA_VBP = 12'd29;        //Ver Back Porchparameter VGA_VVT = 12'd768;  //Ver Valid Timeparameter VGA_VFP = 12'd3;        //Ver Front Porchparameter VGA_CORBER = 12'd128;  //8等分做Color bar显示
`endif`ifdef VGA_1280_960//VGA Timing 1280*1024 & 108MHz & 60Hzassign clk = clk_108m;parameter VGA_HTT = 12'd1800-12'd1;  //Hor Total Timeparameter VGA_HST = 12'd112;      //Hor Sync  Timeparameter VGA_HBP = 12'd312;      //Hor Back Porchparameter VGA_HVT = 12'd1280; //Hor Valid Timeparameter VGA_HFP = 12'd96;       //Hor Front Porchparameter VGA_VTT = 12'd1000-12'd1; //Ver Total Timeparameter VGA_VST = 12'd3;        //Ver Sync Timeparameter VGA_VBP = 12'd36;        //Ver Back Porchparameter VGA_VVT = 12'd960;  //Ver Valid Timeparameter VGA_VFP = 12'd1;        //Ver Front Porchparameter VGA_CORBER = 12'd160;  //8等分做Color bar显示
`endif`ifdef VGA_1280_1024//VGA Timing 1280*1024 & 108MHz & 60Hzassign clk = clk_108m;parameter VGA_HTT = 12'd1688-12'd1; //Hor Total Timeparameter VGA_HST = 12'd112;      //Hor Sync  Timeparameter VGA_HBP = 12'd248;      //Hor Back Porchparameter VGA_HVT = 12'd1280; //Hor Valid Timeparameter VGA_HFP = 12'd48;       //Hor Front Porchparameter VGA_VTT = 12'd1066-12'd1; //Ver Total Timeparameter VGA_VST = 12'd3;        //Ver Sync Timeparameter VGA_VBP = 12'd38;        //Ver Back Porchparameter VGA_VVT = 12'd1024; //Ver Valid Timeparameter VGA_VFP = 12'd1;        //Ver Front Porchparameter VGA_CORBER = 12'd160;  //8等分做Color bar显示
`endif`ifdef VGA_1920_1080//VGA Timing 1920*1080 & 130MHz & 60Hzassign clk = clk_130m;parameter VGA_HTT = 12'd2000-12'd1; //Hor Total Timeparameter VGA_HST = 12'd12;       //Hor Sync  Timeparameter VGA_HBP = 12'd40;       //Hor Back Porchparameter VGA_HVT = 12'd1920; //Hor Valid Timeparameter VGA_HFP = 12'd28;       //Hor Front Porchparameter VGA_VTT = 12'd1105-12'd1; //Ver Total Timeparameter VGA_VST = 12'd4;        //Ver Sync Timeparameter VGA_VBP = 12'd18;        //Ver Back Porchparameter VGA_VVT = 12'd1080; //Ver Valid Timeparameter VGA_VFP = 12'd3;        //Ver Front Porchparameter VGA_CORBER = 12'd240;  //8等分做Color bar显示
`endif//-----------------------------------------------------------//x和y坐标计数器
reg[11:0] xcnt;
reg[11:0] ycnt;always @(posedge clk or negedge rst_n)if(!rst_n) xcnt <= 12'd0;else if(xcnt >= VGA_HTT) xcnt <= 12'd0;else xcnt <= xcnt+1'b1;always @(posedge clk or negedge rst_n)if(!rst_n) ycnt <= 12'd0;else if(xcnt == VGA_HTT) beginif(ycnt >= VGA_VTT) ycnt <= 12'd0;else ycnt <= ycnt+1'b1;endelse ;//-----------------------------------------------------------//行、场同步信号生成
always @(posedge clk or negedge rst_n)if(!rst_n) vga_hsy <= 1'b0;else if(xcnt < VGA_HST) vga_hsy <= 1'b1;else vga_hsy <= 1'b0;always @(posedge clk or negedge rst_n)if(!rst_n) vga_vsy <= 1'b0;else if(ycnt < VGA_VST) vga_vsy <= 1'b1;else vga_vsy <= 1'b0;  //-----------------------------------------------------------   //显示有效区域标志信号生成
reg vga_valid;  //显示区域内，该信号高电平always @(posedge clk or negedge rst_n)if(!rst_n) vga_valid <= 1'b0;else if((xcnt >= (VGA_HST+VGA_HBP)) && (xcnt < (VGA_HST+VGA_HBP+VGA_HVT))&& (ycnt >= (VGA_VST+VGA_VBP)) && (ycnt < (VGA_VST+VGA_VBP+VGA_VVT)))vga_valid <= 1'b1;else vga_valid <= 1'b0;//-----------------------------------------------------------//显示色彩生产逻辑
reg vga_rdb;    //R色彩
reg vga_gdb;    //G色彩
reg vga_bdb;    //B色彩always @(posedge clk or negedge rst_n)if(!rst_n) beginvga_rdb <= 1'b0;vga_gdb <= 1'b0;vga_bdb <= 1'b0;endelse if(xcnt == (VGA_HST+VGA_HBP)) begin   //显示第一行为绿色vga_rdb <= 1'b0;vga_gdb <= 1'b1;vga_bdb <= 1'b0;       endelse if(xcnt == (VGA_HST+VGA_HBP+VGA_HVT-1'b1)) begin   //显示最后一行为绿色vga_rdb <= 1'b0;vga_gdb <= 1'b1;vga_bdb <= 1'b0;      endelse if(ycnt == (VGA_VST+VGA_VBP)) begin  //显示第一列为绿色vga_rdb <= 1'b0;vga_gdb <= 1'b1;vga_bdb <= 1'b0;           endelse if(ycnt == (VGA_VST+VGA_VBP+VGA_VVT-1'b1)) begin   //显示最后一列为绿色vga_rdb <= 1'b0;vga_gdb <= 1'b1;vga_bdb <= 1'b0;      endelse if(xcnt <= (VGA_HST+VGA_HBP+VGA_CORBER)) begin        //显示第1个Color barvga_rdb <= 1'b0;vga_gdb <= 1'b0;vga_bdb <= 1'b0; endelse if(xcnt <= (VGA_HST+VGA_HBP+VGA_CORBER+VGA_CORBER)) begin        //显示第2个Color barvga_rdb <= 1'b0;vga_gdb <= 1'b0;vga_bdb <= 1'b1;end  else if(xcnt <= (VGA_HST+VGA_HBP+VGA_CORBER+VGA_CORBER+VGA_CORBER)) begin       //显示第3个Color barvga_rdb <= 1'b0;vga_gdb <= 1'b1;vga_bdb <= 1'b0;end  else if(xcnt <= (VGA_HST+VGA_HBP+VGA_CORBER+VGA_CORBER+VGA_CORBER+VGA_CORBER)) begin       //显示第4个Color barvga_rdb <= 1'b0;vga_gdb <= 1'b1;vga_bdb <= 1'b1;end  else if(xcnt <= (VGA_HST+VGA_HBP+VGA_CORBER+VGA_CORBER+VGA_CORBER+VGA_CORBER+VGA_CORBER)) begin       //显示第5个Color barvga_rdb <= 1'b1;vga_gdb <= 1'b0;vga_bdb <= 1'b0; end else if(xcnt <= (VGA_HST+VGA_HBP+VGA_CORBER+VGA_CORBER+VGA_CORBER+VGA_CORBER+VGA_CORBER+VGA_CORBER)) begin       //显示第6个Color barvga_rdb <= 1'b1;vga_gdb <= 1'b0;vga_bdb <= 1'b1; endelse if(xcnt <= (VGA_HST+VGA_HBP+VGA_CORBER+VGA_CORBER+VGA_CORBER+VGA_CORBER+VGA_CORBER+VGA_CORBER+VGA_CORBER)) begin        //显示第7个Color barvga_rdb <= 1'b1;vga_gdb <= 1'b1;vga_bdb <= 1'b0; endelse if(xcnt <= (VGA_HST+VGA_HBP+VGA_CORBER+VGA_CORBER+VGA_CORBER+VGA_CORBER+VGA_CORBER+VGA_CORBER+VGA_CORBER+VGA_CORBER)) begin        //显示第8个Color barvga_rdb <= 1'b1;vga_gdb <= 1'b1;vga_bdb <= 1'b1; endelse beginvga_rdb <= 1'b0;vga_gdb <= 1'b0;vga_bdb <= 1'b0;    endassign vga_r = vga_valid ? vga_rdb:1'b0;
assign vga_g = vga_valid ? vga_gdb:1'b0;
assign vga_b = vga_valid ? vga_bdb:1'b0;  endmodule

进行了指定时钟下的时序计数并进行 I/O 的控制；

实际情况如下：

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