RISC-V 实现整数运算指令（Part 2）

验证R型运算指令

源代码

package alu_defs;enum logic [3:0] {ADD = 4'b0001,SUB = 4'b0010,AND = 4'b0011,OR  = 4'b0100,XOR = 4'b0101,SRA = 4'b0110,SLL = 4'b0111,SRL = 4'b1000} aluop;endpackage`default_nettype none
// --------------------------------------------------------------------
// CPU 模块
// --------------------------------------------------------------------
module CPU#(parameter DATAWIDTH = 32,parameter ADDRWIDTH = 32)
(input  wire iCPU_Reset,input  wire iCPU_Clk,// 指令存储器接口output wire [ADDRWIDTH-1:0] oIM_Addr,   //指令存储器地址input  wire [DATAWIDTH-1:0] iIM_Data,   //指令存储器数据// 数据存储器接口input  wire [DATAWIDTH-1:0] iReadData,  //数据存储器读数据output wire [DATAWIDTH-1:0] oWriteData, //数据存储器写数据output wire [ADDRWIDTH-1:0] oAB,        //数据存储器地址output wire oWR,                        //数据存储器写使能// 连接调试器的信号output wire [ADDRWIDTH-1:0] oCurrent_PC,output wire oFetch,input  wire iScanClk,input  wire iScanIn,output wire oScanOut,input  wire [1:0] iScanCtrl
);/** The input port is replaced with an internal signal **/wire   clk   = iCPU_Clk;wire   reset = iCPU_Reset;// Instruction parts//PClogic [31:0] pc, nextPC;logic [31:0] instruction; // instruction codeassign nextPC = pc + 4;   /*-TODO 目前仅支持PC+4，增加分支指令时需修改 -*/// DataRegDataReg #(32) pcreg(.iD(nextPC), .oQ(pc), .Clk(clk), .Reset(reset), .Load(1'b1));assign oIM_Addr = pc;         // 连接指令存储器的地址端口assign instruction = iIM_Data;// 连接指令存储器的数据端口// Instruction decodelogic [6:0] opcode;logic [2:0] funct3;logic [6:0] funct7;logic [4:0] ra1,ra2,wa;assign funct7 = instruction[31:25];assign ra2    = instruction[24:20];assign ra1    = instruction[19:15];assign funct3 = instruction[14:12];assign wa     = instruction[11:7];assign opcode = instruction[6:0];// Control unitlogic cRegWrite;logic [3:0] aluOp;logic [4:0] cImm_type;  //{J,U,B,S,I}logic immToAlu;Controller controller(.iOpcode(opcode),.iFunct3(funct3),.iFunct7(funct7),/*-TODO 随着指令的增加，相应添加端口信号 -*/.oRegWrite(cRegWrite),.oImm_type(cImm_type),.oALUop(aluOp),.oImmToAlu(immToAlu));// Immediate data generationlogic [31:0] immData;ImmGen  immGen(.iInstruction(instruction[31:7]),.iImm_type(cImm_type),.oImmediate(immData));// Register filelogic [31:0] regWriteData, regReadData1, regReadData2;RegisterFile #(32) regFile(.Clk(clk),.iWE(cRegWrite), .iWA(wa), .iWD(regWriteData),.iRA1(ra1), .oRD1(regReadData1),.iRA2(ra2), .oRD2(regReadData2));assign regWriteData = aluOut; /*-目前仅支持将ALU运算结果写入寄存器堆，TODO：增加Load类指令时需修改 -*///MultiChooseOnelogic [31:0] result;Two2One two2one(.iImmToALU(immToAlu),.iImm(immData),.iRd2(regReadData2),.oResult(result));// ALUlogic [31:0] aluOut;ALU alu(.iX(regReadData1),.iY(result),.iALUop(aluOp),.oF(aluOut));/*-TODO 连接数据存储器 -*///---------------------- 送给调试器的变量 ------------------------////送给调试器的观察信号，需要与虚拟面板的信号框相对应struct packed{/*-TODO 在这里添加观察信号的类型 -*/logic ImmToAlu;               //对应虚拟元件WS3logic [3:0] ALUop;            //对应虚拟元件WS2logic RegWrite;               //对应虚拟元件WS1logic [4:0] ImmType;          //对应虚拟元件WS0}ws;always_comb begin/*-【注意】添加观察信号类型后须关联相应变量！-*/ws.ImmToAlu = immToAlu;       //对应虚拟元件WS3ws.ALUop = aluOp;             //对应虚拟元件WS2ws.RegWrite = cRegWrite;      //对应虚拟元件WS1ws.ImmType = cImm_type;       //对应虚拟元件WS0end//送给调试器的观察变量，需要与虚拟面板的数据框相对应struct packed{/*-TODO 在这里添加观察数据的类型 -*/logic [31:0] regReadData2; //对应虚拟元件WD9logic [31:0] aluOut;       //对应虚拟元件WD8logic [31:0] immData;      //对应虚拟元件WD7logic [31:0] regReadData1; //对应虚拟元件WD6logic [4:0]  ra2;          //对应虚拟元件WD5，5位logic [4:0]  ra1;          //对应虚拟元件WD4，5位logic [4:0]  wa;           //对应虚拟元件WD3，5位logic [31:0] instruction;  //对应虚拟元件WD2logic [31:0] pc;           //对应虚拟元件WD1logic [31:0] nextPC;       //对应虚拟元件WD0}wd;always_comb begin/*-【注意】添加观察数据类型后须关联相应变量！-*/wd.regReadData2 = regReadData2; //对应虚拟元件WD9wd.aluOut       = aluOut;       //对应虚拟元件WD8wd.immData      = immData;      //对应虚拟元件WD7wd.regReadData1 = regReadData1; //对应虚拟元件WD6wd.ra2          = ra2;          //对应虚拟元件WD5，5位wd.ra1          = ra1;          //对应虚拟元件WD4，5位wd.wa           = wa;           //对应虚拟元件WD3，5位wd.instruction  = instruction;  //对应虚拟元件WD2wd.pc           = pc;           //对应虚拟元件WD1wd.nextPC       = nextPC;       //对应虚拟元件WD0end// 调试器部分，请勿修改！WatchChain #(.DATAWIDTH($bits(ws)+$bits(wd))) WatchChain_inst(.DataIn({ws,wd}),.ScanIn(iScanIn),.ScanOut(oScanOut),.ShiftDR(iScanCtrl[1]),.CaptureDR(iScanCtrl[0]),.TCK(iScanClk));assign oCurrent_PC = pc;assign oFetch = 1'b1;endmodule// --------------------------------------------------------------------
// Controller模块
// --------------------------------------------------------------------
module Controller(input  logic [6:0] iOpcode,input  logic [2:0] iFunct3,input  logic [6:0] iFunct7,/*- TODO：扩充指令时在这里增加端口 -*/output  logic oImmToAlu,output logic [3:0] oALUop,output logic oRegWrite,output logic [4:0] oImm_type   //对应五种类型：{J,U,B,S,I}
);always @ * begin/*- TODO：扩充指令时需修改 ...... -*///I型指令if (iOpcode==7'b0010011) beginoImmToAlu = 1'b1;oImm_type = 5'b00001;oRegWrite = 1'b1;if(iFunct3 == 3'b000) oALUop = 4'b0001;else if(iFunct3 == 3'b001) oALUop = 4'b0111;else if(iFunct3 == 3'b100) oALUop = 4'b0101;else if(iFunct3 == 3'b101 && iFunct7[5] == 1'b0) oALUop = 4'b1000;else if(iFunct3 == 3'b101 && iFunct7[5] == 1'b1) oALUop = 4'b0110;else if(iFunct3 == 3'b110) oALUop = 4'b0100;else if(iFunct3 == 3'b111) oALUop = 4'b0011;end//R型指令else if (iOpcode==7'b0110011) beginoImmToAlu = 1'b0;oImm_type = 5'b00000;oRegWrite = 1'b1;if(iFunct3 == 3'b000 && iFunct7[5] == 1'b0) oALUop = 4'b0001;else if(iFunct3 == 3'b000 && iFunct7[5] == 1'b1) oALUop = 4'b0010;else if(iFunct3 == 3'b001) oALUop = 4'b0111;else if(iFunct3 == 3'b100) oALUop = 4'b0101;else if(iFunct3 == 3'b101 && iFunct7[5] == 1'b0) oALUop = 4'b1000;else if(iFunct3 == 3'b101 && iFunct7[5] == 1'b1) oALUop = 4'b0110;else if(iFunct3 == 3'b110) oALUop = 4'b0100;else if(iFunct3 == 3'b111) oALUop = 4'b0011;endelse beginoALUop = 5'b00000;oImm_type = 5'b00000;oRegWrite = 1'b0;end
end
endmodule// --------------------------------------------------------------------
// 立即数生成模块
// --------------------------------------------------------------------
module ImmGen( //立即数生成input  logic [4:0]  iImm_type,   //{J,U,B,S,I}input  logic [31:7] iInstruction,output logic [31:0] oImmediate
);
/*- TODO：增加其他类型的立即数需修改。目前只有I型，所以并未区分Imm_type -*/
always_comb beginif(iImm_type == 5'b00001)oImmediate = {{20{iInstruction[31]}}, iInstruction[31:20]};else if(iImm_type == 5'b00000)oImmediate = 0;elseoImmediate = {32{1'bx}};
end
endmodule// --------------------------------------------------------------------
// ALU模块
// --------------------------------------------------------------------
module ALU
#(parameter N=32)
(input logic [N-1:0] iX, iY,input logic [3:0] iALUop,output logic [N-1:0] oF
);
wire [N-1:0] X = iX;
wire [N-1:0] Y = iY;
always_comb begincase (iALUop)4'b0001: oF = X + Y;4'b0010: oF = X - Y;4'b0011: oF = X & Y;4'b0100: oF = X | Y;4'b0101: oF = X ^ Y;4'b0110: oF = $signed(X) >>> Y;4'b0111: oF = X << Y;4'b1000: oF = X >> Y;default: oF = {32{1'bx}};endcase
end
endmodule// --------------------------------------------------------------------
// 三端口寄存器堆模块
// --------------------------------------------------------------------
module RegisterFile#(parameter DATAWIDTH = 32,parameter ADDRWIDTH = 5)
(input  logic  Clk,input  logic  iWE,input  logic  [4:0] iWA, iRA1, iRA2,moveBit,input  logic  [31:0] iWD,output logic  [31:0] oRD1, oRD2output logic  [31:0] oMove;
);
/*- TODO：...  -*/
localparam MEMDEPTH = 1<<ADDRWIDTH;
logic [DATAWIDTH-1:0] mem[0:MEMDEPTH-1];always_ff @(posedge Clk)
beginif(iWE)if(iWA!={ADDRWIDTH{1'b0}})mem[iWA] <= iWD;
endassign oRD1 = mem[iRA1];
assign oRD2 = mem[iRA2];
endmodule// --------------------------------------------------------------------
// DataReg模块
// --------------------------------------------------------------------
module DataReg
#(parameter N = 4)
(   output reg [N-1:0] oQ,input wire [N-1:0] iD,input wire Clk,input wire Load,input wire Reset
);
always @(posedge Clk or posedge Reset)
beginif (Reset)oQ <= 0;else if (Load)oQ <= iD;
end
endmodule// --------------------------------------------------------------------
// MultiChooseOne模块
// --------------------------------------------------------------------module Two2One
(input logic iImmToALU,input logic [31:0] iImm,input logic [31:0] iRd2,output logic [31:0] oResult
);
always_comb begincase(iImmToALU)1'b0 : oResult = iRd2;1'b1 : oResult = iImm;endcase
end
endmodule

Tips：如何快速生成测试指令？

当你自己的代码完成设计并编译成功后，如何验证你的功能模块是否设计的符合要求？

因为你的实验得分并不可能一蹴而就的达到100分，你也不知道哪些后台设置的测试数据没有通过，因为这是不公开的，也许是为了防止你以各种千奇百怪方式“骗分”，过来人都懂）

那么，我们可以从两方面来验证、调试、分析、追踪、定位错误

1. 以本题为例，你的输入指令应覆盖R型指令

2. 你可以在代码中添加数据观察窗口，这样你可以在运行指令过程中确保是你想要的结果，也就是指令应该运行的方向

如何快速生成指令覆盖R型指令？

工具：Ripes

GitHub - mortbopet/Ripes: A graphical processor simulator and assembly editor for the RISC-V ISAA graphical processor simulator and assembly editor for the RISC-V ISA - GitHub - mortbopet/Ripes: A graphical processor simulator and assembly editor for the RISC-V ISAhttps://github.com/mortbopet/Ripes 在左边输入R型指令，右边可自动生成我们需要的微指令（红方框），红方框后面那一列是微命令

然后，你可以将其填入实验平台的控制存储器，进行微单步运行

你可以参照下面的分析进行验证（绿色方框的结果你可以根据自己的知识储备计算，也可以利用手机上的计算器或者网页端在线计算器计算，选择一个你喜欢的即可）

如何添加数据观察窗口？

只需注意你在代码所添加的数据观察窗口应当和实验面板的数据一一对应即可（以ALUop为例，包括位宽、序号，不可少也不可多，不然会扰乱信号传递，增添不必要的麻烦）

关于序号，它的大小是从下往上递增，由上图可以看到ALUop处于2号位序

提交你的结果

实验系统已修复实验面板与个人中心的提交分数不一致的问题