UBOOT学习之DDR3

DDR3内存简介

- RAM
RAM随机存储器，可以随时进行读写操作，速度块，但是掉电以后数据会丢失。比如内存条、SDRAM、SRAM和DDR都是RAM,RAM一般用来保存程序数据、中间结果。

- ROM
ROM只读存储器，随着科技发展，ROM演变为FLASH,flash可以写操作，但是相对于读操作，效率低。例如手机配置“8G+128G”，8G指的就RAM,128G指的就是FLASH。EMMC、NAND Flash和UFS都属于ROM。总的来说，RAM读写速度快，但是掉电数据会丢失，价格昂贵，不易把内存做大，适合于CPU通信、保存程序数据；ROM读写速度慢，但是掉电数据也可以保存，价格便宜，容易把内存做大，适用于保存数据。

- SRAM简介

SRAM是Static Random-Access Memory（静态随机存储器）的简称，“静态”指的是只要上电数据就一直保存着，掉电数据丢失。单片机系统常用SRAM外扩RAM 。SRAM可以随意读取地址空间的任意数据，SRAM的地址总线和数据总线分开。

- SDRAM
SDRAM 全称是 Synchronous Dynamic Random Access Memory，翻译过来就是同步动态随机存储器，“同步”的意思是 SDRAM 工作需要时钟线，“动态”的意思是 SDRAM 中的数据需要不断的刷新来保证数据不会丢失，“随机”的意思就是可以读写任意地址的数据。，SDRAM是采用一个非常小的电容表示一个位数据，SRAM采用几个晶体管表示一个位。所以SRAM造价相比较会比较高，且不容易把内存做大。SDRAM造价相比较会比较低且容易把内存做大。但是SDRAM也有一个缺点，由于SDRAM表示位的电容很小，很容“漏电”，随着时间的变成，电荷会慢慢丢失，为了解决这个问题，需要隔一段时间对SDRAM进行刷新，就是定时的把数据读取出来，然后重新写入。

- DDR SDRAM
DDR 全称是 Double Data Rate SDRAM，也就是双倍速率 SDRAM，DDR SDRAM用行和列表示一个位，其内部结构如图，它有一个场效应管和一个电容表示一个位，行控制器控制场效应管的开关，列地址连接一个sense amps感知列的电平即读位，且连接了一个列控制器对电容进行充放电即写操作。所以行列操作只能表示一个位，我们称这个结构为一个memory array,一个memory array表示一位数据，如果我们要表示一个8位的数据哪？如图，我们通过把8个memory array叠加组成一个bank，同时控制8个并列的memory array就可实现8位数据读写，以此类推，如果表示16位数据，那就把16个memory array叠加成一个bank。一颗芯片有几个数据io，就说明这颗芯片的一个bank就有几个memory array组成。一颗芯片我们称之为device,一个device有若干个bank,假如一个device有8个bank。

开发板上的DDR的硬件连接

下图为北京讯为4412开发板的DDR硬件原理图，核心板一共有4块DDR，我这里只截取了一块的连接图。4412芯片有两个独立的DDR控制器，映射的内存大小都为1.5G，但是映射的地址范围不一样。核心板上两个组成一组，一组连接在soc的控制器1，另一组连接在soc的控制器2。

地址选择线

Xm1ADDR[15:0]为地址选择线，一组DDR也就是两颗DDR的地址选择线是公用的。

数据线

每颗DDR上有16根数据线。一组DDR也就是两颗DDR的数据线是并列的，刚好组成32位数据。

控制线
bank选择线、时钟信号线、行列使能信号线等统称为控制线，一组DDR的控制线是公用的。

bank选择线
Xm1BA0、Xm1BA1和Xm1BA2表示bank选择引脚，一颗芯片有8个bank，刚好三个引脚可是实现选择。
行列选择信号
CAS和RAS分别表示行列选择信号
写使能信号
we表示写使能信号，不使能表示读
片选信号
CS表示片选信号，低电平使能
时钟使能信号
CKE表示时钟使能信号
复位信号
reset表示复位信号，复位芯片
ODT
表示片上终端使能

uboot中DDR初始化源码的位置
…\cpu\arm_cortexa9\cpu_init_scp.s
三星4412数据手册初始化的ddr的流程：
Use the sequence given here to initialize DDR3 devices. Unless specified otherwise, these steps are mandatory.

Apply power. RESET# needs to be maintained for minimum 200us with stable power. CKE is pulled “Low”
anytime before RESET# being de-asserted (min. time 10ns)
If on die termination is required, enable PhyControl1.term_write_en, PhyControl1.term_read_en.
If ZQ calibration is required, disable PhyZQControl.ctrl_zq_mode_noterm and enable PhyZQControl.ctrl_zq_start so that the PHY automatically calibrates the I/Os to match the driving and termination impedance
by referencing resistor value of an external resistor and updates the matched value during auto re-fresh cycles.
Set the PhyControl0.ctrl_start_point and PhyControl0.ctrl_inc bit-fields to correct value according to clock
frequency. Set the PhyControl0.ctrl_dll_on bit-field to „1‟ to activate the PHY DLL.
DQS Cleaning: set the PhyControl1.ctrl_shiftc and PhyControl1.ctrl_offsetc bit-fields to the proper value
according to clock frequency, board delay and memory tDQSCK parameter.
Set the PhyControl0.ctrl_start bit-field to “1”.
Set the ConControl. At this moment, an auto refresh counter should be off.
Set the MemControl. At this moment, all power down modes and periodic ZQ(pzq_en) should be off.
Set the MemConfig0 register. If there are two external memory chips, also set the MemConfig1 register.
Set the PrechConfig and PwrdnConfig registers.
Set the TimingAref, TimingRow, TimingData and TimingPower registers according to memory AC parameters.
If QoS scheme is required, set the QosControl0~15 and QosConfig0~15 registers.
Wait for the PhyStatus0.ctrl_clock and PhyStatus0.ctrl_flock bit-fields to change to „1‟. Check whether PHY
DLL is locked.
PHY DLL compensates the changes of delay amount caused by PVT variation during memory operation.
Therefore, it should not be off for reliable operation. It can be off except runs at low frequency. If off mode is used,
set the PhyControl0.ctrl_force bit-field to the correct value according to the PhySta-tus0.ctrl_lock_value[9:2] bitfield for fix delay amount. Clear the PhyControl0.ctrl_dll_on bit-field to turn off PHY DLL.
Set the PhyControl1.fp_resync bit-field to „1‟ to update DLL information.
Set the PhyControl1.fp_resync bit-field to „0‟.
Confirm that after RESET# is de-asserted, 500 us have passed before CKE becomes active.
Confirm that clocks(CK, CK#) need to be started and stabilized for at least 10 ns or 5 tCK (which is larger)
before CKE goes active.
Issue a NOP command using the DirectCmd register to assert and to hold CKE to a logic high level.
Wait for tXPR(max(5nCK,tRFC(min)+10ns)) or set tXP to tXPR value before step 17. If the system set tXP to
tXPR, then the system must set tXP to proper value before normal memory operation.
Issue an EMRS2 command using the DirectCmd register to program the operating parameters. Dynamic ODT
should be disabled. A10 and A9 should be low.
Issue an EMRS3 command using the DirectCmd register to program the operating parameters.
Issue an EMRS command using the DirectCmd register to enable the memory DLL.
Issue a MRS command using the DirectCmd register to reset the memory DLL.
Issues a MRS command using the DirectCmd register to program the operating parameters without resetting
the memory DLL.
Issues a ZQINIT commands using the DirectCmd register.
If there are two external memory chips, perform steps 19 ~ 26 procedures for chip1 memory device.
Set the ConControl to turn on an auto refresh counter.
If power down modes or periodic ZQ(pzq_en) are required, set the MemControl register
翻译如下：
1、接通电源，复位引脚必须得保持200us直到电源稳定，然后时钟信号拉低至少得10ns
2、

#include <config.h>
#include <s5pc210.h>//#define SET_MIU@ MIU (Memory Interleaving Unit)
//#define MIU_LINEAR
//#define MIU_1BIT_INTERLEAVED
//#define MIU_2BIT_INTERLEAVED//#define MIU_1BIT_12_INTERLEAVED
//#define MIU_1BIT_7_INTERLEAVED
//#define MIU_2BIT_21_12_INTERLEAVED
#define MIU_2BIT_21_7_INTERLEAVED#define MEM_DLL#ifdef CONFIG_CLK_800_330_165
#define DRAM_CLK_330
#endif
#ifdef CONFIG_CLK_1000_200_200
#define DRAM_CLK_200
#endif
#ifdef CONFIG_CLK_1000_330_165
#define DRAM_CLK_330
#endif
#ifdef CONFIG_CLK_1000_400_200
#define DRAM_CLK_400
#endif/* add by cym 20130218 */
#define DMC_IVCONTROL   0xF0
wait_phy_state:ldr r1, [r0, #DMC_PHYSTATUS]tst r1, #(1<<2)beq wait_phy_statemov pc, lrdmc_delay:push {lr}
1:  subs r2, r2, #1bne 1bpop {pc}.globl mem_ctrl_asm_init_ddr3
mem_ctrl_asm_init_ddr3:push {lr}/*****************************************************************/
/*DREX0***********************************************************/
/*****************************************************************/ldr  r0, =APB_DMC_0_BASE ldr    r1, =0x0str    r1, [r0, #DMC_PHYCONTROL2]ldr   r1, =0x0str    r1, [r0, #0x24]ldr  r1, =0xE3855503str r1, [r0, #DMC_PHYZQCONTROL]ldr  r1, =0x71101008                str r1, [r0, #DMC_PHYCONTROL0]ldr   r1, =0x7110100A                str r1, [r0, #DMC_PHYCONTROL0]/*5. DQS Cleaning: set the PhyControl1.ctrl_shiftc and PhyControl1.ctrl_offsetc bit-fields to the proper valueaccording to clock frequency, board delay and memory tDQSCK parameter.*/ldr r1, =0x20000086                str r1, [r0, #DMC_PHYCONTROL1]/*6.Set the PhyControl0.ctrl_start bit-field to "1".*/ldr   r1, =0x71101008                str r1, [r0, #DMC_PHYCONTROL0]ldr   r1, =0x2000008E                str r1, [r0, #DMC_PHYCONTROL1]ldr   r1, =0x20000086                str r1, [r0, #DMC_PHYCONTROL1]ldr   r1, =0x2000008E                str r1, [r0, #DMC_PHYCONTROL1]ldr   r1, =0x20000086                str r1, [r0, #DMC_PHYCONTROL1]/*7. Set the ConControl. At this moment, an auto refresh counter should be off.*/ldr  r1, =0x0FFF30CAstr r1, [r0, #DMC_CONCONTROL]/*8. Set the MemControl. At this moment, all power down modes and periodic ZQ(pzq_en) should be off.*/ldr  r1, =0x00302600                str r1, [r0, #DMC_MEMCONTROL]/*9. Set the MemConfig0 register. If there are two external memory chips, also set the MemConfig1 register.*/#if 0ldr  r1, =0x40C01323    str r1, [r0, #DMC_MEMCONFIG0]
#else/* 4Gb * 4 *//*ldr r1, =0x40801323str r1, [r0, #DMC_MEMCONFIG0]*//* 2Gb * 8 */ldr r1, =0x40801333str r1, [r0, #DMC_MEMCONFIG0]#endifldr  r1, =(0x80000000 | CONFIG_IV_SIZE)str  r1, [r0, #DMC_IVCONTROL]/*10. Set the PrechConfig and PwrdnConfig registers.*/ldr   r1, =0x64000000            str r1, [r0, #DMC_PRECHCONFIG]ldr   r1, =0x9C4000FF            str r1, [r0, #DMC_PHYCONTROL0]/*11. Set the TimingAref, TimingRow, TimingData and TimingPower registers according to memory AC parameters.*/ldr r1, =0x000000BBstr r1, [r0, #DMC_TIMINGAREF] @TimingAref#ifdef CONFIG_EVT0_RECOMMENDldr   r1, =0x34A98691
#else   ldr r1, =0x34498691
#endifldr   r1, =0x7846654F/*0x4046654F*/str   r1, [r0, #DMC_TIMINGROW] @TimingRowldr r1, =0x46400506                    str r1, [r0, #DMC_TIMINGDATA] @TimingDataldr   r1, =0x52000A3C                    str r1, [r0, #DMC_TIMINGPOWER] @TimingPower/* minimum wait time is 100 nano seconds *//* 0x64: wait 250 nano seconds at ARMCLK 1.5 Ghz */mov   r2, #0x64bl dmc_delay
/*19. Issue a NOP command using the DirectCmd register to assert and to hold CKE to a logic high level*/ldr r1, =0x07000000                    str r1, [r0, #DMC_DIRECTCMD] /*20. Wait for tXPR(max(5nCK,tRFC(min)+10ns)) or set tXP to tXPR value before step 17. If the system set tXP to
tXPR, then the system must set tXP to proper value before normal memory operation.*//* minimum wait time is 200 micro seconds *//* 0x19000: wait 250 micro seconds at ARMCLK 1.5 Ghz */mov  r2, #0x19000bl dmc_delayldr r1, =0x00020000                    str r1, [r0, #DMC_DIRECTCMD]/* minimum wait time is 20 micro seconds *//* 0x2700: wait 25 micro seconds at ARMCLK 1.5 Ghz */mov r2, #0x2700bl dmc_delayldr  r1, =0x00030000                    str r1, [r0, #DMC_DIRECTCMD] /* minimum wait time is 1 micro seconds *//* 0x3f0: wait 2.5 micro seconds at ARMCLK 1.5 Ghz */mov r2, #0x3f0bl dmc_delayldr   r1, =0x00010000str r1, [r0, #DMC_DIRECTCMD] ldr    r1, =0x00000100                    str r1, [r0, #DMC_DIRECTCMD] mov    r2, #0x3f0bl dmc_delayldr   r1, =0x00000420                    str r1, [r0, #DMC_DIRECTCMD]mov r2, #0x3f0bl dmc_delay/*26. Issues a ZQINIT commands using the DirectCmd register*/ldr  r1, =0x0A000000str r1, [r0, #DMC_DIRECTCMD]mov r2, #0x3f0bl dmc_delay/*****************************************************************/
/*DREX1***********************************************************/
/*****************************************************************/ldr  r0, =APB_DMC_1_BASE ldr    r1, =0x0str    r1, [r0, #DMC_PHYCONTROL2]ldr   r1, =0x0str    r1, [r0, #0x24]ldr  r1, =0xE3855503str r1, [r0, #DMC_PHYZQCONTROL]ldr  r1, =0x71101008                str r1, [r0, #DMC_PHYCONTROL0]ldr   r1, =0x7110100A                str r1, [r0, #DMC_PHYCONTROL0]ldr   r1, =0x20000086                str r1, [r0, #DMC_PHYCONTROL1]ldr   r1, =0x71101008                str r1, [r0, #DMC_PHYCONTROL0]ldr   r1, =0x2000008E                str r1, [r0, #DMC_PHYCONTROL1]ldr   r1, =0x20000086                str r1, [r0, #DMC_PHYCONTROL1]ldr   r1, =0x2000008E                str r1, [r0, #DMC_PHYCONTROL1]ldr   r1, =0x20000086                str r1, [r0, #DMC_PHYCONTROL1]ldr   r1, =0x0FFF30CAstr r1, [r0, #DMC_CONCONTROL]ldr    r1, =0x00302600                str r1, [r0, #DMC_MEMCONTROL]
#if 0ldr    r1, =0x40C01323    str r1, [r0, #DMC_MEMCONFIG0]
#else/* 4Gb * 4 *//*ldr r1, =0x40801323str r1, [r0, #DMC_MEMCONFIG0]*//* 2Gb * 8 */ldr r1, =0x40801333str r1, [r0, #DMC_MEMCONFIG0]#endifldr  r1, =(0x80000000 | CONFIG_IV_SIZE)str  r1, [r0, #DMC_IVCONTROL]ldr r1, =0x64000000            str r1, [r0, #DMC_PRECHCONFIG]ldr   r1, =0x9C4000FF            str r1, [r0, #DMC_PHYCONTROL0]ldr   r1, =0x000000BBstr r1, [r0, #DMC_TIMINGAREF] @TimingAref#ifdef CONFIG_EVT0_RECOMMENDldr   r1, =0x34A98691
#else   ldr r1, =0x34498691
#endifldr   r1, =0x7846654F/*0x4046654F*/str   r1, [r0, #DMC_TIMINGROW] @TimingRowldr r1, =0x46400506                    str r1, [r0, #DMC_TIMINGDATA] @TimingDataldr   r1, =0x52000A3C                    str r1, [r0, #DMC_TIMINGPOWER] @TimingPower/* minimum wait time is 100 nano seconds *//* 0x64: wait 250 nano seconds at ARMCLK 1.5 Ghz */mov   r2, #0x64bl dmc_delayldr    r1, =0x07000000                    str r1, [r0, #DMC_DIRECTCMD] /* minimum wait time is 200 micro seconds *//* 0x19000: wait 250 micro seconds at ARMCLK 1.5 Ghz */mov r2, #0x19000bl dmc_delayldr r1, =0x00020000                    str r1, [r0, #DMC_DIRECTCMD]/* minimum wait time is 20 micro seconds *//* 0x2700: wait 25 micro seconds at ARMCLK 1.5 Ghz */mov r2, #0x2700bl dmc_delayldr  r1, =0x00030000                    str r1, [r0, #DMC_DIRECTCMD] /* minimum wait time is 1 micro seconds *//* 0x3f0: wait 2.5 micro seconds at ARMCLK 1.5 Ghz */mov r2, #0x3f0bl dmc_delayldr   r1, =0x00010000str r1, [r0, #DMC_DIRECTCMD] ldr    r1, =0x00000100                    str r1, [r0, #DMC_DIRECTCMD] mov    r2, #0x3f0bl dmc_delayldr   r1, =0x00000420                    str r1, [r0, #DMC_DIRECTCMD]mov r2, #0x3f0bl dmc_delayldr   r1, =0x0A000000str r1, [r0, #DMC_DIRECTCMD]mov r2, #0x3f0bl dmc_delay//以上为初始化memertry2ldr  r0, =APB_DMC_0_BASEldr r1, =0x7110100Aldr r2, =DMC_PHYCONTROL0str    r1, [r0, r2]ldr r1, =0x20000086ldr r2, =DMC_PHYCONTROL1str    r1, [r0, r2]ldr r1, =0x7110100Bldr r2, =DMC_PHYCONTROL0str    r1, [r0, r2]bl wait_phy_stateldr    r1, =0x2000008Eldr r2, =DMC_PHYCONTROL1str    r1, [r0, r2]ldr r1, =0x20000086ldr r2, =DMC_PHYCONTROL1str    r1, [r0, r2]bl wait_phy_stateldr    r0, =APB_DMC_1_BASEldr r1, =0x7110100Aldr r2, =DMC_PHYCONTROL0str    r1, [r0, r2]ldr r1, =0x20000086ldr r2, =DMC_PHYCONTROL1str    r1, [r0, r2]ldr r1, =0x7110100Bldr r2, =DMC_PHYCONTROL0str    r1, [r0, r2]bl wait_phy_stateldr    r1, =0x2000008Eldr r2, =DMC_PHYCONTROL1str    r1, [r0, r2]ldr r1, =0x20000086ldr r2, =DMC_PHYCONTROL1str    r1, [r0, r2]bl wait_phy_state/*28. Set the ConControl to turn on an auto refresh counter*/ldr   r0, =APB_DMC_0_BASEldr r2, =DMC_CONCONTROLldr r1, [r0, r2]orr r1, r1, #(1 << 5)str r1, [r0, r2]ldr  r0, =APB_DMC_1_BASEldr r2, =DMC_CONCONTROLldr r1, [r0, r2]orr r1, r1, #(1 << 5)str r1, [r0, r2]/*29. If power down modes or periodic ZQ(pzq_en) are required, set the MemControl register*/ldr  r0, =APB_DMC_0_BASEldr r2, =DMC_MEMCONTROLldr r1, [r0, r2]orr r1, r1, #((1 << 4) | (1 << 1) | (1 << 0))str  r1, [r0, r2]ldr r0, =APB_DMC_1_BASEldr r2, =DMC_MEMCONTROLldr r1, [r0, r2]orr r1, r1, #((1 << 4) | (1 << 1) | (1 << 0))str  r1, [r0, r2]pop {pc}
/* end modify */

## 未完待续