//第一个进程，同步时序always模块，格式化描述次态寄存器迁移到现态寄存器always @ (posedge clk or negedge rst_n)  //异步复位if(!rst_n)current_state <= IDLE;elsecurrent_state <= next_state;//注意，使用的是非阻塞赋值//第二个进程，组合逻辑always模块，描述状态转移条件判断always @ (current_state)   //电平触发beginnext_state = x;  //要初始化，使得系统复位后能进入正确的状态case(current_state)S1: if(...)next_state = S2;  //阻塞赋值
...endcaseend//第三个进程，同步时序always模块，格式化描述次态寄存器输出always @ (posedge clk or negedge rst_n)//初始化case(next_state)S1:out1 <= 1'b1;  //注意是非阻塞逻辑

S2:out2 <= 1'b1;default:...   //default的作用是免除综合工具综合出锁存器。endcaseend

01 module FSM(clk,rst,in,out);
02 input clk,rst;
03 input [7:0] in;
04 output [7:0] out;
05
06 parameter [1:0] //synopsys enum code
07 START = 2'd0,
08 SA = 1,
09 SB = 2,
10 SC = 3;
11
12 reg [1:0] CS,NS;
13 reg [7:0] tmp_out,out;
14
15 // state transfer
16 always @ (posedge clk or negedge rst)
17 begin
18 if (!rst) CS <= #1 START;
19 else      CS <= #1 NS;
20 end
21
22 // state transfer discipline
23 always @ (in or CS)
24 begin
25     NS = START;
26     case (CS)
27        START: case (in[7:6])
28                        2'b11: NS = SA;
29                        2'b00: NS = SC;
30                        default: NS = START;
31                        endcase
32        SA: if(in == 8'h3c) NS = SB;
33        SB: begin
34                 if (in == 8'h88) NS = SC;
35                 else             NS = START;
36                 end
37        SC: case(1'b1) //synopsys parallel_case full_case
38                 (in == 8'd0): NS = SA;
39                 (8'd0 < in && in < 8'd38): NS = START;
40                 (in > 8'd37): NS = SB;
41                   endcase
42        endcase
43 end
44
45 // temp out
46 always @ (CS)
47 begin
48     tmp_out = 8'bX;
49     case (CS)
50        START: tmp_out = 8'h00;
51        SA:   tmp_out = 8'h08;
52        SB:   tmp_out = 8'h18;
53        SC:   tmp_out = 8'h28;
54     endcase
55 end
56
57 // reg out
58 always @ (posedge clk or negedge rst)
59 begin
60     if (!rst) out <= #1 8'b0;
61     else     out <= #1 tmp_out;
62 end
63
64 endmodule