module nsync_fifo(input src_clk,input rst_n,input des_clk,input [8-1:0] fifo_data_in,input fifo_data_in_vaild,output reg  fifo_data_out_vaild,output [32-1:0] fifo_data_out);// write fifo
reg [1:0] buffer_wr_addr;
reg [32-1:0] temp_buffer;
always @(posedge src_clk or negedge rst_n)
beginif (!rst_n)beginbuffer_wr_addr <= 2'b00;endelsebeginbuffer_wr_addr <= (fifo_data_in_vaild) ? buffer_wr_addr + 1'b1 : buffer_wr_addr;end
endalways @(posedge src_clk)
beginif (fifo_data_in_vaild)begincase(buffer_wr_addr)2'd0:temp_buffer[0+:8] <=  fifo_data_in;2'd1:temp_buffer[8+:8] <=  fifo_data_in;2'd2:temp_buffer[16+:8] <=  fifo_data_in;2'd3:temp_buffer[24+:8] <=  fifo_data_in;endcaseend
end//gen wr_fifo signal && sync
reg fifo_wr;
reg fifo_wr_sync;
wire fifo_wr_clr;
reg fifo_wr_dfb;
always @(posedge src_clk)
beginfifo_wr <= (&buffer_wr_addr & fifo_data_in_vaild);
endassign fifo_wr_clr = !rst_n | fifo_wr_sync;  // feed backalways @(posedge fifo_wr or posedge fifo_wr_clr)
beginif (fifo_wr_clr)beginfifo_wr_dfb <= 1'b0;endelse beginfifo_wr_dfb <= 1'b1;end
endalways @(posedge des_clk)   // under des_clk sampled
beginfifo_wr_sync <= fifo_wr_dfb;
end// recv fifo
wire recv_fifo_wr;
reg [1:0] recv_fifo_wr_addr;assign recv_fifo_wr = fifo_wr_sync;
always @(posedge des_clk or rst_n)
beginif (!rst_n)beginrecv_fifo_wr_addr <= 2'b00;endelsebeginrecv_fifo_wr_addr <= (recv_fifo_wr) ? recv_fifo_wr_addr + 1'b1 : recv_fifo_wr_addr;end
end// sync fifo data
reg [32-1:0] fifo_0;
reg [32-1:0] fifo_1;
always @(posedge des_clk)
beginif (recv_fifo_wr)  // only buffer_wr_addr == 3 genbegincase (recv_fifo_wr_addr[0])1'b0 : fifo_0 <= temp_buffer;1'b1 : fifo_1 <= temp_buffer; endcaseend
end// read data from recv fifo
wire [1:0] recv_fifo_cnt;
wire recv_fifo_full;
wire recv_fifo_ready;
reg [1:0] recv_fifo_rd_addr;
assign recv_fifo_ready = | recv_fifo_cnt;
assign recv_fifo_full = recv_fifo_cnt[1]; // 2'b11 = 3
assign recv_fifo_cnt = recv_fifo_wr_addr - recv_fifo_rd_addr;always @(posedge des_clk or negedge rst_n)
beginif (!rst_n)beginrecv_fifo_rd_addr <= 2'b00;endelsebeginrecv_fifo_rd_addr <= (recv_fifo_ready) ? recv_fifo_rd_addr + 1'b1 : recv_fifo_rd_addr;end
endreg [32-1:0] recv_fifo_data;
always @(*)
begincase(recv_fifo_rd_addr[0])1'b0 : recv_fifo_data = fifo_0;1'b1 : recv_fifo_data = fifo_1;endcase
end// out
assign fifo_data_out = recv_fifo_data;
always @(posedge des_clk or negedge rst_n)
beginif(!rst_n)beginfifo_data_out_vaild <= 1'b0;endelsebeginfifo_data_out_vaild <= recv_fifo_ready;end
endendmodule