1 #define fpga_write(offset, data) *((volatile unsigned short int*)(CS0_BASE + (offset << 17))) = data

1 fpga_write(2,1234);

1 #define fpga_read(offset) *((volatile unsigned short int*)(CS0_BASE + (offset << 17)))

1 unsigned short int read_data;
2
3 read_data = fpga_read(2);

//fsmc read / write ep4ce6 demomodule fsmc(ab,   //addressdb,    //datawrn,    //wrrdn,    //rdresetn,    //resetncsn,    //csina,    //input data ainb,    //input data binc,    //input data cind,    //input data dine,    //input data einf,    //input data fing,    //input data ginh,    //input data houta,    //output data aoutb,    //output data aoutc,    //output data aoutd,    //output data aoute,    //output data aoutf,    //output data aoutg,    //output data aouth    //output data a
    );input[2:0]    ab;inout[15:0] db;input wrn;input rdn;input resetn;input csn;input [15:0] ina;input [15:0] inb;input [15:0] inc;input [15:0] ind;input [15:0] ine;input [15:0] inf;input [15:0] ing;input [15:0] inh;output reg [15:0] outa;output reg [15:0] outb;output reg [15:0] outc;output reg [15:0] outd;output reg [15:0] oute;output reg [15:0] outf;output reg [15:0] outg;output reg [15:0] outh;wire rd;wire wr;reg [15:0] indata;assign rd = !(csn & rdn); //get rd pulse  ____|~~~~|______assign wr = !(csn & wrn); //get wr pulse  ____|~~~~|______assign db = rd ? indata:16'hzzzz;//write data, 根据地址线选择八个空间写入，每个空间16位always @(negedge wr or negedge resetn)beginif(!resetn)beginouta <= 16'h0000;outb <= 16'h0000;outc <= 16'h0000;outd <= 16'h0000;oute <= 16'h0000;outf <= 16'h0000;outg <= 16'h0000;outh <= 16'h0000;end    else  begincase (ab)            3'b000:outa <= db;3'b001:outb <= db;3'b010:outc <= db;3'b011:outd <= db;3'b100:oute <= db;3'b101:outf <= db;3'b110:outg <= db;3'b111:outh <= db;default:;endcaseendend//read data 根据地址线选择8个空间读取，每个空间 16位always @(rd or !resetn)beginif(!resetn)indata <= 16'h0000;else  begincase (ab)3'b000:indata <= ina;3'b001:indata <= inb;3'b010:indata <= inc;3'b011:indata <= ind;3'b100:indata <= ine;3'b101:indata <= inf;3'b110:indata <= ing;3'b111:indata <= inh;default:;endcaseendendendmodule

for (i = 0; i < 65536; i++) {fpga_write(7, i);dat = fpga_read(0);if ((dat + i) != 65535) {errors++;}else success++;}